xref: /wlan-driver/fw-api/hw/qcn9224/v2/ofdma_trigger_details.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _OFDMA_TRIGGER_DETAILS_H_
27 #define _OFDMA_TRIGGER_DETAILS_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "mlo_sta_id_details.h"
32 #define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22
33 
34 #define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11
35 
36 
37 struct ofdma_trigger_details {
38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
39              uint32_t ax_trigger_source                                       :  1,
40                       rx_trigger_frame_user_source                            :  2,
41                       received_bandwidth                                      :  3,
42                       txop_duration_all_ones                                  :  1,
43                       eht_trigger_response                                    :  1,
44                       pre_rssi_comb                                           :  8,
45                       rssi_comb                                               :  8,
46                       rxpcu_pcie_l0_req_duration                              :  8;
47              uint32_t he_trigger_ul_ppdu_length                               :  5,
48                       he_trigger_ru_allocation                                :  8,
49                       he_trigger_dl_tx_power                                  :  5,
50                       he_trigger_ul_target_rssi                               :  5,
51                       he_trigger_ul_mcs                                       :  2,
52                       he_trigger_reserved                                     :  1,
53                       bss_color                                               :  6;
54              uint32_t trigger_type                                            :  4,
55                       lsig_response_length                                    : 12,
56                       cascade_indication                                      :  1,
57                       carrier_sense                                           :  1,
58                       bandwidth                                               :  2,
59                       cp_ltf_size                                             :  2,
60                       mu_mimo_ltf_mode                                        :  1,
61                       number_of_ltfs                                          :  3,
62                       stbc                                                    :  1,
63                       ldpc_extra_symbol                                       :  1,
64                       ap_tx_power_lsb_part                                    :  4;
65              uint32_t ap_tx_power_msb_part                                    :  2,
66                       packet_extension_a_factor                               :  2,
67                       packet_extension_pe_disambiguity                        :  1,
68                       spatial_reuse                                           : 16,
69                       doppler                                                 :  1,
70                       he_siga_reserved                                        :  9,
71                       reserved_3b                                             :  1;
72              uint32_t aid12                                                   : 12,
73                       ru_allocation                                           :  9,
74                       mcs                                                     :  4,
75                       dcm                                                     :  1,
76                       start_spatial_stream                                    :  3,
77                       number_of_spatial_stream                                :  3;
78              uint32_t target_rssi                                             :  7,
79                       coding_type                                             :  1,
80                       mpdu_mu_spacing_factor                                  :  2,
81                       tid_aggregation_limit                                   :  3,
82                       reserved_5b                                             :  1,
83                       prefered_ac                                             :  2,
84                       bar_control_ack_policy                                  :  1,
85                       bar_control_multi_tid                                   :  1,
86                       bar_control_compressed_bitmap                           :  1,
87                       bar_control_reserved                                    :  9,
88                       bar_control_tid_info                                    :  4;
89              uint32_t nr0_per_tid_info_reserved                               : 12,
90                       nr0_per_tid_info_tid_value                              :  4,
91                       nr0_start_seq_ctrl_frag_number                          :  4,
92                       nr0_start_seq_ctrl_start_seq_number                     : 12;
93              uint32_t nr1_per_tid_info_reserved                               : 12,
94                       nr1_per_tid_info_tid_value                              :  4,
95                       nr1_start_seq_ctrl_frag_number                          :  4,
96                       nr1_start_seq_ctrl_start_seq_number                     : 12;
97              uint32_t nr2_per_tid_info_reserved                               : 12,
98                       nr2_per_tid_info_tid_value                              :  4,
99                       nr2_start_seq_ctrl_frag_number                          :  4,
100                       nr2_start_seq_ctrl_start_seq_number                     : 12;
101              uint32_t nr3_per_tid_info_reserved                               : 12,
102                       nr3_per_tid_info_tid_value                              :  4,
103                       nr3_start_seq_ctrl_frag_number                          :  4,
104                       nr3_start_seq_ctrl_start_seq_number                     : 12;
105              uint32_t nr4_per_tid_info_reserved                               : 12,
106                       nr4_per_tid_info_tid_value                              :  4,
107                       nr4_start_seq_ctrl_frag_number                          :  4,
108                       nr4_start_seq_ctrl_start_seq_number                     : 12;
109              uint32_t nr5_per_tid_info_reserved                               : 12,
110                       nr5_per_tid_info_tid_value                              :  4,
111                       nr5_start_seq_ctrl_frag_number                          :  4,
112                       nr5_start_seq_ctrl_start_seq_number                     : 12;
113              uint32_t nr6_per_tid_info_reserved                               : 12,
114                       nr6_per_tid_info_tid_value                              :  4,
115                       nr6_start_seq_ctrl_frag_number                          :  4,
116                       nr6_start_seq_ctrl_start_seq_number                     : 12;
117              uint32_t nr7_per_tid_info_reserved                               : 12,
118                       nr7_per_tid_info_tid_value                              :  4,
119                       nr7_start_seq_ctrl_frag_number                          :  4,
120                       nr7_start_seq_ctrl_start_seq_number                     : 12;
121              uint32_t fb_segment_retransmission_bitmap                        :  8,
122                       reserved_14a                                            :  2,
123                       u_sig_puncture_pattern_encoding                         :  6,
124                       dot11be_puncture_bitmap                                 : 16;
125              uint32_t rx_chain_mask                                           :  8,
126                       rx_duration_field                                       : 16,
127                       scrambler_seed                                          :  7,
128                       rx_chain_mask_type                                      :  1;
129              struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
130              uint16_t normalized_pre_rssi_comb                                :  8,
131                       normalized_rssi_comb                                    :  8;
132              uint32_t sw_peer_id                                              : 16,
133                       response_tx_duration                                    : 16;
134              uint32_t ranging_trigger_subtype                                 :  4,
135                       tbr_trigger_common_info_79_68                           : 12,
136                       tbr_trigger_sound_reserved_20_12                        :  9,
137                       i2r_rep                                                 :  3,
138                       tbr_trigger_sound_reserved_25_24                        :  2,
139                       reserved_18a                                            :  1,
140                       qos_null_only_response_tx                               :  1;
141              uint32_t tbr_trigger_sound_sac                                   : 16,
142                       reserved_19a                                            :  8,
143                       u_sig_reserved2                                         :  5,
144                       reserved_19b                                            :  3;
145              uint32_t eht_special_aid12                                       : 12,
146                       phy_version                                             :  3,
147                       bandwidth_ext                                           :  2,
148                       eht_spatial_reuse                                       :  8,
149                       u_sig_reserved1                                         :  7;
150              uint32_t eht_trigger_special_user_info_71_40                     : 32;
151 #else
152              uint32_t rxpcu_pcie_l0_req_duration                              :  8,
153                       rssi_comb                                               :  8,
154                       pre_rssi_comb                                           :  8,
155                       eht_trigger_response                                    :  1,
156                       txop_duration_all_ones                                  :  1,
157                       received_bandwidth                                      :  3,
158                       rx_trigger_frame_user_source                            :  2,
159                       ax_trigger_source                                       :  1;
160              uint32_t bss_color                                               :  6,
161                       he_trigger_reserved                                     :  1,
162                       he_trigger_ul_mcs                                       :  2,
163                       he_trigger_ul_target_rssi                               :  5,
164                       he_trigger_dl_tx_power                                  :  5,
165                       he_trigger_ru_allocation                                :  8,
166                       he_trigger_ul_ppdu_length                               :  5;
167              uint32_t ap_tx_power_lsb_part                                    :  4,
168                       ldpc_extra_symbol                                       :  1,
169                       stbc                                                    :  1,
170                       number_of_ltfs                                          :  3,
171                       mu_mimo_ltf_mode                                        :  1,
172                       cp_ltf_size                                             :  2,
173                       bandwidth                                               :  2,
174                       carrier_sense                                           :  1,
175                       cascade_indication                                      :  1,
176                       lsig_response_length                                    : 12,
177                       trigger_type                                            :  4;
178              uint32_t reserved_3b                                             :  1,
179                       he_siga_reserved                                        :  9,
180                       doppler                                                 :  1,
181                       spatial_reuse                                           : 16,
182                       packet_extension_pe_disambiguity                        :  1,
183                       packet_extension_a_factor                               :  2,
184                       ap_tx_power_msb_part                                    :  2;
185              uint32_t number_of_spatial_stream                                :  3,
186                       start_spatial_stream                                    :  3,
187                       dcm                                                     :  1,
188                       mcs                                                     :  4,
189                       ru_allocation                                           :  9,
190                       aid12                                                   : 12;
191              uint32_t bar_control_tid_info                                    :  4,
192                       bar_control_reserved                                    :  9,
193                       bar_control_compressed_bitmap                           :  1,
194                       bar_control_multi_tid                                   :  1,
195                       bar_control_ack_policy                                  :  1,
196                       prefered_ac                                             :  2,
197                       reserved_5b                                             :  1,
198                       tid_aggregation_limit                                   :  3,
199                       mpdu_mu_spacing_factor                                  :  2,
200                       coding_type                                             :  1,
201                       target_rssi                                             :  7;
202              uint32_t nr0_start_seq_ctrl_start_seq_number                     : 12,
203                       nr0_start_seq_ctrl_frag_number                          :  4,
204                       nr0_per_tid_info_tid_value                              :  4,
205                       nr0_per_tid_info_reserved                               : 12;
206              uint32_t nr1_start_seq_ctrl_start_seq_number                     : 12,
207                       nr1_start_seq_ctrl_frag_number                          :  4,
208                       nr1_per_tid_info_tid_value                              :  4,
209                       nr1_per_tid_info_reserved                               : 12;
210              uint32_t nr2_start_seq_ctrl_start_seq_number                     : 12,
211                       nr2_start_seq_ctrl_frag_number                          :  4,
212                       nr2_per_tid_info_tid_value                              :  4,
213                       nr2_per_tid_info_reserved                               : 12;
214              uint32_t nr3_start_seq_ctrl_start_seq_number                     : 12,
215                       nr3_start_seq_ctrl_frag_number                          :  4,
216                       nr3_per_tid_info_tid_value                              :  4,
217                       nr3_per_tid_info_reserved                               : 12;
218              uint32_t nr4_start_seq_ctrl_start_seq_number                     : 12,
219                       nr4_start_seq_ctrl_frag_number                          :  4,
220                       nr4_per_tid_info_tid_value                              :  4,
221                       nr4_per_tid_info_reserved                               : 12;
222              uint32_t nr5_start_seq_ctrl_start_seq_number                     : 12,
223                       nr5_start_seq_ctrl_frag_number                          :  4,
224                       nr5_per_tid_info_tid_value                              :  4,
225                       nr5_per_tid_info_reserved                               : 12;
226              uint32_t nr6_start_seq_ctrl_start_seq_number                     : 12,
227                       nr6_start_seq_ctrl_frag_number                          :  4,
228                       nr6_per_tid_info_tid_value                              :  4,
229                       nr6_per_tid_info_reserved                               : 12;
230              uint32_t nr7_start_seq_ctrl_start_seq_number                     : 12,
231                       nr7_start_seq_ctrl_frag_number                          :  4,
232                       nr7_per_tid_info_tid_value                              :  4,
233                       nr7_per_tid_info_reserved                               : 12;
234              uint32_t dot11be_puncture_bitmap                                 : 16,
235                       u_sig_puncture_pattern_encoding                         :  6,
236                       reserved_14a                                            :  2,
237                       fb_segment_retransmission_bitmap                        :  8;
238              uint32_t rx_chain_mask_type                                      :  1,
239                       scrambler_seed                                          :  7,
240                       rx_duration_field                                       : 16,
241                       rx_chain_mask                                           :  8;
242              uint32_t normalized_rssi_comb                                    :  8,
243                       normalized_pre_rssi_comb                                :  8;
244              struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
245              uint32_t response_tx_duration                                    : 16,
246                       sw_peer_id                                              : 16;
247              uint32_t qos_null_only_response_tx                               :  1,
248                       reserved_18a                                            :  1,
249                       tbr_trigger_sound_reserved_25_24                        :  2,
250                       i2r_rep                                                 :  3,
251                       tbr_trigger_sound_reserved_20_12                        :  9,
252                       tbr_trigger_common_info_79_68                           : 12,
253                       ranging_trigger_subtype                                 :  4;
254              uint32_t reserved_19b                                            :  3,
255                       u_sig_reserved2                                         :  5,
256                       reserved_19a                                            :  8,
257                       tbr_trigger_sound_sac                                   : 16;
258              uint32_t u_sig_reserved1                                         :  7,
259                       eht_spatial_reuse                                       :  8,
260                       bandwidth_ext                                           :  2,
261                       phy_version                                             :  3,
262                       eht_special_aid12                                       : 12;
263              uint32_t eht_trigger_special_user_info_71_40                     : 32;
264 #endif
265 };
266 
267 
268 
269 
270 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET                              0x0000000000000000
271 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB                                 0
272 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB                                 0
273 #define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK                                0x0000000000000001
274 
275 
276 
277 
278 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET                   0x0000000000000000
279 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB                      1
280 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB                      2
281 #define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK                     0x0000000000000006
282 
283 
284 
285 
286 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET                             0x0000000000000000
287 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB                                3
288 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB                                5
289 #define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK                               0x0000000000000038
290 
291 
292 
293 
294 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET                         0x0000000000000000
295 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB                            6
296 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB                            6
297 #define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK                           0x0000000000000040
298 
299 
300 
301 
302 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET                           0x0000000000000000
303 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB                              7
304 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB                              7
305 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK                             0x0000000000000080
306 
307 
308 
309 
310 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET                                  0x0000000000000000
311 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB                                     8
312 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB                                     15
313 #define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK                                    0x000000000000ff00
314 
315 
316 
317 
318 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET                                      0x0000000000000000
319 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB                                         16
320 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB                                         23
321 #define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK                                        0x0000000000ff0000
322 
323 
324 
325 
326 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET                     0x0000000000000000
327 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB                        24
328 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB                        31
329 #define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK                       0x00000000ff000000
330 
331 
332 
333 
334 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET                      0x0000000000000000
335 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB                         32
336 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB                         36
337 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK                        0x0000001f00000000
338 
339 
340 
341 
342 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET                       0x0000000000000000
343 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB                          37
344 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB                          44
345 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK                         0x00001fe000000000
346 
347 
348 
349 
350 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET                         0x0000000000000000
351 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB                            45
352 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB                            49
353 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK                           0x0003e00000000000
354 
355 
356 
357 
358 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET                      0x0000000000000000
359 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB                         50
360 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB                         54
361 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK                        0x007c000000000000
362 
363 
364 
365 
366 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET                              0x0000000000000000
367 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB                                 55
368 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB                                 56
369 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK                                0x0180000000000000
370 
371 
372 
373 
374 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET                            0x0000000000000000
375 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB                               57
376 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB                               57
377 #define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK                              0x0200000000000000
378 
379 
380 
381 
382 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET                                      0x0000000000000000
383 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB                                         58
384 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB                                         63
385 #define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK                                        0xfc00000000000000
386 
387 
388 
389 
390 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET                                   0x0000000000000008
391 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB                                      0
392 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB                                      3
393 #define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK                                     0x000000000000000f
394 
395 
396 
397 
398 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                           0x0000000000000008
399 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB                              4
400 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB                              15
401 #define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK                             0x000000000000fff0
402 
403 
404 
405 
406 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET                             0x0000000000000008
407 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB                                16
408 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB                                16
409 #define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK                               0x0000000000010000
410 
411 
412 
413 
414 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET                                  0x0000000000000008
415 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB                                     17
416 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB                                     17
417 #define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK                                    0x0000000000020000
418 
419 
420 
421 
422 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET                                      0x0000000000000008
423 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB                                         18
424 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB                                         19
425 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK                                        0x00000000000c0000
426 
427 
428 
429 
430 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET                                    0x0000000000000008
431 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB                                       20
432 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB                                       21
433 #define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK                                      0x0000000000300000
434 
435 
436 
437 
438 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET                               0x0000000000000008
439 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB                                  22
440 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB                                  22
441 #define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK                                 0x0000000000400000
442 
443 
444 
445 
446 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET                                 0x0000000000000008
447 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB                                    23
448 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB                                    25
449 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK                                   0x0000000003800000
450 
451 
452 
453 
454 #define OFDMA_TRIGGER_DETAILS_STBC_OFFSET                                           0x0000000000000008
455 #define OFDMA_TRIGGER_DETAILS_STBC_LSB                                              26
456 #define OFDMA_TRIGGER_DETAILS_STBC_MSB                                              26
457 #define OFDMA_TRIGGER_DETAILS_STBC_MASK                                             0x0000000004000000
458 
459 
460 
461 
462 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET                              0x0000000000000008
463 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB                                 27
464 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB                                 27
465 #define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK                                0x0000000008000000
466 
467 
468 
469 
470 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET                           0x0000000000000008
471 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB                              28
472 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB                              31
473 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK                             0x00000000f0000000
474 
475 
476 
477 
478 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET                           0x0000000000000008
479 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB                              32
480 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB                              33
481 #define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK                             0x0000000300000000
482 
483 
484 
485 
486 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET                      0x0000000000000008
487 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB                         34
488 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB                         35
489 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK                        0x0000000c00000000
490 
491 
492 
493 
494 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET               0x0000000000000008
495 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                  36
496 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                  36
497 #define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                 0x0000001000000000
498 
499 
500 
501 
502 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET                                  0x0000000000000008
503 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB                                     37
504 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB                                     52
505 #define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK                                    0x001fffe000000000
506 
507 
508 
509 
510 #define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET                                        0x0000000000000008
511 #define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB                                           53
512 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB                                           53
513 #define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK                                          0x0020000000000000
514 
515 
516 
517 
518 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET                               0x0000000000000008
519 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB                                  54
520 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB                                  62
521 #define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK                                 0x7fc0000000000000
522 
523 
524 
525 
526 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET                                    0x0000000000000008
527 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB                                       63
528 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB                                       63
529 #define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK                                      0x8000000000000000
530 
531 
532 
533 
534 #define OFDMA_TRIGGER_DETAILS_AID12_OFFSET                                          0x0000000000000010
535 #define OFDMA_TRIGGER_DETAILS_AID12_LSB                                             0
536 #define OFDMA_TRIGGER_DETAILS_AID12_MSB                                             11
537 #define OFDMA_TRIGGER_DETAILS_AID12_MASK                                            0x0000000000000fff
538 
539 
540 
541 
542 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET                                  0x0000000000000010
543 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB                                     12
544 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB                                     20
545 #define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK                                    0x00000000001ff000
546 
547 
548 
549 
550 #define OFDMA_TRIGGER_DETAILS_MCS_OFFSET                                            0x0000000000000010
551 #define OFDMA_TRIGGER_DETAILS_MCS_LSB                                               21
552 #define OFDMA_TRIGGER_DETAILS_MCS_MSB                                               24
553 #define OFDMA_TRIGGER_DETAILS_MCS_MASK                                              0x0000000001e00000
554 
555 
556 
557 
558 #define OFDMA_TRIGGER_DETAILS_DCM_OFFSET                                            0x0000000000000010
559 #define OFDMA_TRIGGER_DETAILS_DCM_LSB                                               25
560 #define OFDMA_TRIGGER_DETAILS_DCM_MSB                                               25
561 #define OFDMA_TRIGGER_DETAILS_DCM_MASK                                              0x0000000002000000
562 
563 
564 
565 
566 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET                           0x0000000000000010
567 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB                              26
568 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB                              28
569 #define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK                             0x000000001c000000
570 
571 
572 
573 
574 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET                       0x0000000000000010
575 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB                          29
576 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB                          31
577 #define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK                         0x00000000e0000000
578 
579 
580 
581 
582 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET                                    0x0000000000000010
583 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB                                       32
584 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB                                       38
585 #define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK                                      0x0000007f00000000
586 
587 
588 
589 
590 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET                                    0x0000000000000010
591 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB                                       39
592 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB                                       39
593 #define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK                                      0x0000008000000000
594 
595 
596 
597 
598 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET                         0x0000000000000010
599 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB                            40
600 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB                            41
601 #define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK                           0x0000030000000000
602 
603 
604 
605 
606 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET                          0x0000000000000010
607 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB                             42
608 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB                             44
609 #define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK                            0x00001c0000000000
610 
611 
612 
613 
614 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET                                    0x0000000000000010
615 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB                                       45
616 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB                                       45
617 #define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK                                      0x0000200000000000
618 
619 
620 
621 
622 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET                                    0x0000000000000010
623 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB                                       46
624 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB                                       47
625 #define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK                                      0x0000c00000000000
626 
627 
628 
629 
630 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET                         0x0000000000000010
631 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB                            48
632 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB                            48
633 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK                           0x0001000000000000
634 
635 
636 
637 
638 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET                          0x0000000000000010
639 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB                             49
640 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB                             49
641 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK                            0x0002000000000000
642 
643 
644 
645 
646 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET                  0x0000000000000010
647 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB                     50
648 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB                     50
649 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK                    0x0004000000000000
650 
651 
652 
653 
654 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET                           0x0000000000000010
655 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB                              51
656 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB                              59
657 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK                             0x0ff8000000000000
658 
659 
660 
661 
662 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET                           0x0000000000000010
663 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB                              60
664 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB                              63
665 #define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK                             0xf000000000000000
666 
667 
668 
669 
670 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
671 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB                         0
672 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB                         11
673 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
674 
675 
676 
677 
678 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
679 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB                        12
680 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB                        15
681 #define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
682 
683 
684 
685 
686 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
687 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
688 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
689 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
690 
691 
692 
693 
694 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
695 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
696 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
697 #define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
698 
699 
700 
701 
702 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000018
703 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB                         32
704 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB                         43
705 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
706 
707 
708 
709 
710 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000018
711 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB                        44
712 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB                        47
713 #define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
714 
715 
716 
717 
718 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000018
719 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
720 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
721 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
722 
723 
724 
725 
726 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000018
727 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
728 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
729 #define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
730 
731 
732 
733 
734 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
735 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB                         0
736 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB                         11
737 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
738 
739 
740 
741 
742 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
743 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB                        12
744 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB                        15
745 #define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
746 
747 
748 
749 
750 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
751 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
752 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
753 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
754 
755 
756 
757 
758 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
759 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
760 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
761 #define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
762 
763 
764 
765 
766 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000020
767 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB                         32
768 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB                         43
769 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
770 
771 
772 
773 
774 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000020
775 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB                        44
776 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB                        47
777 #define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
778 
779 
780 
781 
782 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000020
783 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
784 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
785 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
786 
787 
788 
789 
790 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000020
791 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
792 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
793 #define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
794 
795 
796 
797 
798 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
799 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB                         0
800 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB                         11
801 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
802 
803 
804 
805 
806 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
807 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB                        12
808 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB                        15
809 #define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
810 
811 
812 
813 
814 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
815 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
816 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
817 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
818 
819 
820 
821 
822 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
823 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
824 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
825 #define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
826 
827 
828 
829 
830 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000028
831 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB                         32
832 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB                         43
833 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
834 
835 
836 
837 
838 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000028
839 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB                        44
840 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB                        47
841 #define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
842 
843 
844 
845 
846 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000028
847 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
848 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
849 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
850 
851 
852 
853 
854 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000028
855 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
856 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
857 #define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
858 
859 
860 
861 
862 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
863 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB                         0
864 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB                         11
865 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK                        0x0000000000000fff
866 
867 
868 
869 
870 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
871 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB                        12
872 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB                        15
873 #define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK                       0x000000000000f000
874 
875 
876 
877 
878 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
879 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
880 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
881 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x00000000000f0000
882 
883 
884 
885 
886 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
887 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
888 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
889 #define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0x00000000fff00000
890 
891 
892 
893 
894 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET                      0x0000000000000030
895 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB                         32
896 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB                         43
897 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK                        0x00000fff00000000
898 
899 
900 
901 
902 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000000000000030
903 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB                        44
904 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB                        47
905 #define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK                       0x0000f00000000000
906 
907 
908 
909 
910 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000000000000030
911 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB                    48
912 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB                    51
913 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f000000000000
914 
915 
916 
917 
918 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000000000000030
919 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               52
920 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               63
921 #define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff0000000000000
922 
923 
924 
925 
926 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET               0x0000000000000038
927 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB                  0
928 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB                  7
929 #define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK                 0x00000000000000ff
930 
931 
932 
933 
934 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET                                   0x0000000000000038
935 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB                                      8
936 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB                                      9
937 #define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK                                     0x0000000000000300
938 
939 
940 
941 
942 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                0x0000000000000038
943 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                   10
944 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                   15
945 #define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                  0x000000000000fc00
946 
947 
948 
949 
950 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET                        0x0000000000000038
951 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB                           16
952 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB                           31
953 #define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK                          0x00000000ffff0000
954 
955 
956 
957 
958 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET                                  0x0000000000000038
959 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB                                     32
960 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB                                     39
961 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK                                    0x000000ff00000000
962 
963 
964 
965 
966 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET                              0x0000000000000038
967 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB                                 40
968 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB                                 55
969 #define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK                                0x00ffff0000000000
970 
971 
972 
973 
974 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET                                 0x0000000000000038
975 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB                                    56
976 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB                                    62
977 #define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK                                   0x7f00000000000000
978 
979 
980 
981 
982 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET                             0x0000000000000038
983 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB                                63
984 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB                                63
985 #define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK                               0x8000000000000000
986 
987 
988 
989 
990 
991 
992 
993 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET          0x0000000000000040
994 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB             0
995 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB             9
996 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK            0x00000000000003ff
997 
998 
999 
1000 
1001 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET       0x0000000000000040
1002 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB          10
1003 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB          10
1004 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK         0x0000000000000400
1005 
1006 
1007 
1008 
1009 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET    0x0000000000000040
1010 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB       11
1011 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB       11
1012 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK      0x0000000000000800
1013 
1014 
1015 
1016 
1017 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET    0x0000000000000040
1018 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB       12
1019 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB       12
1020 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK      0x0000000000001000
1021 
1022 
1023 
1024 
1025 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET              0x0000000000000040
1026 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB                 13
1027 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB                 15
1028 #define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK                0x000000000000e000
1029 
1030 
1031 
1032 
1033 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET                       0x0000000000000040
1034 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB                          16
1035 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB                          23
1036 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK                         0x0000000000ff0000
1037 
1038 
1039 
1040 
1041 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET                           0x0000000000000040
1042 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB                              24
1043 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB                              31
1044 #define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK                             0x00000000ff000000
1045 
1046 
1047 
1048 
1049 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET                                     0x0000000000000040
1050 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB                                        32
1051 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB                                        47
1052 #define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK                                       0x0000ffff00000000
1053 
1054 
1055 
1056 
1057 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET                           0x0000000000000040
1058 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB                              48
1059 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB                              63
1060 #define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK                             0xffff000000000000
1061 
1062 
1063 
1064 
1065 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET                        0x0000000000000048
1066 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB                           0
1067 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB                           3
1068 #define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK                          0x000000000000000f
1069 
1070 
1071 
1072 
1073 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET                  0x0000000000000048
1074 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB                     4
1075 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB                     15
1076 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK                    0x000000000000fff0
1077 
1078 
1079 
1080 
1081 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET               0x0000000000000048
1082 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB                  16
1083 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB                  24
1084 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK                 0x0000000001ff0000
1085 
1086 
1087 
1088 
1089 #define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET                                        0x0000000000000048
1090 #define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB                                           25
1091 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB                                           27
1092 #define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK                                          0x000000000e000000
1093 
1094 
1095 
1096 
1097 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET               0x0000000000000048
1098 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB                  28
1099 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB                  29
1100 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK                 0x0000000030000000
1101 
1102 
1103 
1104 
1105 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET                                   0x0000000000000048
1106 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB                                      30
1107 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB                                      30
1108 #define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK                                     0x0000000040000000
1109 
1110 
1111 
1112 
1113 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET                      0x0000000000000048
1114 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB                         31
1115 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB                         31
1116 #define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK                        0x0000000080000000
1117 
1118 
1119 
1120 
1121 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET                          0x0000000000000048
1122 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB                             32
1123 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB                             47
1124 #define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK                            0x0000ffff00000000
1125 
1126 
1127 
1128 
1129 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET                                   0x0000000000000048
1130 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB                                      48
1131 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB                                      55
1132 #define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK                                     0x00ff000000000000
1133 
1134 
1135 
1136 
1137 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET                                0x0000000000000048
1138 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB                                   56
1139 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB                                   60
1140 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK                                  0x1f00000000000000
1141 
1142 
1143 
1144 
1145 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET                                   0x0000000000000048
1146 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB                                      61
1147 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB                                      63
1148 #define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK                                     0xe000000000000000
1149 
1150 
1151 
1152 
1153 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET                              0x0000000000000050
1154 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB                                 0
1155 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB                                 11
1156 #define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK                                0x0000000000000fff
1157 
1158 
1159 
1160 
1161 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET                                    0x0000000000000050
1162 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB                                       12
1163 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB                                       14
1164 #define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK                                      0x0000000000007000
1165 
1166 
1167 
1168 
1169 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET                                  0x0000000000000050
1170 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB                                     15
1171 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB                                     16
1172 #define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK                                    0x0000000000018000
1173 
1174 
1175 
1176 
1177 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET                              0x0000000000000050
1178 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB                                 17
1179 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB                                 24
1180 #define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK                                0x0000000001fe0000
1181 
1182 
1183 
1184 
1185 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET                                0x0000000000000050
1186 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB                                   25
1187 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB                                   31
1188 #define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK                                  0x00000000fe000000
1189 
1190 
1191 
1192 
1193 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET            0x0000000000000050
1194 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB               32
1195 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB               63
1196 #define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK              0xffffffff00000000
1197 
1198 
1199 
1200 #endif
1201