xref: /wlan-driver/fw-api/hw/qcn9224/v2/receive_user_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _RECEIVE_USER_INFO_H_
27 #define _RECEIVE_USER_INFO_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
32 
33 
34 struct receive_user_info {
35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
36              uint32_t phy_ppdu_id                                             : 16,
37                       user_rssi                                               :  8,
38                       pkt_type                                                :  4,
39                       stbc                                                    :  1,
40                       reception_type                                          :  3;
41              uint32_t rate_mcs                                                :  4,
42                       sgi                                                     :  2,
43                       he_ranging_ndp                                          :  1,
44                       reserved_1a                                             :  1,
45                       mimo_ss_bitmap                                          :  8,
46                       receive_bandwidth                                       :  3,
47                       reserved_1b                                             :  5,
48                       dl_ofdma_user_index                                     :  8;
49              uint32_t dl_ofdma_content_channel                                :  1,
50                       reserved_2a                                             :  7,
51                       nss                                                     :  3,
52                       stream_offset                                           :  3,
53                       sta_dcm                                                 :  1,
54                       ldpc                                                    :  1,
55                       ru_type_80_0                                            :  4,
56                       ru_type_80_1                                            :  4,
57                       ru_type_80_2                                            :  4,
58                       ru_type_80_3                                            :  4;
59              uint32_t ru_start_index_80_0                                     :  6,
60                       reserved_3a                                             :  2,
61                       ru_start_index_80_1                                     :  6,
62                       reserved_3b                                             :  2,
63                       ru_start_index_80_2                                     :  6,
64                       reserved_3c                                             :  2,
65                       ru_start_index_80_3                                     :  6,
66                       reserved_3d                                             :  2;
67              uint32_t user_fd_rssi_seg0                                       : 32;
68              uint32_t user_fd_rssi_seg1                                       : 32;
69              uint32_t user_fd_rssi_seg2                                       : 32;
70              uint32_t user_fd_rssi_seg3                                       : 32;
71 #else
72              uint32_t reception_type                                          :  3,
73                       stbc                                                    :  1,
74                       pkt_type                                                :  4,
75                       user_rssi                                               :  8,
76                       phy_ppdu_id                                             : 16;
77              uint32_t dl_ofdma_user_index                                     :  8,
78                       reserved_1b                                             :  5,
79                       receive_bandwidth                                       :  3,
80                       mimo_ss_bitmap                                          :  8,
81                       reserved_1a                                             :  1,
82                       he_ranging_ndp                                          :  1,
83                       sgi                                                     :  2,
84                       rate_mcs                                                :  4;
85              uint32_t ru_type_80_3                                            :  4,
86                       ru_type_80_2                                            :  4,
87                       ru_type_80_1                                            :  4,
88                       ru_type_80_0                                            :  4,
89                       ldpc                                                    :  1,
90                       sta_dcm                                                 :  1,
91                       stream_offset                                           :  3,
92                       nss                                                     :  3,
93                       reserved_2a                                             :  7,
94                       dl_ofdma_content_channel                                :  1;
95              uint32_t reserved_3d                                             :  2,
96                       ru_start_index_80_3                                     :  6,
97                       reserved_3c                                             :  2,
98                       ru_start_index_80_2                                     :  6,
99                       reserved_3b                                             :  2,
100                       ru_start_index_80_1                                     :  6,
101                       reserved_3a                                             :  2,
102                       ru_start_index_80_0                                     :  6;
103              uint32_t user_fd_rssi_seg0                                       : 32;
104              uint32_t user_fd_rssi_seg1                                       : 32;
105              uint32_t user_fd_rssi_seg2                                       : 32;
106              uint32_t user_fd_rssi_seg3                                       : 32;
107 #endif
108 };
109 
110 
111 
112 
113 #define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
114 #define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
115 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
116 #define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
117 
118 
119 
120 
121 #define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
122 #define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
123 #define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
124 #define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
125 
126 
127 
128 
129 #define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
130 #define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
131 #define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
132 #define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
133 
134 
135 
136 
137 #define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
138 #define RECEIVE_USER_INFO_STBC_LSB                                                  28
139 #define RECEIVE_USER_INFO_STBC_MSB                                                  28
140 #define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
141 
142 
143 
144 
145 #define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
146 #define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
147 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
148 #define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
149 
150 
151 
152 
153 #define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
154 #define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
155 #define RECEIVE_USER_INFO_RATE_MCS_MSB                                              3
156 #define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000000f
157 
158 
159 
160 
161 #define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
162 #define RECEIVE_USER_INFO_SGI_LSB                                                   4
163 #define RECEIVE_USER_INFO_SGI_MSB                                                   5
164 #define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000030
165 
166 
167 
168 
169 #define RECEIVE_USER_INFO_HE_RANGING_NDP_OFFSET                                     0x00000004
170 #define RECEIVE_USER_INFO_HE_RANGING_NDP_LSB                                        6
171 #define RECEIVE_USER_INFO_HE_RANGING_NDP_MSB                                        6
172 #define RECEIVE_USER_INFO_HE_RANGING_NDP_MASK                                       0x00000040
173 
174 
175 
176 
177 #define RECEIVE_USER_INFO_RESERVED_1A_OFFSET                                        0x00000004
178 #define RECEIVE_USER_INFO_RESERVED_1A_LSB                                           7
179 #define RECEIVE_USER_INFO_RESERVED_1A_MSB                                           7
180 #define RECEIVE_USER_INFO_RESERVED_1A_MASK                                          0x00000080
181 
182 
183 
184 
185 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
186 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
187 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
188 #define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
189 
190 
191 
192 
193 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
194 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
195 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
196 #define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
197 
198 
199 
200 
201 #define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
202 #define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
203 #define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
204 #define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
205 
206 
207 
208 
209 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
210 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
211 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
212 #define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
213 
214 
215 
216 
217 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
218 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
219 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
220 #define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
221 
222 
223 
224 
225 #define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
226 #define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
227 #define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           7
228 #define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x000000fe
229 
230 
231 
232 
233 #define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
234 #define RECEIVE_USER_INFO_NSS_LSB                                                   8
235 #define RECEIVE_USER_INFO_NSS_MSB                                                   10
236 #define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
237 
238 
239 
240 
241 #define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
242 #define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
243 #define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
244 #define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
245 
246 
247 
248 
249 #define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
250 #define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
251 #define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
252 #define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
253 
254 
255 
256 
257 #define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
258 #define RECEIVE_USER_INFO_LDPC_LSB                                                  15
259 #define RECEIVE_USER_INFO_LDPC_MSB                                                  15
260 #define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
261 
262 
263 
264 
265 #define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
266 #define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
267 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
268 #define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
269 
270 
271 
272 
273 #define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
274 #define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
275 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
276 #define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
277 
278 
279 
280 
281 #define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
282 #define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
283 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
284 #define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
285 
286 
287 
288 
289 #define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
290 #define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
291 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
292 #define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
293 
294 
295 
296 
297 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
298 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
299 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
300 #define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
301 
302 
303 
304 
305 #define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
306 #define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
307 #define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
308 #define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
309 
310 
311 
312 
313 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
314 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
315 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
316 #define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
317 
318 
319 
320 
321 #define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
322 #define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
323 #define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
324 #define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
325 
326 
327 
328 
329 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
330 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
331 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
332 #define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
333 
334 
335 
336 
337 #define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
338 #define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
339 #define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
340 #define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
341 
342 
343 
344 
345 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
346 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
347 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
348 #define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
349 
350 
351 
352 
353 #define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
354 #define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           30
355 #define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
356 #define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0xc0000000
357 
358 
359 
360 
361 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
362 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
363 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
364 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
365 
366 
367 
368 
369 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
370 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
371 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
372 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
373 
374 
375 
376 
377 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
378 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
379 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
380 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
381 
382 
383 
384 
385 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
386 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
387 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
388 #define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
389 
390 
391 
392 #endif
393