1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _REO_FLUSH_QUEUE_H_ 27 #define _REO_FLUSH_QUEUE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_reo_cmd_header.h" 32 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 33 34 #define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 35 36 37 struct reo_flush_queue { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct uniform_reo_cmd_header cmd_header; 40 uint32_t flush_desc_addr_31_0 : 32; 41 uint32_t flush_desc_addr_39_32 : 8, 42 block_desc_addr_usage_after_flush : 1, 43 block_resource_index : 2, 44 reserved_2a : 21; 45 uint32_t reserved_3a : 32; 46 uint32_t reserved_4a : 32; 47 uint32_t reserved_5a : 32; 48 uint32_t reserved_6a : 32; 49 uint32_t reserved_7a : 32; 50 uint32_t reserved_8a : 32; 51 uint32_t tlv64_padding : 32; 52 #else 53 struct uniform_reo_cmd_header cmd_header; 54 uint32_t flush_desc_addr_31_0 : 32; 55 uint32_t reserved_2a : 21, 56 block_resource_index : 2, 57 block_desc_addr_usage_after_flush : 1, 58 flush_desc_addr_39_32 : 8; 59 uint32_t reserved_3a : 32; 60 uint32_t reserved_4a : 32; 61 uint32_t reserved_5a : 32; 62 uint32_t reserved_6a : 32; 63 uint32_t reserved_7a : 32; 64 uint32_t reserved_8a : 32; 65 uint32_t tlv64_padding : 32; 66 #endif 67 }; 68 69 70 71 72 73 74 75 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 76 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 77 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 78 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff 79 80 81 82 83 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 84 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 85 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 86 #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 87 88 89 90 91 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 92 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 93 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 94 #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 95 96 97 98 99 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 100 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 101 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 102 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 103 104 105 106 107 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 108 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 109 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 110 #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff 111 112 113 114 115 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 116 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 117 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 118 #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 119 120 121 122 123 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 124 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 125 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 126 #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 127 128 129 130 131 #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 132 #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 133 #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 134 #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 135 136 137 138 139 #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 140 #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 141 #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 142 #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 143 144 145 146 147 #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 148 #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 149 #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 150 #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff 151 152 153 154 155 #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 156 #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 157 #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 158 #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 159 160 161 162 163 #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 164 #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 165 #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 166 #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff 167 168 169 170 171 #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 172 #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 173 #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 174 #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 175 176 177 178 179 #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 180 #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 181 #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 182 #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff 183 184 185 186 187 #define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 188 #define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 189 #define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 190 #define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 191 192 193 194 #endif 195