1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_FRAME_1K_BITMAP_ACK_H_ 27 #define _RX_FRAME_1K_BITMAP_ACK_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 32 33 #define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 34 35 36 struct rx_frame_1k_bitmap_ack { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t reserved_0a : 5, 39 ba_bitmap_size : 2, 40 reserved_0b : 3, 41 ba_tid : 4, 42 sta_full_aid : 13, 43 reserved_0c : 5; 44 uint32_t addr1_31_0 : 32; 45 uint32_t addr1_47_32 : 16, 46 addr2_15_0 : 16; 47 uint32_t addr2_47_16 : 32; 48 uint32_t ba_ts_ctrl : 16, 49 ba_ts_seq : 16; 50 uint32_t ba_ts_bitmap_31_0 : 32; 51 uint32_t ba_ts_bitmap_63_32 : 32; 52 uint32_t ba_ts_bitmap_95_64 : 32; 53 uint32_t ba_ts_bitmap_127_96 : 32; 54 uint32_t ba_ts_bitmap_159_128 : 32; 55 uint32_t ba_ts_bitmap_191_160 : 32; 56 uint32_t ba_ts_bitmap_223_192 : 32; 57 uint32_t ba_ts_bitmap_255_224 : 32; 58 uint32_t ba_ts_bitmap_287_256 : 32; 59 uint32_t ba_ts_bitmap_319_288 : 32; 60 uint32_t ba_ts_bitmap_351_320 : 32; 61 uint32_t ba_ts_bitmap_383_352 : 32; 62 uint32_t ba_ts_bitmap_415_384 : 32; 63 uint32_t ba_ts_bitmap_447_416 : 32; 64 uint32_t ba_ts_bitmap_479_448 : 32; 65 uint32_t ba_ts_bitmap_511_480 : 32; 66 uint32_t ba_ts_bitmap_543_512 : 32; 67 uint32_t ba_ts_bitmap_575_544 : 32; 68 uint32_t ba_ts_bitmap_607_576 : 32; 69 uint32_t ba_ts_bitmap_639_608 : 32; 70 uint32_t ba_ts_bitmap_671_640 : 32; 71 uint32_t ba_ts_bitmap_703_672 : 32; 72 uint32_t ba_ts_bitmap_735_704 : 32; 73 uint32_t ba_ts_bitmap_767_736 : 32; 74 uint32_t ba_ts_bitmap_799_768 : 32; 75 uint32_t ba_ts_bitmap_831_800 : 32; 76 uint32_t ba_ts_bitmap_863_832 : 32; 77 uint32_t ba_ts_bitmap_895_864 : 32; 78 uint32_t ba_ts_bitmap_927_896 : 32; 79 uint32_t ba_ts_bitmap_959_928 : 32; 80 uint32_t ba_ts_bitmap_991_960 : 32; 81 uint32_t ba_ts_bitmap_1023_992 : 32; 82 uint32_t tlv64_padding : 32; 83 #else 84 uint32_t reserved_0c : 5, 85 sta_full_aid : 13, 86 ba_tid : 4, 87 reserved_0b : 3, 88 ba_bitmap_size : 2, 89 reserved_0a : 5; 90 uint32_t addr1_31_0 : 32; 91 uint32_t addr2_15_0 : 16, 92 addr1_47_32 : 16; 93 uint32_t addr2_47_16 : 32; 94 uint32_t ba_ts_seq : 16, 95 ba_ts_ctrl : 16; 96 uint32_t ba_ts_bitmap_31_0 : 32; 97 uint32_t ba_ts_bitmap_63_32 : 32; 98 uint32_t ba_ts_bitmap_95_64 : 32; 99 uint32_t ba_ts_bitmap_127_96 : 32; 100 uint32_t ba_ts_bitmap_159_128 : 32; 101 uint32_t ba_ts_bitmap_191_160 : 32; 102 uint32_t ba_ts_bitmap_223_192 : 32; 103 uint32_t ba_ts_bitmap_255_224 : 32; 104 uint32_t ba_ts_bitmap_287_256 : 32; 105 uint32_t ba_ts_bitmap_319_288 : 32; 106 uint32_t ba_ts_bitmap_351_320 : 32; 107 uint32_t ba_ts_bitmap_383_352 : 32; 108 uint32_t ba_ts_bitmap_415_384 : 32; 109 uint32_t ba_ts_bitmap_447_416 : 32; 110 uint32_t ba_ts_bitmap_479_448 : 32; 111 uint32_t ba_ts_bitmap_511_480 : 32; 112 uint32_t ba_ts_bitmap_543_512 : 32; 113 uint32_t ba_ts_bitmap_575_544 : 32; 114 uint32_t ba_ts_bitmap_607_576 : 32; 115 uint32_t ba_ts_bitmap_639_608 : 32; 116 uint32_t ba_ts_bitmap_671_640 : 32; 117 uint32_t ba_ts_bitmap_703_672 : 32; 118 uint32_t ba_ts_bitmap_735_704 : 32; 119 uint32_t ba_ts_bitmap_767_736 : 32; 120 uint32_t ba_ts_bitmap_799_768 : 32; 121 uint32_t ba_ts_bitmap_831_800 : 32; 122 uint32_t ba_ts_bitmap_863_832 : 32; 123 uint32_t ba_ts_bitmap_895_864 : 32; 124 uint32_t ba_ts_bitmap_927_896 : 32; 125 uint32_t ba_ts_bitmap_959_928 : 32; 126 uint32_t ba_ts_bitmap_991_960 : 32; 127 uint32_t ba_ts_bitmap_1023_992 : 32; 128 uint32_t tlv64_padding : 32; 129 #endif 130 }; 131 132 133 134 135 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 136 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 137 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 138 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f 139 140 141 142 143 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 144 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 145 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 146 #define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 147 148 149 150 151 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 152 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 153 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 154 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 155 156 157 158 159 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 160 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 161 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 162 #define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 163 164 165 166 167 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 168 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 169 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 170 #define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 171 172 173 174 175 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 176 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 177 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 178 #define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 179 180 181 182 183 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 184 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 185 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 186 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 187 188 189 190 191 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 192 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 193 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 194 #define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff 195 196 197 198 199 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 200 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 201 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 202 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 203 204 205 206 207 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 208 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 209 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 210 #define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 211 212 213 214 215 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 216 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 217 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 218 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff 219 220 221 222 223 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 224 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 225 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 226 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 227 228 229 230 231 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 232 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 233 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 234 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 235 236 237 238 239 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 240 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 241 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 242 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff 243 244 245 246 247 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 248 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 249 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 250 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 251 252 253 254 255 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 256 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 257 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 258 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff 259 260 261 262 263 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 264 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 265 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 266 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 267 268 269 270 271 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 272 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 273 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 274 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff 275 276 277 278 279 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 280 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 281 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 282 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 283 284 285 286 287 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 288 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 289 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 290 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff 291 292 293 294 295 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 296 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 297 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 298 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 299 300 301 302 303 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 304 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 305 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 306 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff 307 308 309 310 311 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 312 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 313 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 314 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 315 316 317 318 319 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 320 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 321 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 322 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff 323 324 325 326 327 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 328 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 329 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 330 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 331 332 333 334 335 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 336 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 337 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 338 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff 339 340 341 342 343 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 344 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 345 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 346 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 347 348 349 350 351 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 352 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 353 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 354 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff 355 356 357 358 359 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 360 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 361 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 362 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 363 364 365 366 367 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 368 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 369 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 370 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff 371 372 373 374 375 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 376 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 377 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 378 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 379 380 381 382 383 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 384 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 385 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 386 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff 387 388 389 390 391 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 392 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 393 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 394 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 395 396 397 398 399 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 400 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 401 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 402 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff 403 404 405 406 407 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 408 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 409 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 410 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 411 412 413 414 415 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 416 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 417 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 418 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff 419 420 421 422 423 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 424 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 425 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 426 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 427 428 429 430 431 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 432 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 433 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 434 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff 435 436 437 438 439 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 440 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 441 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 442 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 443 444 445 446 447 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 448 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 449 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 450 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff 451 452 453 454 455 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 456 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 457 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 458 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 459 460 461 462 463 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 464 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 465 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 466 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff 467 468 469 470 471 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 472 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 473 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 474 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 475 476 477 478 479 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 480 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 481 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 482 #define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff 483 484 485 486 487 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 488 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 489 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 490 #define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 491 492 493 494 #endif 495