1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MPDU_INFO_H_ 27 #define _RX_MPDU_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rxpt_classify_info.h" 32 #define NUM_OF_DWORDS_RX_MPDU_INFO 30 33 34 35 struct rx_mpdu_info { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct rxpt_classify_info rxpt_classify_info_details; 38 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 39 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 40 receive_queue_number : 16, 41 pre_delim_err_warning : 1, 42 first_delim_err : 1, 43 reserved_2a : 6; 44 uint32_t pn_31_0 : 32; 45 uint32_t pn_63_32 : 32; 46 uint32_t pn_95_64 : 32; 47 uint32_t pn_127_96 : 32; 48 uint32_t epd_en : 1, 49 all_frames_shall_be_encrypted : 1, 50 encrypt_type : 4, 51 wep_key_width_for_variable_key : 2, 52 mesh_sta : 2, 53 bssid_hit : 1, 54 bssid_number : 4, 55 tid : 4, 56 reserved_7a : 13; 57 uint32_t peer_meta_data : 32; 58 uint32_t rxpcu_mpdu_filter_in_category : 2, 59 sw_frame_group_id : 7, 60 ndp_frame : 1, 61 phy_err : 1, 62 phy_err_during_mpdu_header : 1, 63 protocol_version_err : 1, 64 ast_based_lookup_valid : 1, 65 ranging : 1, 66 reserved_9a : 1, 67 phy_ppdu_id : 16; 68 uint32_t ast_index : 16, 69 sw_peer_id : 16; 70 uint32_t mpdu_frame_control_valid : 1, 71 mpdu_duration_valid : 1, 72 mac_addr_ad1_valid : 1, 73 mac_addr_ad2_valid : 1, 74 mac_addr_ad3_valid : 1, 75 mac_addr_ad4_valid : 1, 76 mpdu_sequence_control_valid : 1, 77 mpdu_qos_control_valid : 1, 78 mpdu_ht_control_valid : 1, 79 frame_encryption_info_valid : 1, 80 mpdu_fragment_number : 4, 81 more_fragment_flag : 1, 82 reserved_11a : 1, 83 fr_ds : 1, 84 to_ds : 1, 85 encrypted : 1, 86 mpdu_retry : 1, 87 mpdu_sequence_number : 12; 88 uint32_t key_id_octet : 8, 89 new_peer_entry : 1, 90 decrypt_needed : 1, 91 decap_type : 2, 92 rx_insert_vlan_c_tag_padding : 1, 93 rx_insert_vlan_s_tag_padding : 1, 94 strip_vlan_c_tag_decap : 1, 95 strip_vlan_s_tag_decap : 1, 96 pre_delim_count : 12, 97 ampdu_flag : 1, 98 bar_frame : 1, 99 raw_mpdu : 1, 100 reserved_12 : 1; 101 uint32_t mpdu_length : 14, 102 first_mpdu : 1, 103 mcast_bcast : 1, 104 ast_index_not_found : 1, 105 ast_index_timeout : 1, 106 power_mgmt : 1, 107 non_qos : 1, 108 null_data : 1, 109 mgmt_type : 1, 110 ctrl_type : 1, 111 more_data : 1, 112 eosp : 1, 113 fragment_flag : 1, 114 order : 1, 115 u_apsd_trigger : 1, 116 encrypt_required : 1, 117 directed : 1, 118 amsdu_present : 1, 119 reserved_13 : 1; 120 uint32_t mpdu_frame_control_field : 16, 121 mpdu_duration_field : 16; 122 uint32_t mac_addr_ad1_31_0 : 32; 123 uint32_t mac_addr_ad1_47_32 : 16, 124 mac_addr_ad2_15_0 : 16; 125 uint32_t mac_addr_ad2_47_16 : 32; 126 uint32_t mac_addr_ad3_31_0 : 32; 127 uint32_t mac_addr_ad3_47_32 : 16, 128 mpdu_sequence_control_field : 16; 129 uint32_t mac_addr_ad4_31_0 : 32; 130 uint32_t mac_addr_ad4_47_32 : 16, 131 mpdu_qos_control_field : 16; 132 uint32_t mpdu_ht_control_field : 32; 133 uint32_t vdev_id : 8, 134 service_code : 9, 135 priority_valid : 1, 136 src_info : 12, 137 reserved_23a : 1, 138 multi_link_addr_ad1_ad2_valid : 1; 139 uint32_t multi_link_addr_ad1_31_0 : 32; 140 uint32_t multi_link_addr_ad1_47_32 : 16, 141 multi_link_addr_ad2_15_0 : 16; 142 uint32_t multi_link_addr_ad2_47_16 : 32; 143 uint32_t authorized_to_send_wds : 1, 144 reserved_27a : 31; 145 uint32_t reserved_28a : 32; 146 uint32_t reserved_29a : 32; 147 #else 148 struct rxpt_classify_info rxpt_classify_info_details; 149 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 150 uint32_t reserved_2a : 6, 151 first_delim_err : 1, 152 pre_delim_err_warning : 1, 153 receive_queue_number : 16, 154 rx_reo_queue_desc_addr_39_32 : 8; 155 uint32_t pn_31_0 : 32; 156 uint32_t pn_63_32 : 32; 157 uint32_t pn_95_64 : 32; 158 uint32_t pn_127_96 : 32; 159 uint32_t reserved_7a : 13, 160 tid : 4, 161 bssid_number : 4, 162 bssid_hit : 1, 163 mesh_sta : 2, 164 wep_key_width_for_variable_key : 2, 165 encrypt_type : 4, 166 all_frames_shall_be_encrypted : 1, 167 epd_en : 1; 168 uint32_t peer_meta_data : 32; 169 uint32_t phy_ppdu_id : 16, 170 reserved_9a : 1, 171 ranging : 1, 172 ast_based_lookup_valid : 1, 173 protocol_version_err : 1, 174 phy_err_during_mpdu_header : 1, 175 phy_err : 1, 176 ndp_frame : 1, 177 sw_frame_group_id : 7, 178 rxpcu_mpdu_filter_in_category : 2; 179 uint32_t sw_peer_id : 16, 180 ast_index : 16; 181 uint32_t mpdu_sequence_number : 12, 182 mpdu_retry : 1, 183 encrypted : 1, 184 to_ds : 1, 185 fr_ds : 1, 186 reserved_11a : 1, 187 more_fragment_flag : 1, 188 mpdu_fragment_number : 4, 189 frame_encryption_info_valid : 1, 190 mpdu_ht_control_valid : 1, 191 mpdu_qos_control_valid : 1, 192 mpdu_sequence_control_valid : 1, 193 mac_addr_ad4_valid : 1, 194 mac_addr_ad3_valid : 1, 195 mac_addr_ad2_valid : 1, 196 mac_addr_ad1_valid : 1, 197 mpdu_duration_valid : 1, 198 mpdu_frame_control_valid : 1; 199 uint32_t reserved_12 : 1, 200 raw_mpdu : 1, 201 bar_frame : 1, 202 ampdu_flag : 1, 203 pre_delim_count : 12, 204 strip_vlan_s_tag_decap : 1, 205 strip_vlan_c_tag_decap : 1, 206 rx_insert_vlan_s_tag_padding : 1, 207 rx_insert_vlan_c_tag_padding : 1, 208 decap_type : 2, 209 decrypt_needed : 1, 210 new_peer_entry : 1, 211 key_id_octet : 8; 212 uint32_t reserved_13 : 1, 213 amsdu_present : 1, 214 directed : 1, 215 encrypt_required : 1, 216 u_apsd_trigger : 1, 217 order : 1, 218 fragment_flag : 1, 219 eosp : 1, 220 more_data : 1, 221 ctrl_type : 1, 222 mgmt_type : 1, 223 null_data : 1, 224 non_qos : 1, 225 power_mgmt : 1, 226 ast_index_timeout : 1, 227 ast_index_not_found : 1, 228 mcast_bcast : 1, 229 first_mpdu : 1, 230 mpdu_length : 14; 231 uint32_t mpdu_duration_field : 16, 232 mpdu_frame_control_field : 16; 233 uint32_t mac_addr_ad1_31_0 : 32; 234 uint32_t mac_addr_ad2_15_0 : 16, 235 mac_addr_ad1_47_32 : 16; 236 uint32_t mac_addr_ad2_47_16 : 32; 237 uint32_t mac_addr_ad3_31_0 : 32; 238 uint32_t mpdu_sequence_control_field : 16, 239 mac_addr_ad3_47_32 : 16; 240 uint32_t mac_addr_ad4_31_0 : 32; 241 uint32_t mpdu_qos_control_field : 16, 242 mac_addr_ad4_47_32 : 16; 243 uint32_t mpdu_ht_control_field : 32; 244 uint32_t multi_link_addr_ad1_ad2_valid : 1, 245 reserved_23a : 1, 246 src_info : 12, 247 priority_valid : 1, 248 service_code : 9, 249 vdev_id : 8; 250 uint32_t multi_link_addr_ad1_31_0 : 32; 251 uint32_t multi_link_addr_ad2_15_0 : 16, 252 multi_link_addr_ad1_47_32 : 16; 253 uint32_t multi_link_addr_ad2_47_16 : 32; 254 uint32_t reserved_27a : 31, 255 authorized_to_send_wds : 1; 256 uint32_t reserved_28a : 32; 257 uint32_t reserved_29a : 32; 258 #endif 259 }; 260 261 262 263 264 265 266 267 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 268 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 269 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 270 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f 271 272 273 274 275 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 276 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 277 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 278 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 279 280 281 282 283 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 284 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 285 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 286 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 287 288 289 290 291 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 292 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 293 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 294 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 295 296 297 298 299 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 300 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 301 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 302 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 303 304 305 306 307 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 308 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 309 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 310 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 311 312 313 314 315 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 316 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 317 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 318 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 319 320 321 322 323 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 324 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 325 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 326 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 327 328 329 330 331 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 332 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 333 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 334 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 335 336 337 338 339 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 340 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 341 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 342 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 343 344 345 346 347 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 348 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 349 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 350 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 351 352 353 354 355 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 356 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 357 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 358 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 359 360 361 362 363 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 364 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 365 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 366 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 367 368 369 370 371 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 372 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 373 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 374 #define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 375 376 377 378 379 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 380 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 381 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 382 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 383 384 385 386 387 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 388 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 389 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 390 #define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 391 392 393 394 395 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 396 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 397 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 398 #define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 399 400 401 402 403 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 404 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 405 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 406 #define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 407 408 409 410 411 #define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 412 #define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 413 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 414 #define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 415 416 417 418 419 #define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 420 #define RX_MPDU_INFO_RESERVED_2A_LSB 26 421 #define RX_MPDU_INFO_RESERVED_2A_MSB 31 422 #define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 423 424 425 426 427 #define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c 428 #define RX_MPDU_INFO_PN_31_0_LSB 0 429 #define RX_MPDU_INFO_PN_31_0_MSB 31 430 #define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff 431 432 433 434 435 #define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 436 #define RX_MPDU_INFO_PN_63_32_LSB 0 437 #define RX_MPDU_INFO_PN_63_32_MSB 31 438 #define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff 439 440 441 442 443 #define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 444 #define RX_MPDU_INFO_PN_95_64_LSB 0 445 #define RX_MPDU_INFO_PN_95_64_MSB 31 446 #define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff 447 448 449 450 451 #define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 452 #define RX_MPDU_INFO_PN_127_96_LSB 0 453 #define RX_MPDU_INFO_PN_127_96_MSB 31 454 #define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff 455 456 457 458 459 #define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c 460 #define RX_MPDU_INFO_EPD_EN_LSB 0 461 #define RX_MPDU_INFO_EPD_EN_MSB 0 462 #define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 463 464 465 466 467 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c 468 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 469 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 470 #define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 471 472 473 474 475 #define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c 476 #define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 477 #define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 478 #define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c 479 480 481 482 483 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c 484 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 485 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 486 #define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 487 488 489 490 491 #define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c 492 #define RX_MPDU_INFO_MESH_STA_LSB 8 493 #define RX_MPDU_INFO_MESH_STA_MSB 9 494 #define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 495 496 497 498 499 #define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c 500 #define RX_MPDU_INFO_BSSID_HIT_LSB 10 501 #define RX_MPDU_INFO_BSSID_HIT_MSB 10 502 #define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 503 504 505 506 507 #define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c 508 #define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 509 #define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 510 #define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 511 512 513 514 515 #define RX_MPDU_INFO_TID_OFFSET 0x0000001c 516 #define RX_MPDU_INFO_TID_LSB 15 517 #define RX_MPDU_INFO_TID_MSB 18 518 #define RX_MPDU_INFO_TID_MASK 0x00078000 519 520 521 522 523 #define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c 524 #define RX_MPDU_INFO_RESERVED_7A_LSB 19 525 #define RX_MPDU_INFO_RESERVED_7A_MSB 31 526 #define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 527 528 529 530 531 #define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 532 #define RX_MPDU_INFO_PEER_META_DATA_LSB 0 533 #define RX_MPDU_INFO_PEER_META_DATA_MSB 31 534 #define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff 535 536 537 538 539 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 540 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 541 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 542 #define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 543 544 545 546 547 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 548 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 549 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 550 #define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc 551 552 553 554 555 #define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 556 #define RX_MPDU_INFO_NDP_FRAME_LSB 9 557 #define RX_MPDU_INFO_NDP_FRAME_MSB 9 558 #define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 559 560 561 562 563 #define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 564 #define RX_MPDU_INFO_PHY_ERR_LSB 10 565 #define RX_MPDU_INFO_PHY_ERR_MSB 10 566 #define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 567 568 569 570 571 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 572 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 573 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 574 #define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 575 576 577 578 579 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 580 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 581 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 582 #define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 583 584 585 586 587 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 588 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 589 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 590 #define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 591 592 593 594 595 #define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 596 #define RX_MPDU_INFO_RANGING_LSB 14 597 #define RX_MPDU_INFO_RANGING_MSB 14 598 #define RX_MPDU_INFO_RANGING_MASK 0x00004000 599 600 601 602 603 #define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 604 #define RX_MPDU_INFO_RESERVED_9A_LSB 15 605 #define RX_MPDU_INFO_RESERVED_9A_MSB 15 606 #define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 607 608 609 610 611 #define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 612 #define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 613 #define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 614 #define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 615 616 617 618 619 #define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 620 #define RX_MPDU_INFO_AST_INDEX_LSB 0 621 #define RX_MPDU_INFO_AST_INDEX_MSB 15 622 #define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff 623 624 625 626 627 #define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 628 #define RX_MPDU_INFO_SW_PEER_ID_LSB 16 629 #define RX_MPDU_INFO_SW_PEER_ID_MSB 31 630 #define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 631 632 633 634 635 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c 636 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 637 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 638 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 639 640 641 642 643 #define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c 644 #define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 645 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 646 #define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 647 648 649 650 651 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c 652 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 653 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 654 #define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 655 656 657 658 659 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c 660 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 661 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 662 #define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 663 664 665 666 667 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c 668 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 669 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 670 #define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 671 672 673 674 675 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c 676 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 677 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 678 #define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 679 680 681 682 683 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c 684 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 685 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 686 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 687 688 689 690 691 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c 692 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 693 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 694 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 695 696 697 698 699 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c 700 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 701 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 702 #define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 703 704 705 706 707 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c 708 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 709 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 710 #define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 711 712 713 714 715 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c 716 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 717 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 718 #define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 719 720 721 722 723 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c 724 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 725 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 726 #define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 727 728 729 730 731 #define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c 732 #define RX_MPDU_INFO_RESERVED_11A_LSB 15 733 #define RX_MPDU_INFO_RESERVED_11A_MSB 15 734 #define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 735 736 737 738 739 #define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c 740 #define RX_MPDU_INFO_FR_DS_LSB 16 741 #define RX_MPDU_INFO_FR_DS_MSB 16 742 #define RX_MPDU_INFO_FR_DS_MASK 0x00010000 743 744 745 746 747 #define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c 748 #define RX_MPDU_INFO_TO_DS_LSB 17 749 #define RX_MPDU_INFO_TO_DS_MSB 17 750 #define RX_MPDU_INFO_TO_DS_MASK 0x00020000 751 752 753 754 755 #define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c 756 #define RX_MPDU_INFO_ENCRYPTED_LSB 18 757 #define RX_MPDU_INFO_ENCRYPTED_MSB 18 758 #define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 759 760 761 762 763 #define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c 764 #define RX_MPDU_INFO_MPDU_RETRY_LSB 19 765 #define RX_MPDU_INFO_MPDU_RETRY_MSB 19 766 #define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 767 768 769 770 771 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c 772 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 773 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 774 #define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 775 776 777 778 779 #define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 780 #define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 781 #define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 782 #define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff 783 784 785 786 787 #define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 788 #define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 789 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 790 #define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 791 792 793 794 795 #define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 796 #define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 797 #define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 798 #define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 799 800 801 802 803 #define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 804 #define RX_MPDU_INFO_DECAP_TYPE_LSB 10 805 #define RX_MPDU_INFO_DECAP_TYPE_MSB 11 806 #define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 807 808 809 810 811 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 812 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 813 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 814 #define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 815 816 817 818 819 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 820 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 821 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 822 #define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 823 824 825 826 827 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 828 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 829 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 830 #define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 831 832 833 834 835 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 836 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 837 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 838 #define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 839 840 841 842 843 #define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 844 #define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 845 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 846 #define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 847 848 849 850 851 #define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 852 #define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 853 #define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 854 #define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 855 856 857 858 859 #define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 860 #define RX_MPDU_INFO_BAR_FRAME_LSB 29 861 #define RX_MPDU_INFO_BAR_FRAME_MSB 29 862 #define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 863 864 865 866 867 #define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 868 #define RX_MPDU_INFO_RAW_MPDU_LSB 30 869 #define RX_MPDU_INFO_RAW_MPDU_MSB 30 870 #define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 871 872 873 874 875 #define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 876 #define RX_MPDU_INFO_RESERVED_12_LSB 31 877 #define RX_MPDU_INFO_RESERVED_12_MSB 31 878 #define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 879 880 881 882 883 #define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 884 #define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 885 #define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 886 #define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff 887 888 889 890 891 #define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 892 #define RX_MPDU_INFO_FIRST_MPDU_LSB 14 893 #define RX_MPDU_INFO_FIRST_MPDU_MSB 14 894 #define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 895 896 897 898 899 #define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 900 #define RX_MPDU_INFO_MCAST_BCAST_LSB 15 901 #define RX_MPDU_INFO_MCAST_BCAST_MSB 15 902 #define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 903 904 905 906 907 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 908 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 909 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 910 #define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 911 912 913 914 915 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 916 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 917 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 918 #define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 919 920 921 922 923 #define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 924 #define RX_MPDU_INFO_POWER_MGMT_LSB 18 925 #define RX_MPDU_INFO_POWER_MGMT_MSB 18 926 #define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 927 928 929 930 931 #define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 932 #define RX_MPDU_INFO_NON_QOS_LSB 19 933 #define RX_MPDU_INFO_NON_QOS_MSB 19 934 #define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 935 936 937 938 939 #define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 940 #define RX_MPDU_INFO_NULL_DATA_LSB 20 941 #define RX_MPDU_INFO_NULL_DATA_MSB 20 942 #define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 943 944 945 946 947 #define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 948 #define RX_MPDU_INFO_MGMT_TYPE_LSB 21 949 #define RX_MPDU_INFO_MGMT_TYPE_MSB 21 950 #define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 951 952 953 954 955 #define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 956 #define RX_MPDU_INFO_CTRL_TYPE_LSB 22 957 #define RX_MPDU_INFO_CTRL_TYPE_MSB 22 958 #define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 959 960 961 962 963 #define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 964 #define RX_MPDU_INFO_MORE_DATA_LSB 23 965 #define RX_MPDU_INFO_MORE_DATA_MSB 23 966 #define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 967 968 969 970 971 #define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 972 #define RX_MPDU_INFO_EOSP_LSB 24 973 #define RX_MPDU_INFO_EOSP_MSB 24 974 #define RX_MPDU_INFO_EOSP_MASK 0x01000000 975 976 977 978 979 #define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 980 #define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 981 #define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 982 #define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 983 984 985 986 987 #define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 988 #define RX_MPDU_INFO_ORDER_LSB 26 989 #define RX_MPDU_INFO_ORDER_MSB 26 990 #define RX_MPDU_INFO_ORDER_MASK 0x04000000 991 992 993 994 995 #define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 996 #define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 997 #define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 998 #define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 999 1000 1001 1002 1003 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 1004 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 1005 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 1006 #define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 1007 1008 1009 1010 1011 #define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 1012 #define RX_MPDU_INFO_DIRECTED_LSB 29 1013 #define RX_MPDU_INFO_DIRECTED_MSB 29 1014 #define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 1015 1016 1017 1018 1019 #define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 1020 #define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 1021 #define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 1022 #define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 1023 1024 1025 1026 1027 #define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 1028 #define RX_MPDU_INFO_RESERVED_13_LSB 31 1029 #define RX_MPDU_INFO_RESERVED_13_MSB 31 1030 #define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 1031 1032 1033 1034 1035 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 1036 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 1037 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 1038 #define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff 1039 1040 1041 1042 1043 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 1044 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 1045 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 1046 #define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 1047 1048 1049 1050 1051 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c 1052 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 1053 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 1054 #define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff 1055 1056 1057 1058 1059 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 1060 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 1061 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 1062 #define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff 1063 1064 1065 1066 1067 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 1068 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 1069 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 1070 #define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 1071 1072 1073 1074 1075 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 1076 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 1077 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 1078 #define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff 1079 1080 1081 1082 1083 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 1084 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 1085 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 1086 #define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff 1087 1088 1089 1090 1091 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c 1092 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 1093 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 1094 #define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff 1095 1096 1097 1098 1099 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c 1100 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 1101 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 1102 #define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 1103 1104 1105 1106 1107 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 1108 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 1109 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 1110 #define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff 1111 1112 1113 1114 1115 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 1116 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 1117 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 1118 #define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff 1119 1120 1121 1122 1123 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 1124 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 1125 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 1126 #define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 1127 1128 1129 1130 1131 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 1132 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 1133 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 1134 #define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff 1135 1136 1137 1138 1139 #define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c 1140 #define RX_MPDU_INFO_VDEV_ID_LSB 0 1141 #define RX_MPDU_INFO_VDEV_ID_MSB 7 1142 #define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff 1143 1144 1145 1146 1147 #define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c 1148 #define RX_MPDU_INFO_SERVICE_CODE_LSB 8 1149 #define RX_MPDU_INFO_SERVICE_CODE_MSB 16 1150 #define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 1151 1152 1153 1154 1155 #define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c 1156 #define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 1157 #define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 1158 #define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 1159 1160 1161 1162 1163 #define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c 1164 #define RX_MPDU_INFO_SRC_INFO_LSB 18 1165 #define RX_MPDU_INFO_SRC_INFO_MSB 29 1166 #define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 1167 1168 1169 1170 1171 #define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c 1172 #define RX_MPDU_INFO_RESERVED_23A_LSB 30 1173 #define RX_MPDU_INFO_RESERVED_23A_MSB 30 1174 #define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 1175 1176 1177 1178 1179 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c 1180 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 1181 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 1182 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 1183 1184 1185 1186 1187 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 1188 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 1189 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 1190 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff 1191 1192 1193 1194 1195 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 1196 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 1197 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 1198 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff 1199 1200 1201 1202 1203 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 1204 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 1205 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 1206 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 1207 1208 1209 1210 1211 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 1212 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 1213 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 1214 #define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff 1215 1216 1217 1218 1219 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c 1220 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 1221 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 1222 #define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 1223 1224 1225 1226 1227 #define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c 1228 #define RX_MPDU_INFO_RESERVED_27A_LSB 1 1229 #define RX_MPDU_INFO_RESERVED_27A_MSB 31 1230 #define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe 1231 1232 1233 1234 1235 #define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 1236 #define RX_MPDU_INFO_RESERVED_28A_LSB 0 1237 #define RX_MPDU_INFO_RESERVED_28A_MSB 31 1238 #define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff 1239 1240 1241 1242 1243 #define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 1244 #define RX_MPDU_INFO_RESERVED_29A_LSB 0 1245 #define RX_MPDU_INFO_RESERVED_29A_MSB 31 1246 #define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff 1247 1248 1249 1250 #endif 1251