1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_MSDU_END_H_ 27 #define _RX_MSDU_END_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_MSDU_END 32 32 33 #define NUM_OF_QWORDS_RX_MSDU_END 16 34 35 36 struct rx_msdu_end { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t rxpcu_mpdu_filter_in_category : 2, 39 sw_frame_group_id : 7, 40 reserved_0 : 7, 41 phy_ppdu_id : 16; 42 uint32_t ip_hdr_chksum : 16, 43 reported_mpdu_length : 14, 44 reserved_1a : 2; 45 uint32_t reserved_2a : 8, 46 cce_super_rule : 6, 47 cce_classify_not_done_truncate : 1, 48 cce_classify_not_done_cce_dis : 1, 49 cumulative_l3_checksum : 16; 50 uint32_t rule_indication_31_0 : 32; 51 uint32_t ipv6_options_crc : 32; 52 uint32_t da_offset : 6, 53 sa_offset : 6, 54 da_offset_valid : 1, 55 sa_offset_valid : 1, 56 reserved_5a : 2, 57 l3_type : 16; 58 uint32_t rule_indication_63_32 : 32; 59 uint32_t tcp_seq_number : 32; 60 uint32_t tcp_ack_number : 32; 61 uint32_t tcp_flag : 9, 62 lro_eligible : 1, 63 reserved_9a : 6, 64 window_size : 16; 65 uint32_t sa_sw_peer_id : 16, 66 sa_idx_timeout : 1, 67 da_idx_timeout : 1, 68 to_ds : 1, 69 tid : 4, 70 sa_is_valid : 1, 71 da_is_valid : 1, 72 da_is_mcbc : 1, 73 l3_header_padding : 2, 74 first_msdu : 1, 75 last_msdu : 1, 76 fr_ds : 1, 77 ip_chksum_fail_copy : 1; 78 uint32_t sa_idx : 16, 79 da_idx_or_sw_peer_id : 16; 80 uint32_t msdu_drop : 1, 81 reo_destination_indication : 5, 82 flow_idx : 20, 83 use_ppe : 1, 84 mesh_sta : 2, 85 vlan_ctag_stripped : 1, 86 vlan_stag_stripped : 1, 87 fragment_flag : 1; 88 uint32_t fse_metadata : 32; 89 uint32_t cce_metadata : 16, 90 tcp_udp_chksum : 16; 91 uint32_t aggregation_count : 8, 92 flow_aggregation_continuation : 1, 93 fisa_timeout : 1, 94 tcp_udp_chksum_fail_copy : 1, 95 msdu_limit_error : 1, 96 flow_idx_timeout : 1, 97 flow_idx_invalid : 1, 98 cce_match : 1, 99 amsdu_parser_error : 1, 100 cumulative_ip_length : 16; 101 uint32_t key_id_octet : 8, 102 reserved_16a : 24; 103 uint32_t reserved_17a : 6, 104 service_code : 9, 105 priority_valid : 1, 106 intra_bss : 1, 107 dest_chip_id : 2, 108 multicast_echo : 1, 109 wds_learning_event : 1, 110 wds_roaming_event : 1, 111 wds_keep_alive_event : 1, 112 dest_chip_pmac_id : 1, 113 reserved_17b : 8; 114 uint32_t msdu_length : 14, 115 stbc : 1, 116 ipsec_esp : 1, 117 l3_offset : 7, 118 ipsec_ah : 1, 119 l4_offset : 8; 120 uint32_t msdu_number : 8, 121 decap_format : 2, 122 ipv4_proto : 1, 123 ipv6_proto : 1, 124 tcp_proto : 1, 125 udp_proto : 1, 126 ip_frag : 1, 127 tcp_only_ack : 1, 128 da_is_bcast_mcast : 1, 129 toeplitz_hash_sel : 2, 130 ip_fixed_header_valid : 1, 131 ip_extn_header_valid : 1, 132 tcp_udp_header_valid : 1, 133 mesh_control_present : 1, 134 ldpc : 1, 135 ip4_protocol_ip6_next_header : 8; 136 uint32_t vlan_ctag_ci : 16, 137 vlan_stag_ci : 16; 138 uint32_t peer_meta_data : 32; 139 uint32_t user_rssi : 8, 140 pkt_type : 4, 141 sgi : 2, 142 rate_mcs : 4, 143 receive_bandwidth : 3, 144 reception_type : 3, 145 mimo_ss_bitmap : 7, 146 msdu_done_copy : 1; 147 uint32_t flow_id_toeplitz : 32; 148 uint32_t ppdu_start_timestamp_63_32 : 32; 149 uint32_t sw_phy_meta_data : 32; 150 uint32_t ppdu_start_timestamp_31_0 : 32; 151 uint32_t toeplitz_hash_2_or_4 : 32; 152 uint32_t reserved_28a : 16, 153 sa_15_0 : 16; 154 uint32_t sa_47_16 : 32; 155 uint32_t first_mpdu : 1, 156 reserved_30a : 1, 157 mcast_bcast : 1, 158 ast_index_not_found : 1, 159 ast_index_timeout : 1, 160 power_mgmt : 1, 161 non_qos : 1, 162 null_data : 1, 163 mgmt_type : 1, 164 ctrl_type : 1, 165 more_data : 1, 166 eosp : 1, 167 a_msdu_error : 1, 168 reserved_30b : 1, 169 order : 1, 170 wifi_parser_error : 1, 171 overflow_err : 1, 172 msdu_length_err : 1, 173 tcp_udp_chksum_fail : 1, 174 ip_chksum_fail : 1, 175 sa_idx_invalid : 1, 176 da_idx_invalid : 1, 177 amsdu_addr_mismatch : 1, 178 rx_in_tx_decrypt_byp : 1, 179 encrypt_required : 1, 180 directed : 1, 181 buffer_fragment : 1, 182 mpdu_length_err : 1, 183 tkip_mic_err : 1, 184 decrypt_err : 1, 185 unencrypted_frame_err : 1, 186 fcs_err : 1; 187 uint32_t reserved_31a : 10, 188 decrypt_status_code : 3, 189 rx_bitmap_not_updated : 1, 190 reserved_31b : 17, 191 msdu_done : 1; 192 #else 193 uint32_t phy_ppdu_id : 16, 194 reserved_0 : 7, 195 sw_frame_group_id : 7, 196 rxpcu_mpdu_filter_in_category : 2; 197 uint32_t reserved_1a : 2, 198 reported_mpdu_length : 14, 199 ip_hdr_chksum : 16; 200 uint32_t cumulative_l3_checksum : 16, 201 cce_classify_not_done_cce_dis : 1, 202 cce_classify_not_done_truncate : 1, 203 cce_super_rule : 6, 204 reserved_2a : 8; 205 uint32_t rule_indication_31_0 : 32; 206 uint32_t ipv6_options_crc : 32; 207 uint32_t l3_type : 16, 208 reserved_5a : 2, 209 sa_offset_valid : 1, 210 da_offset_valid : 1, 211 sa_offset : 6, 212 da_offset : 6; 213 uint32_t rule_indication_63_32 : 32; 214 uint32_t tcp_seq_number : 32; 215 uint32_t tcp_ack_number : 32; 216 uint32_t window_size : 16, 217 reserved_9a : 6, 218 lro_eligible : 1, 219 tcp_flag : 9; 220 uint32_t ip_chksum_fail_copy : 1, 221 fr_ds : 1, 222 last_msdu : 1, 223 first_msdu : 1, 224 l3_header_padding : 2, 225 da_is_mcbc : 1, 226 da_is_valid : 1, 227 sa_is_valid : 1, 228 tid : 4, 229 to_ds : 1, 230 da_idx_timeout : 1, 231 sa_idx_timeout : 1, 232 sa_sw_peer_id : 16; 233 uint32_t da_idx_or_sw_peer_id : 16, 234 sa_idx : 16; 235 uint32_t fragment_flag : 1, 236 vlan_stag_stripped : 1, 237 vlan_ctag_stripped : 1, 238 mesh_sta : 2, 239 use_ppe : 1, 240 flow_idx : 20, 241 reo_destination_indication : 5, 242 msdu_drop : 1; 243 uint32_t fse_metadata : 32; 244 uint32_t tcp_udp_chksum : 16, 245 cce_metadata : 16; 246 uint32_t cumulative_ip_length : 16, 247 amsdu_parser_error : 1, 248 cce_match : 1, 249 flow_idx_invalid : 1, 250 flow_idx_timeout : 1, 251 msdu_limit_error : 1, 252 tcp_udp_chksum_fail_copy : 1, 253 fisa_timeout : 1, 254 flow_aggregation_continuation : 1, 255 aggregation_count : 8; 256 uint32_t reserved_16a : 24, 257 key_id_octet : 8; 258 uint32_t reserved_17b : 8, 259 dest_chip_pmac_id : 1, 260 wds_keep_alive_event : 1, 261 wds_roaming_event : 1, 262 wds_learning_event : 1, 263 multicast_echo : 1, 264 dest_chip_id : 2, 265 intra_bss : 1, 266 priority_valid : 1, 267 service_code : 9, 268 reserved_17a : 6; 269 uint32_t l4_offset : 8, 270 ipsec_ah : 1, 271 l3_offset : 7, 272 ipsec_esp : 1, 273 stbc : 1, 274 msdu_length : 14; 275 uint32_t ip4_protocol_ip6_next_header : 8, 276 ldpc : 1, 277 mesh_control_present : 1, 278 tcp_udp_header_valid : 1, 279 ip_extn_header_valid : 1, 280 ip_fixed_header_valid : 1, 281 toeplitz_hash_sel : 2, 282 da_is_bcast_mcast : 1, 283 tcp_only_ack : 1, 284 ip_frag : 1, 285 udp_proto : 1, 286 tcp_proto : 1, 287 ipv6_proto : 1, 288 ipv4_proto : 1, 289 decap_format : 2, 290 msdu_number : 8; 291 uint32_t vlan_stag_ci : 16, 292 vlan_ctag_ci : 16; 293 uint32_t peer_meta_data : 32; 294 uint32_t msdu_done_copy : 1, 295 mimo_ss_bitmap : 7, 296 reception_type : 3, 297 receive_bandwidth : 3, 298 rate_mcs : 4, 299 sgi : 2, 300 pkt_type : 4, 301 user_rssi : 8; 302 uint32_t flow_id_toeplitz : 32; 303 uint32_t ppdu_start_timestamp_63_32 : 32; 304 uint32_t sw_phy_meta_data : 32; 305 uint32_t ppdu_start_timestamp_31_0 : 32; 306 uint32_t toeplitz_hash_2_or_4 : 32; 307 uint32_t sa_15_0 : 16, 308 reserved_28a : 16; 309 uint32_t sa_47_16 : 32; 310 uint32_t fcs_err : 1, 311 unencrypted_frame_err : 1, 312 decrypt_err : 1, 313 tkip_mic_err : 1, 314 mpdu_length_err : 1, 315 buffer_fragment : 1, 316 directed : 1, 317 encrypt_required : 1, 318 rx_in_tx_decrypt_byp : 1, 319 amsdu_addr_mismatch : 1, 320 da_idx_invalid : 1, 321 sa_idx_invalid : 1, 322 ip_chksum_fail : 1, 323 tcp_udp_chksum_fail : 1, 324 msdu_length_err : 1, 325 overflow_err : 1, 326 wifi_parser_error : 1, 327 order : 1, 328 reserved_30b : 1, 329 a_msdu_error : 1, 330 eosp : 1, 331 more_data : 1, 332 ctrl_type : 1, 333 mgmt_type : 1, 334 null_data : 1, 335 non_qos : 1, 336 power_mgmt : 1, 337 ast_index_timeout : 1, 338 ast_index_not_found : 1, 339 mcast_bcast : 1, 340 reserved_30a : 1, 341 first_mpdu : 1; 342 uint32_t msdu_done : 1, 343 reserved_31b : 17, 344 rx_bitmap_not_updated : 1, 345 decrypt_status_code : 3, 346 reserved_31a : 10; 347 #endif 348 }; 349 350 351 352 353 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 354 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 355 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 356 #define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 357 358 359 360 361 #define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 362 #define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 363 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 364 #define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc 365 366 367 368 369 #define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 370 #define RX_MSDU_END_RESERVED_0_LSB 9 371 #define RX_MSDU_END_RESERVED_0_MSB 15 372 #define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 373 374 375 376 377 #define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 378 #define RX_MSDU_END_PHY_PPDU_ID_LSB 16 379 #define RX_MSDU_END_PHY_PPDU_ID_MSB 31 380 #define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 381 382 383 384 385 #define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 386 #define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 387 #define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 388 #define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 389 390 391 392 393 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 394 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 395 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 396 #define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 397 398 399 400 401 #define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 402 #define RX_MSDU_END_RESERVED_1A_LSB 62 403 #define RX_MSDU_END_RESERVED_1A_MSB 63 404 #define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 405 406 407 408 409 #define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 410 #define RX_MSDU_END_RESERVED_2A_LSB 0 411 #define RX_MSDU_END_RESERVED_2A_MSB 7 412 #define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff 413 414 415 416 417 #define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 418 #define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 419 #define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 420 #define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 421 422 423 424 425 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 426 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 427 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 428 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 429 430 431 432 433 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 434 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 435 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 436 #define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 437 438 439 440 441 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 442 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 443 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 444 #define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 445 446 447 448 449 #define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 450 #define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 451 #define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 452 #define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 453 454 455 456 457 #define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 458 #define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 459 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 460 #define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff 461 462 463 464 465 #define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 466 #define RX_MSDU_END_DA_OFFSET_LSB 32 467 #define RX_MSDU_END_DA_OFFSET_MSB 37 468 #define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 469 470 471 472 473 #define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 474 #define RX_MSDU_END_SA_OFFSET_LSB 38 475 #define RX_MSDU_END_SA_OFFSET_MSB 43 476 #define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 477 478 479 480 481 #define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 482 #define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 483 #define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 484 #define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 485 486 487 488 489 #define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 490 #define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 491 #define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 492 #define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 493 494 495 496 497 #define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 498 #define RX_MSDU_END_RESERVED_5A_LSB 46 499 #define RX_MSDU_END_RESERVED_5A_MSB 47 500 #define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 501 502 503 504 505 #define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 506 #define RX_MSDU_END_L3_TYPE_LSB 48 507 #define RX_MSDU_END_L3_TYPE_MSB 63 508 #define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 509 510 511 512 513 #define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 514 #define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 515 #define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 516 #define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff 517 518 519 520 521 #define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 522 #define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 523 #define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 524 #define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 525 526 527 528 529 #define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 530 #define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 531 #define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 532 #define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff 533 534 535 536 537 #define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 538 #define RX_MSDU_END_TCP_FLAG_LSB 32 539 #define RX_MSDU_END_TCP_FLAG_MSB 40 540 #define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 541 542 543 544 545 #define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 546 #define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 547 #define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 548 #define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 549 550 551 552 553 #define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 554 #define RX_MSDU_END_RESERVED_9A_LSB 42 555 #define RX_MSDU_END_RESERVED_9A_MSB 47 556 #define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 557 558 559 560 561 #define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 562 #define RX_MSDU_END_WINDOW_SIZE_LSB 48 563 #define RX_MSDU_END_WINDOW_SIZE_MSB 63 564 #define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 565 566 567 568 569 #define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 570 #define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 571 #define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 572 #define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff 573 574 575 576 577 #define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 578 #define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 579 #define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 580 #define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 581 582 583 584 585 #define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 586 #define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 587 #define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 588 #define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 589 590 591 592 593 #define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 594 #define RX_MSDU_END_TO_DS_LSB 18 595 #define RX_MSDU_END_TO_DS_MSB 18 596 #define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 597 598 599 600 601 #define RX_MSDU_END_TID_OFFSET 0x0000000000000028 602 #define RX_MSDU_END_TID_LSB 19 603 #define RX_MSDU_END_TID_MSB 22 604 #define RX_MSDU_END_TID_MASK 0x0000000000780000 605 606 607 608 609 #define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 610 #define RX_MSDU_END_SA_IS_VALID_LSB 23 611 #define RX_MSDU_END_SA_IS_VALID_MSB 23 612 #define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 613 614 615 616 617 #define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 618 #define RX_MSDU_END_DA_IS_VALID_LSB 24 619 #define RX_MSDU_END_DA_IS_VALID_MSB 24 620 #define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 621 622 623 624 625 #define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 626 #define RX_MSDU_END_DA_IS_MCBC_LSB 25 627 #define RX_MSDU_END_DA_IS_MCBC_MSB 25 628 #define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 629 630 631 632 633 #define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 634 #define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 635 #define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 636 #define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 637 638 639 640 641 #define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 642 #define RX_MSDU_END_FIRST_MSDU_LSB 28 643 #define RX_MSDU_END_FIRST_MSDU_MSB 28 644 #define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 645 646 647 648 649 #define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 650 #define RX_MSDU_END_LAST_MSDU_LSB 29 651 #define RX_MSDU_END_LAST_MSDU_MSB 29 652 #define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 653 654 655 656 657 #define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 658 #define RX_MSDU_END_FR_DS_LSB 30 659 #define RX_MSDU_END_FR_DS_MSB 30 660 #define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 661 662 663 664 665 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 666 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 667 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 668 #define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 669 670 671 672 673 #define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 674 #define RX_MSDU_END_SA_IDX_LSB 32 675 #define RX_MSDU_END_SA_IDX_MSB 47 676 #define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 677 678 679 680 681 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 682 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 683 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 684 #define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 685 686 687 688 689 #define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 690 #define RX_MSDU_END_MSDU_DROP_LSB 0 691 #define RX_MSDU_END_MSDU_DROP_MSB 0 692 #define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 693 694 695 696 697 #define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 698 #define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 699 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 700 #define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e 701 702 703 704 705 #define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 706 #define RX_MSDU_END_FLOW_IDX_LSB 6 707 #define RX_MSDU_END_FLOW_IDX_MSB 25 708 #define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 709 710 711 712 713 #define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 714 #define RX_MSDU_END_USE_PPE_LSB 26 715 #define RX_MSDU_END_USE_PPE_MSB 26 716 #define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 717 718 719 720 721 #define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 722 #define RX_MSDU_END_MESH_STA_LSB 27 723 #define RX_MSDU_END_MESH_STA_MSB 28 724 #define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 725 726 727 728 729 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 730 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 731 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 732 #define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 733 734 735 736 737 #define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 738 #define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 739 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 740 #define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 741 742 743 744 745 #define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 746 #define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 747 #define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 748 #define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 749 750 751 752 753 #define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 754 #define RX_MSDU_END_FSE_METADATA_LSB 32 755 #define RX_MSDU_END_FSE_METADATA_MSB 63 756 #define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 757 758 759 760 761 #define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 762 #define RX_MSDU_END_CCE_METADATA_LSB 0 763 #define RX_MSDU_END_CCE_METADATA_MSB 15 764 #define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff 765 766 767 768 769 #define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 770 #define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 771 #define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 772 #define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 773 774 775 776 777 #define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 778 #define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 779 #define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 780 #define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 781 782 783 784 785 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 786 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 787 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 788 #define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 789 790 791 792 793 #define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 794 #define RX_MSDU_END_FISA_TIMEOUT_LSB 41 795 #define RX_MSDU_END_FISA_TIMEOUT_MSB 41 796 #define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 797 798 799 800 801 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 802 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 803 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 804 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 805 806 807 808 809 #define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 810 #define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 811 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 812 #define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 813 814 815 816 817 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 818 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 819 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 820 #define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 821 822 823 824 825 #define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 826 #define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 827 #define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 828 #define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 829 830 831 832 833 #define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 834 #define RX_MSDU_END_CCE_MATCH_LSB 46 835 #define RX_MSDU_END_CCE_MATCH_MSB 46 836 #define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 837 838 839 840 841 #define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 842 #define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 843 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 844 #define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 845 846 847 848 849 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 850 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 851 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 852 #define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 853 854 855 856 857 #define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 858 #define RX_MSDU_END_KEY_ID_OCTET_LSB 0 859 #define RX_MSDU_END_KEY_ID_OCTET_MSB 7 860 #define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff 861 862 863 864 865 #define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 866 #define RX_MSDU_END_RESERVED_16A_LSB 8 867 #define RX_MSDU_END_RESERVED_16A_MSB 31 868 #define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 869 870 871 872 873 #define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 874 #define RX_MSDU_END_RESERVED_17A_LSB 32 875 #define RX_MSDU_END_RESERVED_17A_MSB 37 876 #define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 877 878 879 880 881 #define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 882 #define RX_MSDU_END_SERVICE_CODE_LSB 38 883 #define RX_MSDU_END_SERVICE_CODE_MSB 46 884 #define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 885 886 887 888 889 #define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 890 #define RX_MSDU_END_PRIORITY_VALID_LSB 47 891 #define RX_MSDU_END_PRIORITY_VALID_MSB 47 892 #define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 893 894 895 896 897 #define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 898 #define RX_MSDU_END_INTRA_BSS_LSB 48 899 #define RX_MSDU_END_INTRA_BSS_MSB 48 900 #define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 901 902 903 904 905 #define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 906 #define RX_MSDU_END_DEST_CHIP_ID_LSB 49 907 #define RX_MSDU_END_DEST_CHIP_ID_MSB 50 908 #define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 909 910 911 912 913 #define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 914 #define RX_MSDU_END_MULTICAST_ECHO_LSB 51 915 #define RX_MSDU_END_MULTICAST_ECHO_MSB 51 916 #define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 917 918 919 920 921 #define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 922 #define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 923 #define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 924 #define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 925 926 927 928 929 #define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 930 #define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 931 #define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 932 #define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 933 934 935 936 937 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 938 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 939 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 940 #define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 941 942 943 944 945 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_OFFSET 0x0000000000000040 946 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_LSB 55 947 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MSB 55 948 #define RX_MSDU_END_DEST_CHIP_PMAC_ID_MASK 0x0080000000000000 949 950 951 952 953 #define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 954 #define RX_MSDU_END_RESERVED_17B_LSB 56 955 #define RX_MSDU_END_RESERVED_17B_MSB 63 956 #define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 957 958 959 960 961 #define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 962 #define RX_MSDU_END_MSDU_LENGTH_LSB 0 963 #define RX_MSDU_END_MSDU_LENGTH_MSB 13 964 #define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff 965 966 967 968 969 #define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 970 #define RX_MSDU_END_STBC_LSB 14 971 #define RX_MSDU_END_STBC_MSB 14 972 #define RX_MSDU_END_STBC_MASK 0x0000000000004000 973 974 975 976 977 #define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 978 #define RX_MSDU_END_IPSEC_ESP_LSB 15 979 #define RX_MSDU_END_IPSEC_ESP_MSB 15 980 #define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 981 982 983 984 985 #define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 986 #define RX_MSDU_END_L3_OFFSET_LSB 16 987 #define RX_MSDU_END_L3_OFFSET_MSB 22 988 #define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 989 990 991 992 993 #define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 994 #define RX_MSDU_END_IPSEC_AH_LSB 23 995 #define RX_MSDU_END_IPSEC_AH_MSB 23 996 #define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 997 998 999 1000 1001 #define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 1002 #define RX_MSDU_END_L4_OFFSET_LSB 24 1003 #define RX_MSDU_END_L4_OFFSET_MSB 31 1004 #define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 1005 1006 1007 1008 1009 #define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 1010 #define RX_MSDU_END_MSDU_NUMBER_LSB 32 1011 #define RX_MSDU_END_MSDU_NUMBER_MSB 39 1012 #define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 1013 1014 1015 1016 1017 #define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 1018 #define RX_MSDU_END_DECAP_FORMAT_LSB 40 1019 #define RX_MSDU_END_DECAP_FORMAT_MSB 41 1020 #define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 1021 1022 1023 1024 1025 #define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 1026 #define RX_MSDU_END_IPV4_PROTO_LSB 42 1027 #define RX_MSDU_END_IPV4_PROTO_MSB 42 1028 #define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 1029 1030 1031 1032 1033 #define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 1034 #define RX_MSDU_END_IPV6_PROTO_LSB 43 1035 #define RX_MSDU_END_IPV6_PROTO_MSB 43 1036 #define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 1037 1038 1039 1040 1041 #define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 1042 #define RX_MSDU_END_TCP_PROTO_LSB 44 1043 #define RX_MSDU_END_TCP_PROTO_MSB 44 1044 #define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 1045 1046 1047 1048 1049 #define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 1050 #define RX_MSDU_END_UDP_PROTO_LSB 45 1051 #define RX_MSDU_END_UDP_PROTO_MSB 45 1052 #define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 1053 1054 1055 1056 1057 #define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 1058 #define RX_MSDU_END_IP_FRAG_LSB 46 1059 #define RX_MSDU_END_IP_FRAG_MSB 46 1060 #define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 1061 1062 1063 1064 1065 #define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 1066 #define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 1067 #define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 1068 #define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 1069 1070 1071 1072 1073 #define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 1074 #define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 1075 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 1076 #define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 1077 1078 1079 1080 1081 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 1082 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 1083 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 1084 #define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 1085 1086 1087 1088 1089 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 1090 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 1091 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 1092 #define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 1093 1094 1095 1096 1097 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 1098 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 1099 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 1100 #define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 1101 1102 1103 1104 1105 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 1106 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 1107 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 1108 #define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 1109 1110 1111 1112 1113 #define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 1114 #define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 1115 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 1116 #define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 1117 1118 1119 1120 1121 #define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 1122 #define RX_MSDU_END_LDPC_LSB 55 1123 #define RX_MSDU_END_LDPC_MSB 55 1124 #define RX_MSDU_END_LDPC_MASK 0x0080000000000000 1125 1126 1127 1128 1129 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 1130 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 1131 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 1132 #define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 1133 1134 1135 1136 1137 #define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 1138 #define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 1139 #define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 1140 #define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff 1141 1142 1143 1144 1145 #define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 1146 #define RX_MSDU_END_VLAN_STAG_CI_LSB 16 1147 #define RX_MSDU_END_VLAN_STAG_CI_MSB 31 1148 #define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 1149 1150 1151 1152 1153 #define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 1154 #define RX_MSDU_END_PEER_META_DATA_LSB 32 1155 #define RX_MSDU_END_PEER_META_DATA_MSB 63 1156 #define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 1157 1158 1159 1160 1161 #define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 1162 #define RX_MSDU_END_USER_RSSI_LSB 0 1163 #define RX_MSDU_END_USER_RSSI_MSB 7 1164 #define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff 1165 1166 1167 1168 1169 #define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 1170 #define RX_MSDU_END_PKT_TYPE_LSB 8 1171 #define RX_MSDU_END_PKT_TYPE_MSB 11 1172 #define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 1173 1174 1175 1176 1177 #define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 1178 #define RX_MSDU_END_SGI_LSB 12 1179 #define RX_MSDU_END_SGI_MSB 13 1180 #define RX_MSDU_END_SGI_MASK 0x0000000000003000 1181 1182 1183 1184 1185 #define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 1186 #define RX_MSDU_END_RATE_MCS_LSB 14 1187 #define RX_MSDU_END_RATE_MCS_MSB 17 1188 #define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 1189 1190 1191 1192 1193 #define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 1194 #define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 1195 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 1196 #define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 1197 1198 1199 1200 1201 #define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 1202 #define RX_MSDU_END_RECEPTION_TYPE_LSB 21 1203 #define RX_MSDU_END_RECEPTION_TYPE_MSB 23 1204 #define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 1205 1206 1207 1208 1209 #define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 1210 #define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 1211 #define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 1212 #define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 1213 1214 1215 1216 1217 #define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 1218 #define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 1219 #define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 1220 #define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 1221 1222 1223 1224 1225 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 1226 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 1227 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 1228 #define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 1229 1230 1231 1232 1233 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 1234 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 1235 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 1236 #define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff 1237 1238 1239 1240 1241 #define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 1242 #define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 1243 #define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 1244 #define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 1245 1246 1247 1248 1249 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 1250 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 1251 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 1252 #define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 1253 1254 1255 1256 1257 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 1258 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 1259 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 1260 #define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 1261 1262 1263 1264 1265 #define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 1266 #define RX_MSDU_END_RESERVED_28A_LSB 0 1267 #define RX_MSDU_END_RESERVED_28A_MSB 15 1268 #define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff 1269 1270 1271 1272 1273 #define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 1274 #define RX_MSDU_END_SA_15_0_LSB 16 1275 #define RX_MSDU_END_SA_15_0_MSB 31 1276 #define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 1277 1278 1279 1280 1281 #define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 1282 #define RX_MSDU_END_SA_47_16_LSB 32 1283 #define RX_MSDU_END_SA_47_16_MSB 63 1284 #define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 1285 1286 1287 1288 1289 #define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 1290 #define RX_MSDU_END_FIRST_MPDU_LSB 0 1291 #define RX_MSDU_END_FIRST_MPDU_MSB 0 1292 #define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 1293 1294 1295 1296 1297 #define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 1298 #define RX_MSDU_END_RESERVED_30A_LSB 1 1299 #define RX_MSDU_END_RESERVED_30A_MSB 1 1300 #define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 1301 1302 1303 1304 1305 #define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 1306 #define RX_MSDU_END_MCAST_BCAST_LSB 2 1307 #define RX_MSDU_END_MCAST_BCAST_MSB 2 1308 #define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 1309 1310 1311 1312 1313 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 1314 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 1315 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 1316 #define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 1317 1318 1319 1320 1321 #define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 1322 #define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 1323 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 1324 #define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 1325 1326 1327 1328 1329 #define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 1330 #define RX_MSDU_END_POWER_MGMT_LSB 5 1331 #define RX_MSDU_END_POWER_MGMT_MSB 5 1332 #define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 1333 1334 1335 1336 1337 #define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 1338 #define RX_MSDU_END_NON_QOS_LSB 6 1339 #define RX_MSDU_END_NON_QOS_MSB 6 1340 #define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 1341 1342 1343 1344 1345 #define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 1346 #define RX_MSDU_END_NULL_DATA_LSB 7 1347 #define RX_MSDU_END_NULL_DATA_MSB 7 1348 #define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 1349 1350 1351 1352 1353 #define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 1354 #define RX_MSDU_END_MGMT_TYPE_LSB 8 1355 #define RX_MSDU_END_MGMT_TYPE_MSB 8 1356 #define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 1357 1358 1359 1360 1361 #define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 1362 #define RX_MSDU_END_CTRL_TYPE_LSB 9 1363 #define RX_MSDU_END_CTRL_TYPE_MSB 9 1364 #define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 1365 1366 1367 1368 1369 #define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 1370 #define RX_MSDU_END_MORE_DATA_LSB 10 1371 #define RX_MSDU_END_MORE_DATA_MSB 10 1372 #define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 1373 1374 1375 1376 1377 #define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 1378 #define RX_MSDU_END_EOSP_LSB 11 1379 #define RX_MSDU_END_EOSP_MSB 11 1380 #define RX_MSDU_END_EOSP_MASK 0x0000000000000800 1381 1382 1383 1384 1385 #define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 1386 #define RX_MSDU_END_A_MSDU_ERROR_LSB 12 1387 #define RX_MSDU_END_A_MSDU_ERROR_MSB 12 1388 #define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 1389 1390 1391 1392 1393 #define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 1394 #define RX_MSDU_END_RESERVED_30B_LSB 13 1395 #define RX_MSDU_END_RESERVED_30B_MSB 13 1396 #define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 1397 1398 1399 1400 1401 #define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 1402 #define RX_MSDU_END_ORDER_LSB 14 1403 #define RX_MSDU_END_ORDER_MSB 14 1404 #define RX_MSDU_END_ORDER_MASK 0x0000000000004000 1405 1406 1407 1408 1409 #define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 1410 #define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 1411 #define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 1412 #define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 1413 1414 1415 1416 1417 #define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 1418 #define RX_MSDU_END_OVERFLOW_ERR_LSB 16 1419 #define RX_MSDU_END_OVERFLOW_ERR_MSB 16 1420 #define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 1421 1422 1423 1424 1425 #define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 1426 #define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 1427 #define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 1428 #define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 1429 1430 1431 1432 1433 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 1434 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 1435 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 1436 #define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 1437 1438 1439 1440 1441 #define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 1442 #define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 1443 #define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 1444 #define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 1445 1446 1447 1448 1449 #define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 1450 #define RX_MSDU_END_SA_IDX_INVALID_LSB 20 1451 #define RX_MSDU_END_SA_IDX_INVALID_MSB 20 1452 #define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 1453 1454 1455 1456 1457 #define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 1458 #define RX_MSDU_END_DA_IDX_INVALID_LSB 21 1459 #define RX_MSDU_END_DA_IDX_INVALID_MSB 21 1460 #define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 1461 1462 1463 1464 1465 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 1466 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 1467 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 1468 #define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 1469 1470 1471 1472 1473 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 1474 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 1475 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 1476 #define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 1477 1478 1479 1480 1481 #define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 1482 #define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 1483 #define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 1484 #define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 1485 1486 1487 1488 1489 #define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 1490 #define RX_MSDU_END_DIRECTED_LSB 25 1491 #define RX_MSDU_END_DIRECTED_MSB 25 1492 #define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 1493 1494 1495 1496 1497 #define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 1498 #define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 1499 #define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 1500 #define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 1501 1502 1503 1504 1505 #define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 1506 #define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 1507 #define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 1508 #define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 1509 1510 1511 1512 1513 #define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 1514 #define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 1515 #define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 1516 #define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 1517 1518 1519 1520 1521 #define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 1522 #define RX_MSDU_END_DECRYPT_ERR_LSB 29 1523 #define RX_MSDU_END_DECRYPT_ERR_MSB 29 1524 #define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 1525 1526 1527 1528 1529 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 1530 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 1531 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 1532 #define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 1533 1534 1535 1536 1537 #define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 1538 #define RX_MSDU_END_FCS_ERR_LSB 31 1539 #define RX_MSDU_END_FCS_ERR_MSB 31 1540 #define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 1541 1542 1543 1544 1545 #define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 1546 #define RX_MSDU_END_RESERVED_31A_LSB 32 1547 #define RX_MSDU_END_RESERVED_31A_MSB 41 1548 #define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 1549 1550 1551 1552 1553 #define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 1554 #define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 1555 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 1556 #define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 1557 1558 1559 1560 1561 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 1562 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 1563 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 1564 #define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 1565 1566 1567 1568 1569 #define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 1570 #define RX_MSDU_END_RESERVED_31B_LSB 46 1571 #define RX_MSDU_END_RESERVED_31B_MSB 62 1572 #define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 1573 1574 1575 1576 1577 #define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 1578 #define RX_MSDU_END_MSDU_DONE_LSB 63 1579 #define RX_MSDU_END_MSDU_DONE_MSB 63 1580 #define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 1581 1582 1583 1584 #endif 1585