1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_PPDU_END_USER_STATS_H_ 27 #define _RX_PPDU_END_USER_STATS_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "rx_rxpcu_classification_overview.h" 32 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 24 33 34 #define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 12 35 36 37 struct rx_ppdu_end_user_stats { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 struct rx_rxpcu_classification_overview rxpcu_classification_details; 40 uint32_t sta_full_aid : 13, 41 mcs : 4, 42 nss : 3, 43 expected_response_ack_or_ba : 1, 44 reserved_1a : 11; 45 uint32_t sw_peer_id : 16, 46 mpdu_cnt_fcs_err : 11, 47 sw2rxdma0_buf_source_used : 1, 48 fw2rxdma_pmac0_buf_source_used : 1, 49 sw2rxdma1_buf_source_used : 1, 50 sw2rxdma_exception_buf_source_used : 1, 51 fw2rxdma_pmac1_buf_source_used : 1; 52 uint32_t mpdu_cnt_fcs_ok : 11, 53 frame_control_info_valid : 1, 54 qos_control_info_valid : 1, 55 ht_control_info_valid : 1, 56 data_sequence_control_info_valid : 1, 57 ht_control_info_null_valid : 1, 58 rxdma2fw_pmac1_ring_used : 1, 59 rxdma2reo_ring_used : 1, 60 rxdma2fw_pmac0_ring_used : 1, 61 rxdma2sw_ring_used : 1, 62 rxdma_release_ring_used : 1, 63 ht_control_field_pkt_type : 4, 64 rxdma2reo_remote0_ring_used : 1, 65 rxdma2reo_remote1_ring_used : 1, 66 reserved_3b : 5; 67 uint32_t ast_index : 16, 68 frame_control_field : 16; 69 uint32_t first_data_seq_ctrl : 16, 70 qos_control_field : 16; 71 uint32_t ht_control_field : 32; 72 uint32_t fcs_ok_bitmap_31_0 : 32; 73 uint32_t fcs_ok_bitmap_63_32 : 32; 74 uint32_t udp_msdu_count : 16, 75 tcp_msdu_count : 16; 76 uint32_t other_msdu_count : 16, 77 tcp_ack_msdu_count : 16; 78 uint32_t sw_response_reference_ptr : 32; 79 uint32_t received_qos_data_tid_bitmap : 16, 80 received_qos_data_tid_eosp_bitmap : 16; 81 uint32_t qosctrl_15_8_tid0 : 8, 82 qosctrl_15_8_tid1 : 8, 83 qosctrl_15_8_tid2 : 8, 84 qosctrl_15_8_tid3 : 8; 85 uint32_t qosctrl_15_8_tid4 : 8, 86 qosctrl_15_8_tid5 : 8, 87 qosctrl_15_8_tid6 : 8, 88 qosctrl_15_8_tid7 : 8; 89 uint32_t qosctrl_15_8_tid8 : 8, 90 qosctrl_15_8_tid9 : 8, 91 qosctrl_15_8_tid10 : 8, 92 qosctrl_15_8_tid11 : 8; 93 uint32_t qosctrl_15_8_tid12 : 8, 94 qosctrl_15_8_tid13 : 8, 95 qosctrl_15_8_tid14 : 8, 96 qosctrl_15_8_tid15 : 8; 97 uint32_t mpdu_ok_byte_count : 25, 98 ampdu_delim_ok_count_6_0 : 7; 99 uint32_t ampdu_delim_err_count : 25, 100 ampdu_delim_ok_count_13_7 : 7; 101 uint32_t mpdu_err_byte_count : 25, 102 ampdu_delim_ok_count_20_14 : 7; 103 uint32_t non_consecutive_delimiter_err : 16, 104 retried_msdu_count : 16; 105 uint32_t ht_control_null_field : 32; 106 uint32_t sw_response_reference_ptr_ext : 32; 107 uint32_t corrupted_due_to_fifo_delay : 1, 108 frame_control_info_null_valid : 1, 109 frame_control_field_null : 16, 110 retried_mpdu_count : 11, 111 reserved_23a : 3; 112 #else 113 struct rx_rxpcu_classification_overview rxpcu_classification_details; 114 uint32_t reserved_1a : 11, 115 expected_response_ack_or_ba : 1, 116 nss : 3, 117 mcs : 4, 118 sta_full_aid : 13; 119 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 120 sw2rxdma_exception_buf_source_used : 1, 121 sw2rxdma1_buf_source_used : 1, 122 fw2rxdma_pmac0_buf_source_used : 1, 123 sw2rxdma0_buf_source_used : 1, 124 mpdu_cnt_fcs_err : 11, 125 sw_peer_id : 16; 126 uint32_t reserved_3b : 5, 127 rxdma2reo_remote1_ring_used : 1, 128 rxdma2reo_remote0_ring_used : 1, 129 ht_control_field_pkt_type : 4, 130 rxdma_release_ring_used : 1, 131 rxdma2sw_ring_used : 1, 132 rxdma2fw_pmac0_ring_used : 1, 133 rxdma2reo_ring_used : 1, 134 rxdma2fw_pmac1_ring_used : 1, 135 ht_control_info_null_valid : 1, 136 data_sequence_control_info_valid : 1, 137 ht_control_info_valid : 1, 138 qos_control_info_valid : 1, 139 frame_control_info_valid : 1, 140 mpdu_cnt_fcs_ok : 11; 141 uint32_t frame_control_field : 16, 142 ast_index : 16; 143 uint32_t qos_control_field : 16, 144 first_data_seq_ctrl : 16; 145 uint32_t ht_control_field : 32; 146 uint32_t fcs_ok_bitmap_31_0 : 32; 147 uint32_t fcs_ok_bitmap_63_32 : 32; 148 uint32_t tcp_msdu_count : 16, 149 udp_msdu_count : 16; 150 uint32_t tcp_ack_msdu_count : 16, 151 other_msdu_count : 16; 152 uint32_t sw_response_reference_ptr : 32; 153 uint32_t received_qos_data_tid_eosp_bitmap : 16, 154 received_qos_data_tid_bitmap : 16; 155 uint32_t qosctrl_15_8_tid3 : 8, 156 qosctrl_15_8_tid2 : 8, 157 qosctrl_15_8_tid1 : 8, 158 qosctrl_15_8_tid0 : 8; 159 uint32_t qosctrl_15_8_tid7 : 8, 160 qosctrl_15_8_tid6 : 8, 161 qosctrl_15_8_tid5 : 8, 162 qosctrl_15_8_tid4 : 8; 163 uint32_t qosctrl_15_8_tid11 : 8, 164 qosctrl_15_8_tid10 : 8, 165 qosctrl_15_8_tid9 : 8, 166 qosctrl_15_8_tid8 : 8; 167 uint32_t qosctrl_15_8_tid15 : 8, 168 qosctrl_15_8_tid14 : 8, 169 qosctrl_15_8_tid13 : 8, 170 qosctrl_15_8_tid12 : 8; 171 uint32_t ampdu_delim_ok_count_6_0 : 7, 172 mpdu_ok_byte_count : 25; 173 uint32_t ampdu_delim_ok_count_13_7 : 7, 174 ampdu_delim_err_count : 25; 175 uint32_t ampdu_delim_ok_count_20_14 : 7, 176 mpdu_err_byte_count : 25; 177 uint32_t retried_msdu_count : 16, 178 non_consecutive_delimiter_err : 16; 179 uint32_t ht_control_null_field : 32; 180 uint32_t sw_response_reference_ptr_ext : 32; 181 uint32_t reserved_23a : 3, 182 retried_mpdu_count : 11, 183 frame_control_field_null : 16, 184 frame_control_info_null_valid : 1, 185 corrupted_due_to_fifo_delay : 1; 186 #endif 187 }; 188 189 190 191 192 193 194 195 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 196 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 197 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 198 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 199 200 201 202 203 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 204 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 205 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 206 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 207 208 209 210 211 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 212 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 213 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 214 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 215 216 217 218 219 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 220 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 221 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 222 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 223 224 225 226 227 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 228 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 229 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 230 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 231 232 233 234 235 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 236 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 237 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 238 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 239 240 241 242 243 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 244 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 245 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 246 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 247 248 249 250 251 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 252 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 253 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 254 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 255 256 257 258 259 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 260 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 261 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 262 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 263 264 265 266 267 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 268 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 269 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 270 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 271 272 273 274 275 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 276 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 277 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 278 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 279 280 281 282 283 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 284 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 285 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 286 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 287 288 289 290 291 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 292 #define RX_PPDU_END_USER_STATS_MCS_LSB 45 293 #define RX_PPDU_END_USER_STATS_MCS_MSB 48 294 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 295 296 297 298 299 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 300 #define RX_PPDU_END_USER_STATS_NSS_LSB 49 301 #define RX_PPDU_END_USER_STATS_NSS_MSB 51 302 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 303 304 305 306 307 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 308 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 309 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 310 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 311 312 313 314 315 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 316 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 317 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 318 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 319 320 321 322 323 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 324 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 325 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 326 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff 327 328 329 330 331 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 332 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 333 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 334 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 335 336 337 338 339 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 340 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 341 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 342 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 343 344 345 346 347 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 348 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 349 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 350 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 351 352 353 354 355 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 356 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 357 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 358 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 359 360 361 362 363 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 364 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 365 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 366 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 367 368 369 370 371 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 372 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 373 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 374 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 375 376 377 378 379 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 380 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 381 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 382 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 383 384 385 386 387 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 388 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 389 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 390 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 391 392 393 394 395 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 396 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 397 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 398 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 399 400 401 402 403 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 404 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 405 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 406 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 407 408 409 410 411 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 412 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 413 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 414 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 415 416 417 418 419 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 420 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 421 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 422 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 423 424 425 426 427 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 428 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 429 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 430 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 431 432 433 434 435 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 436 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 437 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 438 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 439 440 441 442 443 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 444 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 445 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 446 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 447 448 449 450 451 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 452 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 453 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 454 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 455 456 457 458 459 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 460 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 461 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 462 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 463 464 465 466 467 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 468 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 469 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 470 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 471 472 473 474 475 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 476 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 477 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 478 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 479 480 481 482 483 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 484 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 485 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 486 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 487 488 489 490 491 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 492 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 493 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 494 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 495 496 497 498 499 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 500 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 501 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 502 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff 503 504 505 506 507 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 508 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 509 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 510 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 511 512 513 514 515 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 516 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 517 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 518 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 519 520 521 522 523 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 524 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 525 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 526 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 527 528 529 530 531 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 532 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 533 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 534 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff 535 536 537 538 539 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 540 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 541 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 542 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 543 544 545 546 547 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 548 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 549 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 550 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff 551 552 553 554 555 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 556 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 557 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 558 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 559 560 561 562 563 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 564 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 565 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 566 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 567 568 569 570 571 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 572 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 573 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 574 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff 575 576 577 578 579 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 580 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 581 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 582 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 583 584 585 586 587 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 588 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 589 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 590 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 591 592 593 594 595 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 596 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 597 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 598 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff 599 600 601 602 603 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 604 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 605 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 606 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 607 608 609 610 611 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 612 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 613 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 614 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 615 616 617 618 619 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 620 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 621 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 622 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 623 624 625 626 627 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 628 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 629 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 630 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 631 632 633 634 635 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 636 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 637 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 638 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 639 640 641 642 643 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 644 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 645 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 646 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff 647 648 649 650 651 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 652 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 653 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 654 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 655 656 657 658 659 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 660 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 661 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 662 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 663 664 665 666 667 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 668 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 669 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 670 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 671 672 673 674 675 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 676 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 677 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 678 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 679 680 681 682 683 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 684 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 685 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 686 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 687 688 689 690 691 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 692 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 693 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 694 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 695 696 697 698 699 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 700 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 701 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 702 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 703 704 705 706 707 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 708 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 709 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 710 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff 711 712 713 714 715 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 716 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 717 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 718 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 719 720 721 722 723 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 724 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 725 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 726 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 727 728 729 730 731 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 732 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 733 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 734 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 735 736 737 738 739 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 740 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 741 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 742 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 743 744 745 746 747 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 748 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 749 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 750 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 751 752 753 754 755 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 756 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 757 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 758 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff 759 760 761 762 763 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 764 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 765 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 766 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 767 768 769 770 771 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 772 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 773 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 774 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 775 776 777 778 779 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 780 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 781 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 782 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 783 784 785 786 787 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 788 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 789 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 790 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff 791 792 793 794 795 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 796 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 797 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 798 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 799 800 801 802 803 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 804 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 805 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 806 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 807 808 809 810 811 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 812 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 813 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 814 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff 815 816 817 818 819 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 820 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 821 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 822 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 823 824 825 826 827 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 828 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 829 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 830 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 831 832 833 834 835 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 836 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 837 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 838 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 839 840 841 842 843 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 844 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 845 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 846 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 847 848 849 850 851 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 852 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 853 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 854 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 855 856 857 858 #endif 859