1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_PPDU_START_H_ 27 #define _RX_PPDU_START_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_PPDU_START 6 32 33 #define NUM_OF_QWORDS_RX_PPDU_START 3 34 35 36 struct rx_ppdu_start { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 uint32_t phy_ppdu_id : 16, 39 preamble_time_to_rxframe : 8, 40 reserved_0a : 8; 41 uint32_t sw_phy_meta_data : 32; 42 uint32_t ppdu_start_timestamp_31_0 : 32; 43 uint32_t ppdu_start_timestamp_63_32 : 32; 44 uint32_t rxframe_assert_timestamp : 32; 45 uint32_t tlv64_padding : 32; 46 #else 47 uint32_t reserved_0a : 8, 48 preamble_time_to_rxframe : 8, 49 phy_ppdu_id : 16; 50 uint32_t sw_phy_meta_data : 32; 51 uint32_t ppdu_start_timestamp_31_0 : 32; 52 uint32_t ppdu_start_timestamp_63_32 : 32; 53 uint32_t rxframe_assert_timestamp : 32; 54 uint32_t tlv64_padding : 32; 55 #endif 56 }; 57 58 59 60 61 #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 62 #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 63 #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 64 #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff 65 66 67 68 69 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 70 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 71 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 72 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 73 74 75 76 77 #define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 78 #define RX_PPDU_START_RESERVED_0A_LSB 24 79 #define RX_PPDU_START_RESERVED_0A_MSB 31 80 #define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 81 82 83 84 85 #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 86 #define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 87 #define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 88 #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 89 90 91 92 93 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 94 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 95 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 96 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff 97 98 99 100 101 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 102 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 103 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 104 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 105 106 107 108 109 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 110 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 111 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 112 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff 113 114 115 116 117 #define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 118 #define RX_PPDU_START_TLV64_PADDING_LSB 32 119 #define RX_PPDU_START_TLV64_PADDING_MSB 63 120 #define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 121 122 123 124 #endif 125