1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_REO_QUEUE_H_ 27 #define _RX_REO_QUEUE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_descriptor_header.h" 32 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 33 34 35 struct rx_reo_queue { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct uniform_descriptor_header descriptor_header; 38 uint32_t receive_queue_number : 16, 39 reserved_1b : 16; 40 uint32_t vld : 1, 41 associated_link_descriptor_counter : 2, 42 disable_duplicate_detection : 1, 43 soft_reorder_enable : 1, 44 ac : 2, 45 bar : 1, 46 rty : 1, 47 chk_2k_mode : 1, 48 oor_mode : 1, 49 ba_window_size : 10, 50 pn_check_needed : 1, 51 pn_shall_be_even : 1, 52 pn_shall_be_uneven : 1, 53 pn_handling_enable : 1, 54 pn_size : 2, 55 ignore_ampdu_flag : 1, 56 reserved_2b : 4; 57 uint32_t svld : 1, 58 ssn : 12, 59 current_index : 10, 60 seq_2k_error_detected_flag : 1, 61 pn_error_detected_flag : 1, 62 reserved_3a : 6, 63 pn_valid : 1; 64 uint32_t pn_31_0 : 32; 65 uint32_t pn_63_32 : 32; 66 uint32_t pn_95_64 : 32; 67 uint32_t pn_127_96 : 32; 68 uint32_t last_rx_enqueue_timestamp : 32; 69 uint32_t last_rx_dequeue_timestamp : 32; 70 uint32_t ptr_to_next_aging_queue_31_0 : 32; 71 uint32_t ptr_to_next_aging_queue_39_32 : 8, 72 reserved_11a : 24; 73 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 74 uint32_t ptr_to_previous_aging_queue_39_32 : 8, 75 statistics_counter_index : 6, 76 reserved_13a : 18; 77 uint32_t rx_bitmap_31_0 : 32; 78 uint32_t rx_bitmap_63_32 : 32; 79 uint32_t rx_bitmap_95_64 : 32; 80 uint32_t rx_bitmap_127_96 : 32; 81 uint32_t rx_bitmap_159_128 : 32; 82 uint32_t rx_bitmap_191_160 : 32; 83 uint32_t rx_bitmap_223_192 : 32; 84 uint32_t rx_bitmap_255_224 : 32; 85 uint32_t rx_bitmap_287_256 : 32; 86 uint32_t current_mpdu_count : 7, 87 current_msdu_count : 25; 88 uint32_t last_sn_reg_index : 4, 89 timeout_count : 6, 90 forward_due_to_bar_count : 6, 91 duplicate_count : 16; 92 uint32_t frames_in_order_count : 24, 93 bar_received_count : 8; 94 uint32_t mpdu_frames_processed_count : 32; 95 uint32_t msdu_frames_processed_count : 32; 96 uint32_t total_processed_byte_count : 32; 97 uint32_t late_receive_mpdu_count : 12, 98 window_jump_2k : 4, 99 hole_count : 16; 100 uint32_t aging_drop_mpdu_count : 16, 101 aging_drop_interval : 8, 102 reserved_30 : 8; 103 uint32_t reserved_31 : 32; 104 #else 105 struct uniform_descriptor_header descriptor_header; 106 uint32_t reserved_1b : 16, 107 receive_queue_number : 16; 108 uint32_t reserved_2b : 4, 109 ignore_ampdu_flag : 1, 110 pn_size : 2, 111 pn_handling_enable : 1, 112 pn_shall_be_uneven : 1, 113 pn_shall_be_even : 1, 114 pn_check_needed : 1, 115 ba_window_size : 10, 116 oor_mode : 1, 117 chk_2k_mode : 1, 118 rty : 1, 119 bar : 1, 120 ac : 2, 121 soft_reorder_enable : 1, 122 disable_duplicate_detection : 1, 123 associated_link_descriptor_counter : 2, 124 vld : 1; 125 uint32_t pn_valid : 1, 126 reserved_3a : 6, 127 pn_error_detected_flag : 1, 128 seq_2k_error_detected_flag : 1, 129 current_index : 10, 130 ssn : 12, 131 svld : 1; 132 uint32_t pn_31_0 : 32; 133 uint32_t pn_63_32 : 32; 134 uint32_t pn_95_64 : 32; 135 uint32_t pn_127_96 : 32; 136 uint32_t last_rx_enqueue_timestamp : 32; 137 uint32_t last_rx_dequeue_timestamp : 32; 138 uint32_t ptr_to_next_aging_queue_31_0 : 32; 139 uint32_t reserved_11a : 24, 140 ptr_to_next_aging_queue_39_32 : 8; 141 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 142 uint32_t reserved_13a : 18, 143 statistics_counter_index : 6, 144 ptr_to_previous_aging_queue_39_32 : 8; 145 uint32_t rx_bitmap_31_0 : 32; 146 uint32_t rx_bitmap_63_32 : 32; 147 uint32_t rx_bitmap_95_64 : 32; 148 uint32_t rx_bitmap_127_96 : 32; 149 uint32_t rx_bitmap_159_128 : 32; 150 uint32_t rx_bitmap_191_160 : 32; 151 uint32_t rx_bitmap_223_192 : 32; 152 uint32_t rx_bitmap_255_224 : 32; 153 uint32_t rx_bitmap_287_256 : 32; 154 uint32_t current_msdu_count : 25, 155 current_mpdu_count : 7; 156 uint32_t duplicate_count : 16, 157 forward_due_to_bar_count : 6, 158 timeout_count : 6, 159 last_sn_reg_index : 4; 160 uint32_t bar_received_count : 8, 161 frames_in_order_count : 24; 162 uint32_t mpdu_frames_processed_count : 32; 163 uint32_t msdu_frames_processed_count : 32; 164 uint32_t total_processed_byte_count : 32; 165 uint32_t hole_count : 16, 166 window_jump_2k : 4, 167 late_receive_mpdu_count : 12; 168 uint32_t reserved_30 : 8, 169 aging_drop_interval : 8, 170 aging_drop_mpdu_count : 16; 171 uint32_t reserved_31 : 32; 172 #endif 173 }; 174 175 176 177 178 179 180 181 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 182 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 183 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 184 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 185 186 187 188 189 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 190 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 191 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 192 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 193 194 195 196 197 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 198 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 199 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 200 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 201 202 203 204 205 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 206 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 207 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 208 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 209 210 211 212 213 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 214 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 215 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 216 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 217 218 219 220 221 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 222 #define RX_REO_QUEUE_VLD_LSB 0 223 #define RX_REO_QUEUE_VLD_MSB 0 224 #define RX_REO_QUEUE_VLD_MASK 0x00000001 225 226 227 228 229 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 230 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 231 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 232 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 233 234 235 236 237 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 238 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 239 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 240 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 241 242 243 244 245 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 246 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 247 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 248 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 249 250 251 252 253 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 254 #define RX_REO_QUEUE_AC_LSB 5 255 #define RX_REO_QUEUE_AC_MSB 6 256 #define RX_REO_QUEUE_AC_MASK 0x00000060 257 258 259 260 261 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 262 #define RX_REO_QUEUE_BAR_LSB 7 263 #define RX_REO_QUEUE_BAR_MSB 7 264 #define RX_REO_QUEUE_BAR_MASK 0x00000080 265 266 267 268 269 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 270 #define RX_REO_QUEUE_RTY_LSB 8 271 #define RX_REO_QUEUE_RTY_MSB 8 272 #define RX_REO_QUEUE_RTY_MASK 0x00000100 273 274 275 276 277 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 278 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 279 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 280 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 281 282 283 284 285 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 286 #define RX_REO_QUEUE_OOR_MODE_LSB 10 287 #define RX_REO_QUEUE_OOR_MODE_MSB 10 288 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 289 290 291 292 293 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 294 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 295 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 296 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 297 298 299 300 301 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 302 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 303 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 304 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 305 306 307 308 309 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 310 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 311 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 312 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 313 314 315 316 317 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 318 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 319 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 320 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 321 322 323 324 325 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 326 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 327 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 328 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 329 330 331 332 333 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 334 #define RX_REO_QUEUE_PN_SIZE_LSB 25 335 #define RX_REO_QUEUE_PN_SIZE_MSB 26 336 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 337 338 339 340 341 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 342 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 343 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 344 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 345 346 347 348 349 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 350 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 351 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 352 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 353 354 355 356 357 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 358 #define RX_REO_QUEUE_SVLD_LSB 0 359 #define RX_REO_QUEUE_SVLD_MSB 0 360 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 361 362 363 364 365 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 366 #define RX_REO_QUEUE_SSN_LSB 1 367 #define RX_REO_QUEUE_SSN_MSB 12 368 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 369 370 371 372 373 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 374 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 375 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 376 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 377 378 379 380 381 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 382 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 383 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 384 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 385 386 387 388 389 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 390 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 391 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 392 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 393 394 395 396 397 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 398 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 399 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 400 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 401 402 403 404 405 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 406 #define RX_REO_QUEUE_PN_VALID_LSB 31 407 #define RX_REO_QUEUE_PN_VALID_MSB 31 408 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 409 410 411 412 413 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 414 #define RX_REO_QUEUE_PN_31_0_LSB 0 415 #define RX_REO_QUEUE_PN_31_0_MSB 31 416 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 417 418 419 420 421 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 422 #define RX_REO_QUEUE_PN_63_32_LSB 0 423 #define RX_REO_QUEUE_PN_63_32_MSB 31 424 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 425 426 427 428 429 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 430 #define RX_REO_QUEUE_PN_95_64_LSB 0 431 #define RX_REO_QUEUE_PN_95_64_MSB 31 432 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 433 434 435 436 437 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 438 #define RX_REO_QUEUE_PN_127_96_LSB 0 439 #define RX_REO_QUEUE_PN_127_96_MSB 31 440 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 441 442 443 444 445 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 446 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 447 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 448 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 449 450 451 452 453 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 454 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 455 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 456 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 457 458 459 460 461 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 462 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 463 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 464 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 465 466 467 468 469 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 470 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 471 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 472 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 473 474 475 476 477 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 478 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 479 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 480 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 481 482 483 484 485 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 486 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 487 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 488 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 489 490 491 492 493 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 494 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 495 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 496 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 497 498 499 500 501 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 502 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 503 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 504 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 505 506 507 508 509 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 510 #define RX_REO_QUEUE_RESERVED_13A_LSB 14 511 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 512 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 513 514 515 516 517 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 518 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 519 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 520 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 521 522 523 524 525 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 526 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 527 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 528 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 529 530 531 532 533 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 534 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 535 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 536 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 537 538 539 540 541 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 542 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 543 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 544 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 545 546 547 548 549 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 550 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 551 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 552 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 553 554 555 556 557 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 558 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 559 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 560 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 561 562 563 564 565 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 566 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 567 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 568 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 569 570 571 572 573 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 574 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 575 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 576 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 577 578 579 580 581 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 582 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 583 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 584 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 585 586 587 588 589 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 590 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 591 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 592 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 593 594 595 596 597 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 598 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 599 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 600 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 601 602 603 604 605 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 606 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 607 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 608 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 609 610 611 612 613 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 614 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 615 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 616 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 617 618 619 620 621 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 622 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 623 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 624 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 625 626 627 628 629 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 630 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 631 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 632 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 633 634 635 636 637 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 638 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 639 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 640 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 641 642 643 644 645 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 646 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 647 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 648 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 649 650 651 652 653 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 654 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 655 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 656 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 657 658 659 660 661 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 662 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 663 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 664 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 665 666 667 668 669 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 670 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 671 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 672 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 673 674 675 676 677 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 678 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 679 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 680 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 681 682 683 684 685 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 686 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 687 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 688 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 689 690 691 692 693 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 694 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 695 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 696 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 697 698 699 700 701 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 702 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 703 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 704 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff 705 706 707 708 709 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 710 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 711 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 712 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 713 714 715 716 717 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 718 #define RX_REO_QUEUE_RESERVED_30_LSB 24 719 #define RX_REO_QUEUE_RESERVED_30_MSB 31 720 #define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 721 722 723 724 725 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 726 #define RX_REO_QUEUE_RESERVED_31_LSB 0 727 #define RX_REO_QUEUE_RESERVED_31_MSB 31 728 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 729 730 731 732 #endif 733