1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_REO_QUEUE_1K_H_ 27 #define _RX_REO_QUEUE_1K_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "uniform_descriptor_header.h" 32 #define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 33 34 35 struct rx_reo_queue_1k { 36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 37 struct uniform_descriptor_header descriptor_header; 38 uint32_t rx_bitmap_319_288 : 32; 39 uint32_t rx_bitmap_351_320 : 32; 40 uint32_t rx_bitmap_383_352 : 32; 41 uint32_t rx_bitmap_415_384 : 32; 42 uint32_t rx_bitmap_447_416 : 32; 43 uint32_t rx_bitmap_479_448 : 32; 44 uint32_t rx_bitmap_511_480 : 32; 45 uint32_t rx_bitmap_543_512 : 32; 46 uint32_t rx_bitmap_575_544 : 32; 47 uint32_t rx_bitmap_607_576 : 32; 48 uint32_t rx_bitmap_639_608 : 32; 49 uint32_t rx_bitmap_671_640 : 32; 50 uint32_t rx_bitmap_703_672 : 32; 51 uint32_t rx_bitmap_735_704 : 32; 52 uint32_t rx_bitmap_767_736 : 32; 53 uint32_t rx_bitmap_799_768 : 32; 54 uint32_t rx_bitmap_831_800 : 32; 55 uint32_t rx_bitmap_863_832 : 32; 56 uint32_t rx_bitmap_895_864 : 32; 57 uint32_t rx_bitmap_927_896 : 32; 58 uint32_t rx_bitmap_959_928 : 32; 59 uint32_t rx_bitmap_991_960 : 32; 60 uint32_t rx_bitmap_1023_992 : 32; 61 uint32_t reserved_24 : 32; 62 uint32_t reserved_25 : 32; 63 uint32_t reserved_26 : 32; 64 uint32_t reserved_27 : 32; 65 uint32_t reserved_28 : 32; 66 uint32_t reserved_29 : 32; 67 uint32_t reserved_30 : 32; 68 uint32_t reserved_31 : 32; 69 #else 70 struct uniform_descriptor_header descriptor_header; 71 uint32_t rx_bitmap_319_288 : 32; 72 uint32_t rx_bitmap_351_320 : 32; 73 uint32_t rx_bitmap_383_352 : 32; 74 uint32_t rx_bitmap_415_384 : 32; 75 uint32_t rx_bitmap_447_416 : 32; 76 uint32_t rx_bitmap_479_448 : 32; 77 uint32_t rx_bitmap_511_480 : 32; 78 uint32_t rx_bitmap_543_512 : 32; 79 uint32_t rx_bitmap_575_544 : 32; 80 uint32_t rx_bitmap_607_576 : 32; 81 uint32_t rx_bitmap_639_608 : 32; 82 uint32_t rx_bitmap_671_640 : 32; 83 uint32_t rx_bitmap_703_672 : 32; 84 uint32_t rx_bitmap_735_704 : 32; 85 uint32_t rx_bitmap_767_736 : 32; 86 uint32_t rx_bitmap_799_768 : 32; 87 uint32_t rx_bitmap_831_800 : 32; 88 uint32_t rx_bitmap_863_832 : 32; 89 uint32_t rx_bitmap_895_864 : 32; 90 uint32_t rx_bitmap_927_896 : 32; 91 uint32_t rx_bitmap_959_928 : 32; 92 uint32_t rx_bitmap_991_960 : 32; 93 uint32_t rx_bitmap_1023_992 : 32; 94 uint32_t reserved_24 : 32; 95 uint32_t reserved_25 : 32; 96 uint32_t reserved_26 : 32; 97 uint32_t reserved_27 : 32; 98 uint32_t reserved_28 : 32; 99 uint32_t reserved_29 : 32; 100 uint32_t reserved_30 : 32; 101 uint32_t reserved_31 : 32; 102 #endif 103 }; 104 105 106 107 108 109 110 111 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 112 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 113 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 114 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 115 116 117 118 119 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 120 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 121 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 122 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 123 124 125 126 127 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 128 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 129 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 130 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 131 132 133 134 135 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 136 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 137 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 138 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff 139 140 141 142 143 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 144 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 145 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 146 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff 147 148 149 150 151 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c 152 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 153 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 154 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff 155 156 157 158 159 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 160 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 161 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 162 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff 163 164 165 166 167 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 168 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 169 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 170 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff 171 172 173 174 175 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 176 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 177 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 178 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff 179 180 181 182 183 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c 184 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 185 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 186 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff 187 188 189 190 191 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 192 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 193 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 194 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff 195 196 197 198 199 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 200 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 201 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 202 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff 203 204 205 206 207 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 208 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 209 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 210 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff 211 212 213 214 215 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c 216 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 217 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 218 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff 219 220 221 222 223 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 224 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 225 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 226 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff 227 228 229 230 231 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 232 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 233 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 234 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff 235 236 237 238 239 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 240 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 241 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 242 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff 243 244 245 246 247 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c 248 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 249 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 250 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff 251 252 253 254 255 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 256 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 257 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 258 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff 259 260 261 262 263 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 264 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 265 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 266 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff 267 268 269 270 271 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 272 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 273 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 274 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff 275 276 277 278 279 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c 280 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 281 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 282 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff 283 284 285 286 287 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 288 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 289 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 290 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff 291 292 293 294 295 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 296 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 297 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 298 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff 299 300 301 302 303 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 304 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 305 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 306 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff 307 308 309 310 311 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c 312 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 313 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 314 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff 315 316 317 318 319 #define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 320 #define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 321 #define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 322 #define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff 323 324 325 326 327 #define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 328 #define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 329 #define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 330 #define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff 331 332 333 334 335 #define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 336 #define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 337 #define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 338 #define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff 339 340 341 342 343 #define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c 344 #define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 345 #define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 346 #define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff 347 348 349 350 351 #define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 352 #define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 353 #define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 354 #define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff 355 356 357 358 359 #define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 360 #define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 361 #define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 362 #define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff 363 364 365 366 367 #define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 368 #define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 369 #define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 370 #define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff 371 372 373 374 375 #define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c 376 #define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 377 #define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 378 #define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff 379 380 381 382 #endif 383