1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_REO_QUEUE_REFERENCE_H_ 27 #define _RX_REO_QUEUE_REFERENCE_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 32 33 34 struct rx_reo_queue_reference { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 37 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 38 reserved_1 : 8, 39 receive_queue_number : 16; 40 #else 41 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 42 uint32_t receive_queue_number : 16, 43 reserved_1 : 8, 44 rx_reo_queue_desc_addr_39_32 : 8; 45 #endif 46 }; 47 48 49 50 51 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 52 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 53 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 54 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 55 56 57 58 59 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 60 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 61 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 62 #define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 63 64 65 66 67 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 68 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 69 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 70 #define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 71 72 73 74 75 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 76 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 77 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 78 #define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 79 80 81 82 #endif 83