1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _RX_RESPONSE_REQUIRED_INFO_H_ 27 #define _RX_RESPONSE_REQUIRED_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "mlo_sta_id_details.h" 32 #define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 33 34 #define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 35 36 37 struct rx_response_required_info { 38 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 39 uint32_t phy_ppdu_id : 16, 40 su_or_uplink_mu_reception : 1, 41 trigger_frame_received : 1, 42 ftm_tm : 2, 43 tb_ranging_response_required : 2, 44 mac_security : 1, 45 filter_pass_monitor_ovrd : 1, 46 ast_search_incomplete : 1, 47 r2r_end_status_to_follow : 1, 48 reserved_0a : 2, 49 three_or_more_type_subtypes : 1, 50 wait_sifs_config_valid : 1, 51 wait_sifs : 2; 52 uint32_t general_frame_control : 16, 53 second_frame_control : 16; 54 uint32_t duration : 16, 55 pkt_type : 4, 56 dot11ax_su_extended : 1, 57 rate_mcs : 4, 58 sgi : 2, 59 stbc : 1, 60 ldpc : 1, 61 ampdu : 1, 62 vht_ack : 1, 63 rts_ta_grp_bit : 1; 64 uint32_t ctrl_frame_soliciting_resp : 1, 65 ast_fail_for_dot11ax_su_ext : 1, 66 service_dynamic : 1, 67 m_pkt : 1, 68 sta_partial_aid : 12, 69 group_id : 6, 70 ctrl_resp_pwr_mgmt : 1, 71 response_indication : 2, 72 ndp_indication : 1, 73 ndp_frame_type : 3, 74 second_frame_control_valid : 1, 75 reserved_3a : 2; 76 uint32_t ack_id : 16, 77 ack_id_ext : 10, 78 agc_cbw : 3, 79 service_cbw : 3; 80 uint32_t response_sta_count : 7, 81 reserved : 4, 82 ht_vht_sig_cbw : 3, 83 cts_cbw : 3, 84 response_ack_count : 7, 85 response_assoc_ack_count : 7, 86 txop_duration_all_ones : 1; 87 uint32_t response_ba32_count : 7, 88 response_ba64_count : 7, 89 response_ba128_count : 7, 90 response_ba256_count : 7, 91 multi_tid : 1, 92 sw_response_tlv_from_crypto : 1, 93 dot11ax_dl_ul_flag : 1, 94 reserved_6a : 1; 95 uint32_t sw_response_frame_length : 16, 96 response_ba512_count : 7, 97 response_ba1024_count : 7, 98 reserved_7a : 2; 99 uint32_t addr1_31_0 : 32; 100 uint32_t addr1_47_32 : 16, 101 addr2_15_0 : 16; 102 uint32_t addr2_47_16 : 32; 103 uint32_t dot11ax_received_format_indication : 1, 104 dot11ax_received_dl_ul_flag : 1, 105 dot11ax_received_bss_color_id : 6, 106 dot11ax_received_spatial_reuse : 4, 107 dot11ax_received_cp_size : 2, 108 dot11ax_received_ltf_size : 2, 109 dot11ax_received_coding : 1, 110 dot11ax_received_dcm : 1, 111 dot11ax_received_doppler_indication : 1, 112 dot11ax_received_ext_ru_size : 4, 113 ftm_fields_valid : 1, 114 ftm_pe_nss : 3, 115 ftm_pe_ltf_size : 2, 116 ftm_pe_content : 1, 117 ftm_chain_csd_en : 1, 118 ftm_pe_chain_csd_en : 1; 119 uint32_t dot11ax_response_rate_source : 8, 120 dot11ax_ext_response_rate_source : 8, 121 sw_peer_id : 16; 122 uint32_t dot11be_puncture_bitmap : 16, 123 dot11be_response : 1, 124 punctured_response : 1, 125 eht_duplicate_mode : 2, 126 force_extra_symbol : 1, 127 reserved_13a : 5, 128 u_sig_puncture_pattern_encoding : 6; 129 struct mlo_sta_id_details mlo_sta_id_details_rx; 130 uint16_t he_a_control_response_time : 12, 131 reserved_after_struct16 : 4; 132 uint32_t tlv64_padding : 32; 133 #else 134 uint32_t wait_sifs : 2, 135 wait_sifs_config_valid : 1, 136 three_or_more_type_subtypes : 1, 137 reserved_0a : 2, 138 r2r_end_status_to_follow : 1, 139 ast_search_incomplete : 1, 140 filter_pass_monitor_ovrd : 1, 141 mac_security : 1, 142 tb_ranging_response_required : 2, 143 ftm_tm : 2, 144 trigger_frame_received : 1, 145 su_or_uplink_mu_reception : 1, 146 phy_ppdu_id : 16; 147 uint32_t second_frame_control : 16, 148 general_frame_control : 16; 149 uint32_t rts_ta_grp_bit : 1, 150 vht_ack : 1, 151 ampdu : 1, 152 ldpc : 1, 153 stbc : 1, 154 sgi : 2, 155 rate_mcs : 4, 156 dot11ax_su_extended : 1, 157 pkt_type : 4, 158 duration : 16; 159 uint32_t reserved_3a : 2, 160 second_frame_control_valid : 1, 161 ndp_frame_type : 3, 162 ndp_indication : 1, 163 response_indication : 2, 164 ctrl_resp_pwr_mgmt : 1, 165 group_id : 6, 166 sta_partial_aid : 12, 167 m_pkt : 1, 168 service_dynamic : 1, 169 ast_fail_for_dot11ax_su_ext : 1, 170 ctrl_frame_soliciting_resp : 1; 171 uint32_t service_cbw : 3, 172 agc_cbw : 3, 173 ack_id_ext : 10, 174 ack_id : 16; 175 uint32_t txop_duration_all_ones : 1, 176 response_assoc_ack_count : 7, 177 response_ack_count : 7, 178 cts_cbw : 3, 179 ht_vht_sig_cbw : 3, 180 reserved : 4, 181 response_sta_count : 7; 182 uint32_t reserved_6a : 1, 183 dot11ax_dl_ul_flag : 1, 184 sw_response_tlv_from_crypto : 1, 185 multi_tid : 1, 186 response_ba256_count : 7, 187 response_ba128_count : 7, 188 response_ba64_count : 7, 189 response_ba32_count : 7; 190 uint32_t reserved_7a : 2, 191 response_ba1024_count : 7, 192 response_ba512_count : 7, 193 sw_response_frame_length : 16; 194 uint32_t addr1_31_0 : 32; 195 uint32_t addr2_15_0 : 16, 196 addr1_47_32 : 16; 197 uint32_t addr2_47_16 : 32; 198 uint32_t ftm_pe_chain_csd_en : 1, 199 ftm_chain_csd_en : 1, 200 ftm_pe_content : 1, 201 ftm_pe_ltf_size : 2, 202 ftm_pe_nss : 3, 203 ftm_fields_valid : 1, 204 dot11ax_received_ext_ru_size : 4, 205 dot11ax_received_doppler_indication : 1, 206 dot11ax_received_dcm : 1, 207 dot11ax_received_coding : 1, 208 dot11ax_received_ltf_size : 2, 209 dot11ax_received_cp_size : 2, 210 dot11ax_received_spatial_reuse : 4, 211 dot11ax_received_bss_color_id : 6, 212 dot11ax_received_dl_ul_flag : 1, 213 dot11ax_received_format_indication : 1; 214 uint32_t sw_peer_id : 16, 215 dot11ax_ext_response_rate_source : 8, 216 dot11ax_response_rate_source : 8; 217 uint32_t u_sig_puncture_pattern_encoding : 6, 218 reserved_13a : 5, 219 force_extra_symbol : 1, 220 eht_duplicate_mode : 2, 221 punctured_response : 1, 222 dot11be_response : 1, 223 dot11be_puncture_bitmap : 16; 224 uint32_t reserved_after_struct16 : 4, 225 he_a_control_response_time : 12; 226 struct mlo_sta_id_details mlo_sta_id_details_rx; 227 uint32_t tlv64_padding : 32; 228 #endif 229 }; 230 231 232 233 234 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 235 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 236 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 237 #define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff 238 239 240 241 242 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 243 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 244 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 245 #define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 246 247 248 249 250 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 251 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 252 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 253 #define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 254 255 256 257 258 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_OFFSET 0x0000000000000000 259 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_LSB 18 260 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MSB 19 261 #define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MASK 0x00000000000c0000 262 263 264 265 266 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 267 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 268 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 269 #define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 270 271 272 273 274 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 275 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 276 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 277 #define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 278 279 280 281 282 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 283 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 284 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 285 #define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 286 287 288 289 290 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 291 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 292 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 293 #define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 294 295 296 297 298 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 299 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 300 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 301 #define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 302 303 304 305 306 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 307 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 308 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 309 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 310 311 312 313 314 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 315 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 316 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 317 #define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 318 319 320 321 322 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 323 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 324 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 325 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 326 327 328 329 330 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 331 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 332 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 333 #define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 334 335 336 337 338 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 339 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 340 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 341 #define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 342 343 344 345 346 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 347 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 348 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 349 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 350 351 352 353 354 #define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 355 #define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 356 #define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 357 #define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff 358 359 360 361 362 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 363 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 364 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 365 #define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 366 367 368 369 370 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 371 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 372 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 373 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 374 375 376 377 378 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 379 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 380 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 381 #define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 382 383 384 385 386 #define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 387 #define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 388 #define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 389 #define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 390 391 392 393 394 #define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 395 #define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 396 #define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 397 #define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 398 399 400 401 402 #define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 403 #define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 404 #define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 405 #define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 406 407 408 409 410 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 411 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 412 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 413 #define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 414 415 416 417 418 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 419 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 420 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 421 #define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 422 423 424 425 426 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 427 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 428 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 429 #define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 430 431 432 433 434 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 435 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 436 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 437 #define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 438 439 440 441 442 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 443 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 444 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 445 #define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 446 447 448 449 450 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 451 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 452 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 453 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 454 455 456 457 458 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 459 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 460 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 461 #define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 462 463 464 465 466 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 467 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 468 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 469 #define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 470 471 472 473 474 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 475 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 476 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 477 #define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 478 479 480 481 482 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 483 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 484 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 485 #define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 486 487 488 489 490 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 491 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 492 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 493 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 494 495 496 497 498 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 499 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 500 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 501 #define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 502 503 504 505 506 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 507 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 508 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 509 #define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 510 511 512 513 514 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 515 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 516 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 517 #define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 518 519 520 521 522 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 523 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 524 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 525 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 526 527 528 529 530 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 531 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 532 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 533 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff 534 535 536 537 538 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 539 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 540 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 541 #define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 542 543 544 545 546 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 547 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 548 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 549 #define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 550 551 552 553 554 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 555 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 556 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 557 #define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 558 559 560 561 562 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 563 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 564 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 565 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 566 567 568 569 570 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 571 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 572 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 573 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 574 575 576 577 578 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 579 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 580 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 581 #define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 582 583 584 585 586 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 587 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 588 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 589 #define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 590 591 592 593 594 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 595 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 596 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 597 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 598 599 600 601 602 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 603 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 604 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 605 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 606 607 608 609 610 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 611 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 612 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 613 #define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 614 615 616 617 618 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 619 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 620 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 621 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f 622 623 624 625 626 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 627 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 628 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 629 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 630 631 632 633 634 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 635 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 636 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 637 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 638 639 640 641 642 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 643 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 644 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 645 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 646 647 648 649 650 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 651 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 652 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 653 #define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 654 655 656 657 658 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 659 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 660 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 661 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 662 663 664 665 666 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 667 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 668 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 669 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 670 671 672 673 674 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 675 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 676 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 677 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 678 679 680 681 682 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 683 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 684 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 685 #define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 686 687 688 689 690 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 691 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 692 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 693 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 694 695 696 697 698 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 699 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 700 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 701 #define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 702 703 704 705 706 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 707 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 708 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 709 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 710 711 712 713 714 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 715 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 716 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 717 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff 718 719 720 721 722 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 723 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 724 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 725 #define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 726 727 728 729 730 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 731 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 732 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 733 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 734 735 736 737 738 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 739 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 740 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 741 #define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff 742 743 744 745 746 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 747 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 748 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 749 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 750 751 752 753 754 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 755 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 756 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 757 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 758 759 760 761 762 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 763 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 764 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 765 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 766 767 768 769 770 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 771 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 772 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 773 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 774 775 776 777 778 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 779 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 780 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 781 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 782 783 784 785 786 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 787 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 788 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 789 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 790 791 792 793 794 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 795 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 796 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 797 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 798 799 800 801 802 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 803 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 804 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 805 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 806 807 808 809 810 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 811 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 812 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 813 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 814 815 816 817 818 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 819 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 820 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 821 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 822 823 824 825 826 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 827 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 828 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 829 #define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 830 831 832 833 834 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 835 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 836 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 837 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 838 839 840 841 842 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 843 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 844 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 845 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 846 847 848 849 850 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 851 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 852 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 853 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 854 855 856 857 858 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 859 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 860 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 861 #define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 862 863 864 865 866 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 867 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 868 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 869 #define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 870 871 872 873 874 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 875 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 876 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 877 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff 878 879 880 881 882 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 883 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 884 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 885 #define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 886 887 888 889 890 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 891 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 892 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 893 #define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 894 895 896 897 898 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 899 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 900 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 901 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 902 903 904 905 906 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 907 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 908 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 909 #define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 910 911 912 913 914 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 915 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 916 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 917 #define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 918 919 920 921 922 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 923 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 924 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 925 #define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 926 927 928 929 930 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 931 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 932 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 933 #define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 934 935 936 937 938 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 939 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 940 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 941 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 942 943 944 945 946 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 947 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 948 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 949 #define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 950 951 952 953 954 955 956 957 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 958 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 959 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 960 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff 961 962 963 964 965 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 966 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 967 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 968 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 969 970 971 972 973 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 974 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 975 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 976 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 977 978 979 980 981 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 982 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 983 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 984 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 985 986 987 988 989 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 990 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 991 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 992 #define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 993 994 995 996 997 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 998 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 999 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 1000 #define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 1001 1002 1003 1004 1005 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 1006 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 1007 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 1008 #define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 1009 1010 1011 1012 1013 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 1014 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 1015 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 1016 #define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 1017 1018 1019 1020 #endif 1021