xref: /wlan-driver/fw-api/hw/qcn9224/v2/rxpcu_early_rx_indication.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
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25 
26 #ifndef _RXPCU_EARLY_RX_INDICATION_H_
27 #define _RXPCU_EARLY_RX_INDICATION_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2
32 
33 #define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1
34 
35 
36 struct rxpcu_early_rx_indication {
37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
38              uint32_t pkt_type                                                :  4,
39                       dot11ax_su_extended                                     :  1,
40                       rate_mcs                                                :  4,
41                       dot11ax_received_ext_ru_size                            :  4,
42                       reserved_0a                                             : 19;
43              uint32_t tlv64_padding                                           : 32;
44 #else
45              uint32_t reserved_0a                                             : 19,
46                       dot11ax_received_ext_ru_size                            :  4,
47                       rate_mcs                                                :  4,
48                       dot11ax_su_extended                                     :  1,
49                       pkt_type                                                :  4;
50              uint32_t tlv64_padding                                           : 32;
51 #endif
52 };
53 
54 
55 
56 
57 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET                                   0x0000000000000000
58 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB                                      0
59 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB                                      3
60 #define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK                                     0x000000000000000f
61 
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63 
64 
65 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET                        0x0000000000000000
66 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB                           4
67 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB                           4
68 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK                          0x0000000000000010
69 
70 
71 
72 
73 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET                                   0x0000000000000000
74 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB                                      5
75 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB                                      8
76 #define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK                                     0x00000000000001e0
77 
78 
79 
80 
81 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000000000000000
82 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  9
83 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  12
84 #define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x0000000000001e00
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89 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET                                0x0000000000000000
90 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB                                   13
91 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB                                   31
92 #define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK                                  0x00000000ffffe000
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96 
97 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET                              0x0000000000000000
98 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB                                 32
99 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB                                 63
100 #define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK                                0xffffffff00000000
101 
102 
103 
104 #endif
105