1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _U_SIG_EHT_SU_MU_INFO_H_ 27 #define _U_SIG_EHT_SU_MU_INFO_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 32 33 34 struct u_sig_eht_su_mu_info { 35 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 36 uint32_t phy_version : 3, 37 transmit_bw : 3, 38 dl_ul_flag : 1, 39 bss_color_id : 6, 40 txop_duration : 7, 41 disregard_0a : 5, 42 validate_0b : 1, 43 reserved_0c : 6; 44 uint32_t eht_ppdu_sig_cmn_type : 2, 45 validate_1a : 1, 46 punctured_channel_information : 5, 47 validate_1b : 1, 48 mcs_of_eht_sig : 2, 49 num_eht_sig_symbols : 5, 50 crc : 4, 51 tail : 6, 52 dot11ax_su_extended : 1, 53 reserved_1d : 3, 54 rx_ndp : 1, 55 rx_integrity_check_passed : 1; 56 #else 57 uint32_t reserved_0c : 6, 58 validate_0b : 1, 59 disregard_0a : 5, 60 txop_duration : 7, 61 bss_color_id : 6, 62 dl_ul_flag : 1, 63 transmit_bw : 3, 64 phy_version : 3; 65 uint32_t rx_integrity_check_passed : 1, 66 rx_ndp : 1, 67 reserved_1d : 3, 68 dot11ax_su_extended : 1, 69 tail : 6, 70 crc : 4, 71 num_eht_sig_symbols : 5, 72 mcs_of_eht_sig : 2, 73 validate_1b : 1, 74 punctured_channel_information : 5, 75 validate_1a : 1, 76 eht_ppdu_sig_cmn_type : 2; 77 #endif 78 }; 79 80 81 82 83 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 84 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 85 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 86 #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 87 88 89 90 91 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 92 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 93 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 94 #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 95 96 97 98 99 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 100 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 101 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 102 #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 103 104 105 106 107 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 108 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 109 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 110 #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 111 112 113 114 115 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 116 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 117 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 118 #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 119 120 121 122 123 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 124 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 125 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 126 #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 127 128 129 130 131 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 132 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 133 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 134 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 135 136 137 138 139 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 140 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 141 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 142 #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 143 144 145 146 147 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 148 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 149 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 150 #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 151 152 153 154 155 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 156 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 157 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 158 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 159 160 161 162 163 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 164 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 165 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 166 #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 167 168 169 170 171 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 172 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 173 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 174 #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 175 176 177 178 179 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 180 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 181 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 182 #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 183 184 185 186 187 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 188 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 189 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 190 #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 191 192 193 194 195 #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 196 #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 197 #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 198 #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 199 200 201 202 203 #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 204 #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 205 #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 206 #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 207 208 209 210 211 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 212 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 213 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 214 #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 215 216 217 218 219 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 220 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 221 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 222 #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 223 224 225 226 227 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 228 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 229 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 230 #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 231 232 233 234 235 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 236 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 237 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 238 #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 239 240 241 242 #endif 243