xref: /wlan-driver/fw-api/hw/qcn9224/v2/wbm2sw_completion_ring_tx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 #ifndef _WBM2SW_COMPLETION_RING_TX_H_
27 #define _WBM2SW_COMPLETION_RING_TX_H_
28 #if !defined(__ASSEMBLER__)
29 #endif
30 
31 #include "tx_rate_stats_info.h"
32 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8
33 
34 
35 struct wbm2sw_completion_ring_tx {
36 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
37              uint32_t buffer_virt_addr_31_0                                   : 32;
38              uint32_t buffer_virt_addr_63_32                                  : 32;
39              uint32_t release_source_module                                   :  3,
40                       cache_id                                                :  1,
41                       reserved_2a                                             :  2,
42                       buffer_or_desc_type                                     :  3,
43                       return_buffer_manager                                   :  4,
44                       tqm_release_reason                                      :  4,
45                       rbm_override_valid                                      :  1,
46                       sw_buffer_cookie_11_0                                   : 12,
47                       cookie_conversion_status                                :  1,
48                       wbm_internal_error                                      :  1;
49              uint32_t tqm_status_number                                       : 24,
50                       transmit_count                                          :  7,
51                       sw_release_details_valid                                :  1;
52              uint32_t ack_frame_rssi                                          :  8,
53                       first_msdu                                              :  1,
54                       last_msdu                                               :  1,
55                       fw_tx_notify_frame                                      :  3,
56                       buffer_timestamp                                        : 19;
57              struct   tx_rate_stats_info                                        tx_rate_stats;
58              uint32_t sw_peer_id                                              : 16,
59                       tid                                                     :  4,
60                       sw_buffer_cookie_19_12                                  :  8,
61                       looping_count                                           :  4;
62 #else
63              uint32_t buffer_virt_addr_31_0                                   : 32;
64              uint32_t buffer_virt_addr_63_32                                  : 32;
65              uint32_t wbm_internal_error                                      :  1,
66                       cookie_conversion_status                                :  1,
67                       sw_buffer_cookie_11_0                                   : 12,
68                       rbm_override_valid                                      :  1,
69                       tqm_release_reason                                      :  4,
70                       return_buffer_manager                                   :  4,
71                       buffer_or_desc_type                                     :  3,
72                       reserved_2a                                             :  2,
73                       cache_id                                                :  1,
74                       release_source_module                                   :  3;
75              uint32_t sw_release_details_valid                                :  1,
76                       transmit_count                                          :  7,
77                       tqm_status_number                                       : 24;
78              uint32_t buffer_timestamp                                        : 19,
79                       fw_tx_notify_frame                                      :  3,
80                       last_msdu                                               :  1,
81                       first_msdu                                              :  1,
82                       ack_frame_rssi                                          :  8;
83              struct   tx_rate_stats_info                                        tx_rate_stats;
84              uint32_t looping_count                                           :  4,
85                       sw_buffer_cookie_19_12                                  :  8,
86                       tid                                                     :  4,
87                       sw_peer_id                                              : 16;
88 #endif
89 };
90 
91 
92 
93 
94 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
95 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB                         0
96 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB                         31
97 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
98 
99 
100 
101 
102 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
103 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB                        0
104 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB                        31
105 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
106 
107 
108 
109 
110 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
111 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB                         0
112 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB                         2
113 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
114 
115 
116 
117 
118 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET                                   0x00000008
119 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB                                      3
120 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB                                      3
121 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK                                     0x00000008
122 
123 
124 
125 
126 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET                                0x00000008
127 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB                                   4
128 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB                                   5
129 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK                                  0x00000030
130 
131 
132 
133 
134 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
135 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB                           6
136 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB                           8
137 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
138 
139 
140 
141 
142 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
143 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB                         9
144 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB                         12
145 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
146 
147 
148 
149 
150 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET                         0x00000008
151 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB                            13
152 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB                            16
153 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK                           0x0001e000
154 
155 
156 
157 
158 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET                         0x00000008
159 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB                            17
160 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB                            17
161 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK                           0x00020000
162 
163 
164 
165 
166 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET                      0x00000008
167 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB                         18
168 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB                         29
169 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK                        0x3ffc0000
170 
171 
172 
173 
174 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
175 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB                      30
176 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB                      30
177 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK                     0x40000000
178 
179 
180 
181 
182 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
183 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB                            31
184 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB                            31
185 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK                           0x80000000
186 
187 
188 
189 
190 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET                          0x0000000c
191 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB                             0
192 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB                             23
193 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK                            0x00ffffff
194 
195 
196 
197 
198 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET                             0x0000000c
199 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB                                24
200 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB                                30
201 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK                               0x7f000000
202 
203 
204 
205 
206 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                   0x0000000c
207 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                      31
208 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                      31
209 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                     0x80000000
210 
211 
212 
213 
214 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET                             0x00000010
215 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB                                0
216 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB                                7
217 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK                               0x000000ff
218 
219 
220 
221 
222 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET                                 0x00000010
223 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB                                    8
224 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB                                    8
225 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK                                   0x00000100
226 
227 
228 
229 
230 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET                                  0x00000010
231 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB                                     9
232 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB                                     9
233 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK                                    0x00000200
234 
235 
236 
237 
238 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                         0x00000010
239 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB                            10
240 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB                            12
241 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK                           0x00001c00
242 
243 
244 
245 
246 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET                           0x00000010
247 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB                              13
248 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB                              31
249 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK                             0xffffe000
250 
251 
252 
253 
254 
255 
256 
257 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET     0x00000014
258 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB        0
259 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB        0
260 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK       0x00000001
261 
262 
263 
264 
265 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                  0x00000014
266 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                     1
267 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                     3
268 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                    0x0000000e
269 
270 
271 
272 
273 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET            0x00000014
274 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB               4
275 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB               7
276 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK              0x000000f0
277 
278 
279 
280 
281 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                0x00000014
282 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                   8
283 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                   8
284 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                  0x00000100
285 
286 
287 
288 
289 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                0x00000014
290 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                   9
291 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                   9
292 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                  0x00000200
293 
294 
295 
296 
297 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                 0x00000014
298 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                    10
299 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                    11
300 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                   0x00000c00
301 
302 
303 
304 
305 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                 0x00000014
306 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                    12
307 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                    15
308 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                   0x0000f000
309 
310 
311 
312 
313 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET           0x00000014
314 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB              16
315 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB              16
316 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK             0x00010000
317 
318 
319 
320 
321 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                  0x00000014
322 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                     17
323 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                     28
324 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                    0x1ffe0000
325 
326 
327 
328 
329 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET                  0x00000014
330 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB                     29
331 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB                     31
332 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK                    0xe0000000
333 
334 
335 
336 
337 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET        0x00000018
338 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB           0
339 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB           31
340 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK          0xffffffff
341 
342 
343 
344 
345 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET                                 0x0000001c
346 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB                                    0
347 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB                                    15
348 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK                                   0x0000ffff
349 
350 
351 
352 
353 #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET                                        0x0000001c
354 #define WBM2SW_COMPLETION_RING_TX_TID_LSB                                           16
355 #define WBM2SW_COMPLETION_RING_TX_TID_MSB                                           19
356 #define WBM2SW_COMPLETION_RING_TX_TID_MASK                                          0x000f0000
357 
358 
359 
360 
361 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET                     0x0000001c
362 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB                        20
363 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB                        27
364 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK                       0x0ff00000
365 
366 
367 
368 
369 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET                              0x0000001c
370 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB                                 28
371 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB                                 31
372 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK                                0xf0000000
373 
374 
375 
376 #endif
377