1 2 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 19 20 21 22 23 24 25 26 #ifndef _WBM_RELEASE_RING_TX_H_ 27 #define _WBM_RELEASE_RING_TX_H_ 28 #if !defined(__ASSEMBLER__) 29 #endif 30 31 #include "tx_rate_stats_info.h" 32 #include "buffer_addr_info.h" 33 #define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 34 35 36 struct wbm_release_ring_tx { 37 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 38 struct buffer_addr_info released_buff_or_desc_addr_info; 39 uint32_t release_source_module : 3, 40 bm_action : 3, 41 buffer_or_desc_type : 3, 42 first_msdu_index : 4, 43 tqm_release_reason : 4, 44 rbm_override_valid : 1, 45 rbm_override : 4, 46 reserved_2a : 7, 47 cache_id : 1, 48 cookie_conversion_status : 1, 49 wbm_internal_error : 1; 50 uint32_t tqm_status_number : 24, 51 transmit_count : 7, 52 sw_release_details_valid : 1; 53 uint32_t ack_frame_rssi : 8, 54 first_msdu : 1, 55 last_msdu : 1, 56 fw_tx_notify_frame : 3, 57 buffer_timestamp : 19; 58 struct tx_rate_stats_info tx_rate_stats; 59 uint32_t sw_peer_id : 16, 60 tid : 4, 61 tqm_status_number_31_24 : 8, 62 looping_count : 4; 63 #else 64 struct buffer_addr_info released_buff_or_desc_addr_info; 65 uint32_t wbm_internal_error : 1, 66 cookie_conversion_status : 1, 67 cache_id : 1, 68 reserved_2a : 7, 69 rbm_override : 4, 70 rbm_override_valid : 1, 71 tqm_release_reason : 4, 72 first_msdu_index : 4, 73 buffer_or_desc_type : 3, 74 bm_action : 3, 75 release_source_module : 3; 76 uint32_t sw_release_details_valid : 1, 77 transmit_count : 7, 78 tqm_status_number : 24; 79 uint32_t buffer_timestamp : 19, 80 fw_tx_notify_frame : 3, 81 last_msdu : 1, 82 first_msdu : 1, 83 ack_frame_rssi : 8; 84 struct tx_rate_stats_info tx_rate_stats; 85 uint32_t looping_count : 4, 86 tqm_status_number_31_24 : 8, 87 tid : 4, 88 sw_peer_id : 16; 89 #endif 90 }; 91 92 93 94 95 96 97 98 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 99 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 100 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 101 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 102 103 104 105 106 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 107 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 108 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 109 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 110 111 112 113 114 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 115 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 116 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 117 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 118 119 120 121 122 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 123 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 124 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 125 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 126 127 128 129 130 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 131 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 132 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 133 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 134 135 136 137 138 #define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 139 #define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 140 #define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 141 #define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 142 143 144 145 146 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 147 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 148 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 149 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 150 151 152 153 154 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 155 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 156 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 157 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 158 159 160 161 162 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 163 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 164 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 165 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 166 167 168 169 170 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 171 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 172 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 173 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 174 175 176 177 178 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 179 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 180 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 181 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 182 183 184 185 186 #define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 187 #define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 188 #define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 189 #define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 190 191 192 193 194 #define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 195 #define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 196 #define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 197 #define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 198 199 200 201 202 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 203 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 204 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 205 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 206 207 208 209 210 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 211 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 212 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 213 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 214 215 216 217 218 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 219 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 220 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 221 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 222 223 224 225 226 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 227 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 228 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 229 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 230 231 232 233 234 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 235 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 236 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 237 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 238 239 240 241 242 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 243 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 244 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 245 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 246 247 248 249 250 #define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 251 #define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 252 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 253 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 254 255 256 257 258 #define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 259 #define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 260 #define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 261 #define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 262 263 264 265 266 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 267 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 268 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 269 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 270 271 272 273 274 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 275 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 276 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 277 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 278 279 280 281 282 283 284 285 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 286 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 287 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 288 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 289 290 291 292 293 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 294 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 295 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 296 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 297 298 299 300 301 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 302 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 303 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 304 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 305 306 307 308 309 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 310 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 311 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 312 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 313 314 315 316 317 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 318 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 319 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 320 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 321 322 323 324 325 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 326 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 327 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 328 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 329 330 331 332 333 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 334 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 335 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 336 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 337 338 339 340 341 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 342 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 343 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 344 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 345 346 347 348 349 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 350 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 351 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 352 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 353 354 355 356 357 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 358 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_LSB 29 359 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MSB 31 360 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_RESERVED_0A_MASK 0xe0000000 361 362 363 364 365 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 366 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 367 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 368 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 369 370 371 372 373 #define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 374 #define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 375 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 376 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff 377 378 379 380 381 #define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c 382 #define WBM_RELEASE_RING_TX_TID_LSB 16 383 #define WBM_RELEASE_RING_TX_TID_MSB 19 384 #define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 385 386 387 388 389 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c 390 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 391 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 392 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 393 394 395 396 397 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 398 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 399 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 400 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 401 402 403 404 #endif 405