1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 23 #define _REO_FLUSH_CACHE_STATUS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_status_header.h" 28 29 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25 30 31 struct reo_flush_cache_status { 32 struct uniform_reo_status_header status_header; 33 uint32_t error_detected : 1, 34 block_error_details : 2, 35 reserved_2a : 5, 36 cache_controller_flush_status_hit: 1, 37 cache_controller_flush_status_desc_type: 3, 38 cache_controller_flush_status_client_id: 4, 39 cache_controller_flush_status_error: 2, 40 cache_controller_flush_count : 8, 41 reserved_2b : 6; 42 uint32_t reserved_3a : 32; 43 uint32_t reserved_4a : 32; 44 uint32_t reserved_5a : 32; 45 uint32_t reserved_6a : 32; 46 uint32_t reserved_7a : 32; 47 uint32_t reserved_8a : 32; 48 uint32_t reserved_9a : 32; 49 uint32_t reserved_10a : 32; 50 uint32_t reserved_11a : 32; 51 uint32_t reserved_12a : 32; 52 uint32_t reserved_13a : 32; 53 uint32_t reserved_14a : 32; 54 uint32_t reserved_15a : 32; 55 uint32_t reserved_16a : 32; 56 uint32_t reserved_17a : 32; 57 uint32_t reserved_18a : 32; 58 uint32_t reserved_19a : 32; 59 uint32_t reserved_20a : 32; 60 uint32_t reserved_21a : 32; 61 uint32_t reserved_22a : 32; 62 uint32_t reserved_23a : 32; 63 uint32_t reserved_24a : 28, 64 looping_count : 4; 65 }; 66 67 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 68 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 69 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff 70 71 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 72 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 73 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 74 75 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 76 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 77 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 78 79 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 80 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 81 #define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 82 83 #define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 84 #define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 85 #define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff 86 87 #define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 88 #define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 89 #define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 90 91 #define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008 92 #define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1 93 #define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006 94 95 #define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 96 #define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3 97 #define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8 98 99 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008 100 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 101 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 102 103 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008 104 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 105 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 106 107 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008 108 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 109 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 110 111 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008 112 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 113 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 114 115 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008 116 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 117 #define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 118 119 #define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008 120 #define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26 121 #define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000 122 123 #define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c 124 #define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0 125 #define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff 126 127 #define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 128 #define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0 129 #define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff 130 131 #define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 132 #define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0 133 #define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff 134 135 #define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 136 #define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0 137 #define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff 138 139 #define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c 140 #define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0 141 #define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff 142 143 #define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 144 #define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0 145 #define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff 146 147 #define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 148 #define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0 149 #define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff 150 151 #define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 152 #define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0 153 #define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff 154 155 #define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c 156 #define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0 157 #define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff 158 159 #define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 160 #define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0 161 #define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff 162 163 #define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 164 #define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0 165 #define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff 166 167 #define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 168 #define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0 169 #define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff 170 171 #define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c 172 #define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0 173 #define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff 174 175 #define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 176 #define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0 177 #define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff 178 179 #define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 180 #define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0 181 #define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff 182 183 #define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 184 #define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0 185 #define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff 186 187 #define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c 188 #define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0 189 #define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff 190 191 #define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 192 #define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0 193 #define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff 194 195 #define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 196 #define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0 197 #define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff 198 199 #define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 200 #define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0 201 #define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff 202 203 #define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c 204 #define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0 205 #define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff 206 207 #define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 208 #define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0 209 #define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff 210 211 #define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 212 #define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 213 #define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 214 215 #endif 216