1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_FLUSH_QUEUE_H_ 23 #define _REO_FLUSH_QUEUE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_cmd_header.h" 28 29 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 30 31 struct reo_flush_queue { 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t flush_desc_addr_31_0 : 32; 34 uint32_t flush_desc_addr_39_32 : 8, 35 block_desc_addr_usage_after_flush: 1, 36 block_resource_index : 2, 37 invalidate_queue_and_flush : 1, 38 reserved_2a : 20; 39 uint32_t reserved_3a : 32; 40 uint32_t reserved_4a : 32; 41 uint32_t reserved_5a : 32; 42 uint32_t reserved_6a : 32; 43 uint32_t reserved_7a : 32; 44 uint32_t reserved_8a : 32; 45 }; 46 47 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 48 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 49 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 50 51 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 52 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 53 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 54 55 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 56 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 57 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 58 59 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 60 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 61 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff 62 63 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 64 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 65 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff 66 67 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 68 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 69 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 70 71 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 72 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 73 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 74 75 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008 76 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 77 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800 78 79 #define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 80 #define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12 81 #define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000 82 83 #define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 84 #define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 85 #define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff 86 87 #define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 88 #define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 89 #define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff 90 91 #define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 92 #define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 93 #define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff 94 95 #define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 96 #define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 97 #define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff 98 99 #define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c 100 #define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 101 #define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff 102 103 #define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 104 #define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 105 #define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff 106 107 #endif 108