1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _REO_GET_QUEUE_STATS_H_ 23 #define _REO_GET_QUEUE_STATS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_reo_cmd_header.h" 28 29 #define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 30 31 struct reo_get_queue_stats { 32 struct uniform_reo_cmd_header cmd_header; 33 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 34 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 35 clear_stats : 1, 36 reserved_2a : 23; 37 uint32_t reserved_3a : 32; 38 uint32_t reserved_4a : 32; 39 uint32_t reserved_5a : 32; 40 uint32_t reserved_6a : 32; 41 uint32_t reserved_7a : 32; 42 uint32_t reserved_8a : 32; 43 }; 44 45 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 46 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 47 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 48 49 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 50 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 51 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 52 53 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 54 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17 55 #define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 56 57 #define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 58 #define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 59 #define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 60 61 #define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 62 #define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 63 #define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 64 65 #define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 66 #define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 67 #define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 68 69 #define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 70 #define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 71 #define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 72 73 #define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c 74 #define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 75 #define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff 76 77 #define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 78 #define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 79 #define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff 80 81 #define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 82 #define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 83 #define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff 84 85 #define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 86 #define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 87 #define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff 88 89 #define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c 90 #define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 91 #define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff 92 93 #define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 94 #define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 95 #define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff 96 97 #endif 98