1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_ATTENTION_H_ 23 #define _RX_ATTENTION_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_ATTENTION 3 28 29 struct rx_attention { 30 uint32_t rxpcu_mpdu_filter_in_category : 2, 31 sw_frame_group_id : 7, 32 reserved_0 : 7, 33 phy_ppdu_id : 16; 34 uint32_t first_mpdu : 1, 35 reserved_1a : 1, 36 mcast_bcast : 1, 37 ast_index_not_found : 1, 38 ast_index_timeout : 1, 39 power_mgmt : 1, 40 non_qos : 1, 41 null_data : 1, 42 mgmt_type : 1, 43 ctrl_type : 1, 44 more_data : 1, 45 eosp : 1, 46 a_msdu_error : 1, 47 fragment_flag : 1, 48 order : 1, 49 cce_match : 1, 50 overflow_err : 1, 51 msdu_length_err : 1, 52 tcp_udp_chksum_fail : 1, 53 ip_chksum_fail : 1, 54 sa_idx_invalid : 1, 55 da_idx_invalid : 1, 56 reserved_1b : 1, 57 rx_in_tx_decrypt_byp : 1, 58 encrypt_required : 1, 59 directed : 1, 60 buffer_fragment : 1, 61 mpdu_length_err : 1, 62 tkip_mic_err : 1, 63 decrypt_err : 1, 64 unencrypted_frame_err : 1, 65 fcs_err : 1; 66 uint32_t flow_idx_timeout : 1, 67 flow_idx_invalid : 1, 68 wifi_parser_error : 1, 69 amsdu_parser_error : 1, 70 sa_idx_timeout : 1, 71 da_idx_timeout : 1, 72 msdu_limit_error : 1, 73 da_is_valid : 1, 74 da_is_mcbc : 1, 75 sa_is_valid : 1, 76 decrypt_status_code : 3, 77 rx_bitmap_not_updated : 1, 78 reserved_2 : 17, 79 msdu_done : 1; 80 }; 81 82 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 83 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 84 #define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 85 86 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 87 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 88 #define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 89 90 #define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 91 #define RX_ATTENTION_0_RESERVED_0_LSB 9 92 #define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 93 94 #define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 95 #define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 96 #define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 97 98 #define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 99 #define RX_ATTENTION_1_FIRST_MPDU_LSB 0 100 #define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 101 102 #define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 103 #define RX_ATTENTION_1_RESERVED_1A_LSB 1 104 #define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 105 106 #define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 107 #define RX_ATTENTION_1_MCAST_BCAST_LSB 2 108 #define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 109 110 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 111 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 112 #define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 113 114 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 115 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 116 #define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 117 118 #define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 119 #define RX_ATTENTION_1_POWER_MGMT_LSB 5 120 #define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 121 122 #define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 123 #define RX_ATTENTION_1_NON_QOS_LSB 6 124 #define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 125 126 #define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 127 #define RX_ATTENTION_1_NULL_DATA_LSB 7 128 #define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 129 130 #define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 131 #define RX_ATTENTION_1_MGMT_TYPE_LSB 8 132 #define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 133 134 #define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 135 #define RX_ATTENTION_1_CTRL_TYPE_LSB 9 136 #define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 137 138 #define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 139 #define RX_ATTENTION_1_MORE_DATA_LSB 10 140 #define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 141 142 #define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 143 #define RX_ATTENTION_1_EOSP_LSB 11 144 #define RX_ATTENTION_1_EOSP_MASK 0x00000800 145 146 #define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 147 #define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 148 #define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 149 150 #define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 151 #define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 152 #define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 153 154 #define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 155 #define RX_ATTENTION_1_ORDER_LSB 14 156 #define RX_ATTENTION_1_ORDER_MASK 0x00004000 157 158 #define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 159 #define RX_ATTENTION_1_CCE_MATCH_LSB 15 160 #define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 161 162 #define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 163 #define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 164 #define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 165 166 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 167 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 168 #define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 169 170 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 171 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 172 #define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 173 174 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 175 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 176 #define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 177 178 #define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 179 #define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 180 #define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 181 182 #define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 183 #define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 184 #define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 185 186 #define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 187 #define RX_ATTENTION_1_RESERVED_1B_LSB 22 188 #define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 189 190 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 191 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 192 #define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 193 194 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 195 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 196 #define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 197 198 #define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 199 #define RX_ATTENTION_1_DIRECTED_LSB 25 200 #define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 201 202 #define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 203 #define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 204 #define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 205 206 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 207 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 208 #define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 209 210 #define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 211 #define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 212 #define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 213 214 #define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 215 #define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 216 #define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 217 218 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 219 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 220 #define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 221 222 #define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 223 #define RX_ATTENTION_1_FCS_ERR_LSB 31 224 #define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 225 226 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 227 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 228 #define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 229 230 #define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 231 #define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 232 #define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 233 234 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 235 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 236 #define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 237 238 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 239 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 240 #define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 241 242 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 243 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 244 #define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 245 246 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 247 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 248 #define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 249 250 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 251 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 252 #define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 253 254 #define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 255 #define RX_ATTENTION_2_DA_IS_VALID_LSB 7 256 #define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 257 258 #define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 259 #define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 260 #define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 261 262 #define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 263 #define RX_ATTENTION_2_SA_IS_VALID_LSB 9 264 #define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 265 266 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 267 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 268 #define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 269 270 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 271 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 272 #define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 273 274 #define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 275 #define RX_ATTENTION_2_RESERVED_2_LSB 14 276 #define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 277 278 #define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 279 #define RX_ATTENTION_2_MSDU_DONE_LSB 31 280 #define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 281 282 #endif 283