xref: /wlan-driver/fw-api/hw/wcn6450/v1/rx_mpdu_start.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 
2 /*
3  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 
21 
22 #ifndef _RX_MPDU_START_H_
23 #define _RX_MPDU_START_H_
24 #if !defined(__ASSEMBLER__)
25 #endif
26 
27 #include "rx_mpdu_info.h"
28 
29 #define NUM_OF_DWORDS_RX_MPDU_START 23
30 
31 struct rx_mpdu_start {
32     struct            rx_mpdu_info                       rx_mpdu_info_details;
33 };
34 
35 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
36 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
37 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
38 
39 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
40 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
41 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
42 
43 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
44 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
45 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
46 
47 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
48 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
49 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
50 
51 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
52 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
53 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
54 
55 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
56 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
57 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
58 
59 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
60 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
61 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
62 
63 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
64 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
65 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
66 
67 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
68 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15
69 #define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000
70 
71 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
72 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
73 #define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
74 
75 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
76 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
77 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
78 
79 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
80 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8
81 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
82 
83 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008
84 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24
85 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000
86 
87 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET  0x00000008
88 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB     25
89 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK    0x02000000
90 
91 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET      0x00000008
92 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB         26
93 #define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK        0xfc000000
94 
95 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET          0x0000000c
96 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB             0
97 #define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK            0xffffffff
98 
99 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET         0x00000010
100 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB            0
101 #define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK           0xffffffff
102 
103 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET         0x00000014
104 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB            0
105 #define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK           0xffffffff
106 
107 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET        0x00000018
108 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB           0
109 #define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK          0xffffffff
110 
111 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET           0x0000001c
112 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB              0
113 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK             0x00000001
114 
115 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c
116 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
117 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
118 
119 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET     0x0000001c
120 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB        2
121 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK       0x0000003c
122 
123 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c
124 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
125 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
126 
127 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET        0x0000001c
128 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB           10
129 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK          0x00000400
130 
131 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET     0x0000001c
132 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB        11
133 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK       0x00007800
134 
135 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET              0x0000001c
136 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB                 15
137 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK                0x00078000
138 
139 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET      0x0000001c
140 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB         19
141 #define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK        0xfff80000
142 
143 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET   0x00000020
144 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB      0
145 #define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK     0xffffffff
146 
147 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024
148 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
149 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
150 
151 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024
152 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB   2
153 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK  0x000001fc
154 
155 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET        0x00000024
156 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB           9
157 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK          0x00000200
158 
159 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET          0x00000024
160 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB             10
161 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK            0x00000400
162 
163 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024
164 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11
165 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
166 
167 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024
168 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12
169 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000
170 
171 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024
172 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13
173 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000
174 
175 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET      0x00000024
176 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB         14
177 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK        0x0000c000
178 
179 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET      0x00000024
180 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB         16
181 #define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK        0xffff0000
182 
183 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET       0x00000028
184 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB          0
185 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK         0x0000ffff
186 
187 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET      0x00000028
188 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB         16
189 #define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK        0xffff0000
190 
191 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c
192 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0
193 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
194 
195 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c
196 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1
197 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002
198 
199 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c
200 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2
201 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004
202 
203 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c
204 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3
205 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008
206 
207 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c
208 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4
209 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010
210 
211 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c
212 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5
213 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020
214 
215 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c
216 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
217 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
218 
219 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c
220 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7
221 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
222 
223 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c
224 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8
225 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100
226 
227 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c
228 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9
229 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
230 
231 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c
232 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10
233 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
234 
235 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c
236 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
237 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
238 
239 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET    0x0000002c
240 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB       15
241 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK      0x00008000
242 
243 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET           0x0000002c
244 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB              16
245 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK             0x00010000
246 
247 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET           0x0000002c
248 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB              17
249 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK             0x00020000
250 
251 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET       0x0000002c
252 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB          18
253 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK         0x00040000
254 
255 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET      0x0000002c
256 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB         19
257 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK        0x00080000
258 
259 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c
260 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20
261 #define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
262 
263 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET    0x00000030
264 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB       0
265 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK      0x000000ff
266 
267 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET  0x00000030
268 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB     8
269 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK    0x00000100
270 
271 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET  0x00000030
272 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB     9
273 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK    0x00000200
274 
275 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET      0x00000030
276 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB         10
277 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK        0x00000c00
278 
279 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
280 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
281 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
282 
283 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
284 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
285 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
286 
287 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
288 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14
289 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
290 
291 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
292 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15
293 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
294 
295 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030
296 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB    16
297 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK   0x0fff0000
298 
299 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET      0x00000030
300 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB         28
301 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK        0x10000000
302 
303 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET       0x00000030
304 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB          29
305 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK         0x20000000
306 
307 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET        0x00000030
308 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB           30
309 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK          0x40000000
310 
311 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET     0x00000030
312 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB        31
313 #define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK       0x80000000
314 
315 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET     0x00000034
316 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB        0
317 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK       0x00003fff
318 
319 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET      0x00000034
320 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB         14
321 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK        0x00004000
322 
323 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET     0x00000034
324 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB        15
325 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK       0x00008000
326 
327 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
328 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16
329 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000
330 
331 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034
332 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB  17
333 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000
334 
335 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET      0x00000034
336 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB         18
337 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK        0x00040000
338 
339 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET         0x00000034
340 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB            19
341 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK           0x00080000
342 
343 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET       0x00000034
344 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB          20
345 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK         0x00100000
346 
347 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET       0x00000034
348 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB          21
349 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK         0x00200000
350 
351 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET       0x00000034
352 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB          22
353 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK         0x00400000
354 
355 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET       0x00000034
356 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB          23
357 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK         0x00800000
358 
359 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET            0x00000034
360 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB               24
361 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK              0x01000000
362 
363 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET   0x00000034
364 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB      25
365 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK     0x02000000
366 
367 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET           0x00000034
368 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB              26
369 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK             0x04000000
370 
371 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET  0x00000034
372 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB     27
373 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK    0x08000000
374 
375 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034
376 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB   28
377 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK  0x10000000
378 
379 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET        0x00000034
380 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB           29
381 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK          0x20000000
382 
383 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET   0x00000034
384 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB      30
385 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK     0x40000000
386 
387 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET     0x00000034
388 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB        31
389 #define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK       0x80000000
390 
391 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
392 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0
393 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
394 
395 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038
396 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16
397 #define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000
398 
399 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
400 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB  0
401 #define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff
402 
403 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
404 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0
405 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
406 
407 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
408 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB  16
409 #define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000
410 
411 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
412 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0
413 #define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff
414 
415 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
416 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB  0
417 #define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff
418 
419 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
420 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0
421 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
422 
423 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
424 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
425 #define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
426 
427 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
428 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB  0
429 #define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff
430 
431 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
432 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0
433 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
434 
435 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
436 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16
437 #define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
438 
439 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
440 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0
441 #define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
442 
443 #endif
444