1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MSDU_DESC_INFO_H_ 23 #define _RX_MSDU_DESC_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 28 29 struct rx_msdu_desc_info { 30 uint32_t first_msdu_in_mpdu_flag : 1, 31 last_msdu_in_mpdu_flag : 1, 32 msdu_continuation : 1, 33 msdu_length : 14, 34 reo_destination_indication : 5, 35 msdu_drop : 1, 36 sa_is_valid : 1, 37 sa_idx_timeout : 1, 38 da_is_valid : 1, 39 da_is_mcbc : 1, 40 da_idx_timeout : 1, 41 l3_header_padding_msb : 1, 42 tcp_udp_chksum_fail : 1, 43 ip_chksum_fail : 1, 44 raw_mpdu : 1; 45 uint32_t sa_idx_or_sw_peer_id_14_0 : 15, 46 mpdu_ast_idx_or_sw_peer_id_14_0 : 15, 47 fr_ds : 1, 48 to_ds : 1; 49 }; 50 51 #define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 52 #define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 53 #define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 54 55 #define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 56 #define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 57 #define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 58 59 #define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 60 #define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 61 #define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 62 63 #define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 64 #define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 65 #define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 66 67 #define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 68 #define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 69 #define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 70 71 #define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 72 #define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 73 #define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 74 75 #define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 76 #define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 77 #define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 78 79 #define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 80 #define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 81 #define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 82 83 #define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 84 #define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 85 #define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 86 87 #define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 88 #define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 89 #define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 90 91 #define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 92 #define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 93 #define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 94 95 #define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 96 #define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28 97 #define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000 98 99 #define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 100 #define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29 101 #define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 102 103 #define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000 104 #define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30 105 #define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000 106 107 #define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 108 #define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31 109 #define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000 110 111 #define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 112 #define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 113 #define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 114 115 #define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 116 #define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 117 #define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 118 119 #define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004 120 #define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30 121 #define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000 122 123 #define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004 124 #define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31 125 #define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000 126 127 #endif 128