1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_MSDU_END_H_ 23 #define _RX_MSDU_END_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_RX_MSDU_END 17 28 29 struct rx_msdu_end { 30 uint32_t rxpcu_mpdu_filter_in_category : 2, 31 sw_frame_group_id : 7, 32 reserved_0 : 7, 33 phy_ppdu_id : 16; 34 uint32_t ip_hdr_chksum : 16, 35 reported_mpdu_length : 14, 36 reserved_1a : 2; 37 uint32_t key_id_octet : 8, 38 cce_super_rule : 6, 39 cce_classify_not_done_truncate : 1, 40 cce_classify_not_done_cce_dis : 1, 41 cumulative_l3_checksum : 16; 42 uint32_t rule_indication_31_0 : 32; 43 uint32_t rule_indication_63_32 : 32; 44 uint32_t da_offset : 6, 45 sa_offset : 6, 46 da_offset_valid : 1, 47 sa_offset_valid : 1, 48 reserved_5a : 2, 49 l3_type : 16; 50 uint32_t ipv6_options_crc : 32; 51 uint32_t tcp_seq_number : 32; 52 uint32_t tcp_ack_number : 32; 53 uint32_t tcp_flag : 9, 54 lro_eligible : 1, 55 reserved_9a : 6, 56 window_size : 16; 57 uint32_t tcp_udp_chksum : 16, 58 sa_idx_timeout : 1, 59 da_idx_timeout : 1, 60 msdu_limit_error : 1, 61 flow_idx_timeout : 1, 62 flow_idx_invalid : 1, 63 wifi_parser_error : 1, 64 amsdu_parser_error : 1, 65 sa_is_valid : 1, 66 da_is_valid : 1, 67 da_is_mcbc : 1, 68 l3_header_padding : 2, 69 first_msdu : 1, 70 last_msdu : 1, 71 tcp_udp_chksum_fail : 1, 72 ip_chksum_fail : 1; 73 uint32_t sa_idx : 16, 74 da_idx_or_sw_peer_id : 16; 75 uint32_t msdu_drop : 1, 76 reo_destination_indication : 5, 77 flow_idx : 20, 78 reserved_12a : 6; 79 uint32_t fse_metadata : 32; 80 uint32_t cce_metadata : 16, 81 sa_sw_peer_id : 16; 82 uint32_t aggregation_count : 8, 83 flow_aggregation_continuation : 1, 84 fisa_timeout : 1, 85 reserved_15a : 22; 86 uint32_t cumulative_l4_checksum : 16, 87 cumulative_ip_length : 16; 88 }; 89 90 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 91 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 92 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 93 94 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 95 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 96 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 97 98 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 99 #define RX_MSDU_END_0_RESERVED_0_LSB 9 100 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 101 102 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 103 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 104 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 105 106 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 107 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 108 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 109 110 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 111 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 112 #define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 113 114 #define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 115 #define RX_MSDU_END_1_RESERVED_1A_LSB 30 116 #define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 117 118 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 119 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 120 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 121 122 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 123 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 124 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 125 126 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 127 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 128 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 129 130 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 131 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 132 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 133 134 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 135 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 136 #define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 137 138 #define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c 139 #define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 140 #define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff 141 142 #define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 143 #define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 144 #define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff 145 146 #define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 147 #define RX_MSDU_END_5_DA_OFFSET_LSB 0 148 #define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f 149 150 #define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 151 #define RX_MSDU_END_5_SA_OFFSET_LSB 6 152 #define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 153 154 #define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 155 #define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 156 #define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 157 158 #define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 159 #define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 160 #define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 161 162 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 163 #define RX_MSDU_END_5_RESERVED_5A_LSB 14 164 #define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 165 166 #define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 167 #define RX_MSDU_END_5_L3_TYPE_LSB 16 168 #define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 169 170 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 171 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 172 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 173 174 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 175 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 176 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 177 178 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 179 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 180 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 181 182 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 183 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 184 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 185 186 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 187 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 188 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 189 190 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 191 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 192 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 193 194 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 195 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 196 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 197 198 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 199 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 200 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff 201 202 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 203 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 204 #define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 205 206 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 207 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 208 #define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 209 210 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 211 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 212 #define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 213 214 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 215 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 216 #define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 217 218 #define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 219 #define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 220 #define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 221 222 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 223 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 224 #define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 225 226 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 227 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 228 #define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 229 230 #define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 231 #define RX_MSDU_END_10_SA_IS_VALID_LSB 23 232 #define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 233 234 #define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 235 #define RX_MSDU_END_10_DA_IS_VALID_LSB 24 236 #define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 237 238 #define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 239 #define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 240 #define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 241 242 #define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 243 #define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 244 #define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 245 246 #define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 247 #define RX_MSDU_END_10_FIRST_MSDU_LSB 28 248 #define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 249 250 #define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 251 #define RX_MSDU_END_10_LAST_MSDU_LSB 29 252 #define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 253 254 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 255 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 256 #define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 257 258 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 259 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 260 #define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 261 262 #define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c 263 #define RX_MSDU_END_11_SA_IDX_LSB 0 264 #define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff 265 266 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c 267 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 268 #define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 269 270 #define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 271 #define RX_MSDU_END_12_MSDU_DROP_LSB 0 272 #define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 273 274 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 275 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 276 #define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e 277 278 #define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 279 #define RX_MSDU_END_12_FLOW_IDX_LSB 6 280 #define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 281 282 #define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 283 #define RX_MSDU_END_12_RESERVED_12A_LSB 26 284 #define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 285 286 #define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 287 #define RX_MSDU_END_13_FSE_METADATA_LSB 0 288 #define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff 289 290 #define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 291 #define RX_MSDU_END_14_CCE_METADATA_LSB 0 292 #define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff 293 294 #define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 295 #define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 296 #define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 297 298 #define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c 299 #define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 300 #define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff 301 302 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c 303 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 304 #define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 305 306 #define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c 307 #define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 308 #define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 309 310 #define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c 311 #define RX_MSDU_END_15_RESERVED_15A_LSB 10 312 #define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 313 314 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 315 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 316 #define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff 317 318 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 319 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 320 #define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 321 322 #endif 323