1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_PPDU_END_USER_STATS_H_ 23 #define _RX_PPDU_END_USER_STATS_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rx_rxpcu_classification_overview.h" 28 29 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23 30 31 struct rx_ppdu_end_user_stats { 32 struct rx_rxpcu_classification_overview rxpcu_classification_details; 33 uint32_t sta_full_aid : 13, 34 mcs : 4, 35 nss : 3, 36 ofdma_info_valid : 1, 37 dl_ofdma_ru_start_index : 7, 38 reserved_1a : 4; 39 uint32_t dl_ofdma_ru_width : 7, 40 reserved_2a : 1, 41 user_receive_quality : 8, 42 mpdu_cnt_fcs_err : 10, 43 wbm2rxdma_buf_source_used : 1, 44 fw2rxdma_buf_source_used : 1, 45 sw2rxdma_buf_source_used : 1, 46 reserved_2b : 3; 47 uint32_t mpdu_cnt_fcs_ok : 9, 48 frame_control_info_valid : 1, 49 qos_control_info_valid : 1, 50 ht_control_info_valid : 1, 51 data_sequence_control_info_valid: 1, 52 ht_control_info_null_valid : 1, 53 reserved_3a : 2, 54 rxdma2reo_ring_used : 1, 55 rxdma2fw_ring_used : 1, 56 rxdma2sw_ring_used : 1, 57 rxdma_release_ring_used : 1, 58 ht_control_field_pkt_type : 4, 59 reserved_3b : 8; 60 uint32_t ast_index : 16, 61 frame_control_field : 16; 62 uint32_t first_data_seq_ctrl : 16, 63 qos_control_field : 16; 64 uint32_t ht_control_field : 32; 65 uint32_t fcs_ok_bitmap_31_0 : 32; 66 uint32_t fcs_ok_bitmap_63_32 : 32; 67 uint32_t udp_msdu_count : 16, 68 tcp_msdu_count : 16; 69 uint32_t other_msdu_count : 16, 70 tcp_ack_msdu_count : 16; 71 uint32_t sw_response_reference_ptr : 32; 72 uint32_t received_qos_data_tid_bitmap : 16, 73 received_qos_data_tid_eosp_bitmap: 16; 74 uint32_t qosctrl_15_8_tid0 : 8, 75 qosctrl_15_8_tid1 : 8, 76 qosctrl_15_8_tid2 : 8, 77 qosctrl_15_8_tid3 : 8; 78 uint32_t qosctrl_15_8_tid4 : 8, 79 qosctrl_15_8_tid5 : 8, 80 qosctrl_15_8_tid6 : 8, 81 qosctrl_15_8_tid7 : 8; 82 uint32_t qosctrl_15_8_tid8 : 8, 83 qosctrl_15_8_tid9 : 8, 84 qosctrl_15_8_tid10 : 8, 85 qosctrl_15_8_tid11 : 8; 86 uint32_t qosctrl_15_8_tid12 : 8, 87 qosctrl_15_8_tid13 : 8, 88 qosctrl_15_8_tid14 : 8, 89 qosctrl_15_8_tid15 : 8; 90 uint32_t mpdu_ok_byte_count : 25, 91 ampdu_delim_ok_count_6_0 : 7; 92 uint32_t ampdu_delim_err_count : 25, 93 ampdu_delim_ok_count_13_7 : 7; 94 uint32_t mpdu_err_byte_count : 25, 95 ampdu_delim_ok_count_20_14 : 7; 96 uint32_t non_consecutive_delimiter_err : 16, 97 reserved_20a : 16; 98 uint32_t ht_control_null_field : 32; 99 uint32_t sw_response_reference_ptr_ext : 32; 100 }; 101 102 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 103 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 104 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 105 106 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 107 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 108 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 109 110 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 111 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 112 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 113 114 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 115 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 116 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 117 118 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 119 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 120 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 121 122 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 123 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 124 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 125 126 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 127 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 128 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 129 130 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 131 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 132 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 133 134 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 135 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 136 #define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 137 138 #define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004 139 #define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0 140 #define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff 141 142 #define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004 143 #define RX_PPDU_END_USER_STATS_1_MCS_LSB 13 144 #define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000 145 146 #define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004 147 #define RX_PPDU_END_USER_STATS_1_NSS_LSB 17 148 #define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000 149 150 #define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004 151 #define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20 152 #define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000 153 154 #define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004 155 #define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21 156 #define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000 157 158 #define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004 159 #define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28 160 #define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000 161 162 #define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008 163 #define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0 164 #define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f 165 166 #define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008 167 #define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7 168 #define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080 169 170 #define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008 171 #define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8 172 #define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00 173 174 #define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 175 #define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16 176 #define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000 177 178 #define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 179 #define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26 180 #define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000 181 182 #define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 183 #define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27 184 #define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000 185 186 #define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 187 #define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28 188 #define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000 189 190 #define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008 191 #define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29 192 #define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000 193 194 #define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c 195 #define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0 196 #define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff 197 198 #define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c 199 #define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9 200 #define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200 201 202 #define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c 203 #define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10 204 #define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400 205 206 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c 207 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11 208 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800 209 210 #define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c 211 #define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12 212 #define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000 213 214 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c 215 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13 216 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000 217 218 #define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c 219 #define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14 220 #define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000 221 222 #define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c 223 #define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16 224 #define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000 225 226 #define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c 227 #define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17 228 #define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000 229 230 #define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c 231 #define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18 232 #define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000 233 234 #define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c 235 #define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19 236 #define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000 237 238 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c 239 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20 240 #define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000 241 242 #define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c 243 #define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24 244 #define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000 245 246 #define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010 247 #define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0 248 #define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff 249 250 #define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010 251 #define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16 252 #define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000 253 254 #define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 255 #define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0 256 #define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff 257 258 #define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014 259 #define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16 260 #define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000 261 262 #define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018 263 #define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0 264 #define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff 265 266 #define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c 267 #define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0 268 #define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff 269 270 #define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 271 #define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0 272 #define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff 273 274 #define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024 275 #define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0 276 #define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff 277 278 #define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024 279 #define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16 280 #define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000 281 282 #define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028 283 #define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0 284 #define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff 285 286 #define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 287 #define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16 288 #define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 289 290 #define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c 291 #define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0 292 #define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff 293 294 #define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 295 #define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 296 #define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff 297 298 #define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 299 #define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 300 #define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 301 302 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034 303 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0 304 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff 305 306 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034 307 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8 308 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00 309 310 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034 311 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16 312 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000 313 314 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034 315 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24 316 #define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000 317 318 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038 319 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0 320 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff 321 322 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038 323 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8 324 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00 325 326 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038 327 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16 328 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000 329 330 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038 331 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24 332 #define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000 333 334 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c 335 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0 336 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff 337 338 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c 339 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8 340 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00 341 342 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c 343 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16 344 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000 345 346 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c 347 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24 348 #define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000 349 350 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040 351 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0 352 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff 353 354 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040 355 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8 356 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00 357 358 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040 359 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16 360 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000 361 362 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040 363 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24 364 #define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000 365 366 #define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 367 #define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0 368 #define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff 369 370 #define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 371 #define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 372 #define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 373 374 #define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 375 #define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0 376 #define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff 377 378 #define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 379 #define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 380 #define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 381 382 #define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c 383 #define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0 384 #define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff 385 386 #define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c 387 #define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 388 #define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 389 390 #define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 391 #define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 392 #define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff 393 394 #define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050 395 #define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16 396 #define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000 397 398 #define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 399 #define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0 400 #define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff 401 402 #define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 403 #define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 404 #define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff 405 406 #endif 407