1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RX_REO_QUEUE_H_ 23 #define _RX_REO_QUEUE_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "uniform_descriptor_header.h" 28 29 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 30 31 struct rx_reo_queue { 32 struct uniform_descriptor_header descriptor_header; 33 uint32_t receive_queue_number : 16, 34 reserved_1b : 16; 35 uint32_t vld : 1, 36 associated_link_descriptor_counter: 2, 37 disable_duplicate_detection : 1, 38 soft_reorder_enable : 1, 39 ac : 2, 40 bar : 1, 41 rty : 1, 42 chk_2k_mode : 1, 43 oor_mode : 1, 44 ba_window_size : 8, 45 pn_check_needed : 1, 46 pn_shall_be_even : 1, 47 pn_shall_be_uneven : 1, 48 pn_handling_enable : 1, 49 pn_size : 2, 50 ignore_ampdu_flag : 1, 51 reserved_2b : 6; 52 uint32_t svld : 1, 53 ssn : 12, 54 current_index : 8, 55 seq_2k_error_detected_flag : 1, 56 pn_error_detected_flag : 1, 57 reserved_3a : 8, 58 pn_valid : 1; 59 uint32_t pn_31_0 : 32; 60 uint32_t pn_63_32 : 32; 61 uint32_t pn_95_64 : 32; 62 uint32_t pn_127_96 : 32; 63 uint32_t last_rx_enqueue_timestamp : 32; 64 uint32_t last_rx_dequeue_timestamp : 32; 65 uint32_t ptr_to_next_aging_queue_31_0 : 32; 66 uint32_t ptr_to_next_aging_queue_39_32 : 8, 67 reserved_11a : 24; 68 uint32_t ptr_to_previous_aging_queue_31_0: 32; 69 uint32_t ptr_to_previous_aging_queue_39_32: 8, 70 reserved_13a : 24; 71 uint32_t rx_bitmap_31_0 : 32; 72 uint32_t rx_bitmap_63_32 : 32; 73 uint32_t rx_bitmap_95_64 : 32; 74 uint32_t rx_bitmap_127_96 : 32; 75 uint32_t rx_bitmap_159_128 : 32; 76 uint32_t rx_bitmap_191_160 : 32; 77 uint32_t rx_bitmap_223_192 : 32; 78 uint32_t rx_bitmap_255_224 : 32; 79 uint32_t current_mpdu_count : 7, 80 current_msdu_count : 25; 81 uint32_t reserved_23 : 4, 82 timeout_count : 6, 83 forward_due_to_bar_count : 6, 84 duplicate_count : 16; 85 uint32_t frames_in_order_count : 24, 86 bar_received_count : 8; 87 uint32_t mpdu_frames_processed_count : 32; 88 uint32_t msdu_frames_processed_count : 32; 89 uint32_t total_processed_byte_count : 32; 90 uint32_t late_receive_mpdu_count : 12, 91 window_jump_2k : 4, 92 hole_count : 16; 93 uint32_t reserved_29 : 32; 94 uint32_t reserved_30 : 32; 95 uint32_t reserved_31 : 32; 96 }; 97 98 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 99 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 100 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 101 102 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 103 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 104 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 105 106 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 107 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 108 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 109 110 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 111 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 112 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 113 114 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 115 #define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 116 #define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 117 118 #define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 119 #define RX_REO_QUEUE_2_VLD_LSB 0 120 #define RX_REO_QUEUE_2_VLD_MASK 0x00000001 121 122 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 123 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 124 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 125 126 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 127 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 128 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 129 130 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 131 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 132 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 133 134 #define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 135 #define RX_REO_QUEUE_2_AC_LSB 5 136 #define RX_REO_QUEUE_2_AC_MASK 0x00000060 137 138 #define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 139 #define RX_REO_QUEUE_2_BAR_LSB 7 140 #define RX_REO_QUEUE_2_BAR_MASK 0x00000080 141 142 #define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 143 #define RX_REO_QUEUE_2_RTY_LSB 8 144 #define RX_REO_QUEUE_2_RTY_MASK 0x00000100 145 146 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 147 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 148 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 149 150 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 151 #define RX_REO_QUEUE_2_OOR_MODE_LSB 10 152 #define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 153 154 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 155 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 156 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 157 158 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 159 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 160 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 161 162 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 163 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 164 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 165 166 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 167 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 168 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 169 170 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 171 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 172 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 173 174 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 175 #define RX_REO_QUEUE_2_PN_SIZE_LSB 23 176 #define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 177 178 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 179 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 180 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 181 182 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 183 #define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 184 #define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 185 186 #define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c 187 #define RX_REO_QUEUE_3_SVLD_LSB 0 188 #define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 189 190 #define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c 191 #define RX_REO_QUEUE_3_SSN_LSB 1 192 #define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe 193 194 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c 195 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 196 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 197 198 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 199 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 200 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 201 202 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 203 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 204 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 205 206 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 207 #define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 208 #define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 209 210 #define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c 211 #define RX_REO_QUEUE_3_PN_VALID_LSB 31 212 #define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 213 214 #define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 215 #define RX_REO_QUEUE_4_PN_31_0_LSB 0 216 #define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff 217 218 #define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 219 #define RX_REO_QUEUE_5_PN_63_32_LSB 0 220 #define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff 221 222 #define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 223 #define RX_REO_QUEUE_6_PN_95_64_LSB 0 224 #define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff 225 226 #define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c 227 #define RX_REO_QUEUE_7_PN_127_96_LSB 0 228 #define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff 229 230 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 231 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 232 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 233 234 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 235 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 236 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 237 238 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 239 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 240 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 241 242 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 243 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 244 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 245 246 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c 247 #define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 248 #define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 249 250 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 251 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 252 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 253 254 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 255 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 256 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 257 258 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 259 #define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 260 #define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 261 262 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 263 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 264 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff 265 266 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c 267 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 268 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff 269 270 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 271 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 272 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff 273 274 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 275 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 276 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff 277 278 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 279 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 280 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff 281 282 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c 283 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 284 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff 285 286 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 287 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 288 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff 289 290 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 291 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 292 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff 293 294 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 295 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 296 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f 297 298 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 299 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 300 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 301 302 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c 303 #define RX_REO_QUEUE_23_RESERVED_23_LSB 0 304 #define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f 305 306 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c 307 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 308 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 309 310 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c 311 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 312 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 313 314 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c 315 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 316 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 317 318 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 319 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 320 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 321 322 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 323 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 324 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 325 326 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 327 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 328 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 329 330 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 331 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 332 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 333 334 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c 335 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 336 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 337 338 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 339 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 340 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 341 342 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 343 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 344 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 345 346 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 347 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 348 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 349 350 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 351 #define RX_REO_QUEUE_29_RESERVED_29_LSB 0 352 #define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff 353 354 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 355 #define RX_REO_QUEUE_30_RESERVED_30_LSB 0 356 #define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff 357 358 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c 359 #define RX_REO_QUEUE_31_RESERVED_31_LSB 0 360 #define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff 361 362 #endif 363