1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _RXPCU_PPDU_END_INFO_H_ 23 #define _RXPCU_PPDU_END_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "phyrx_abort_request_info.h" 28 #include "macrx_abort_request_info.h" 29 30 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 31 32 struct rxpcu_ppdu_end_info { 33 uint32_t wb_timestamp_lower_32 : 32; 34 uint32_t wb_timestamp_upper_32 : 32; 35 uint32_t rx_antenna : 24, 36 tx_ht_vht_ack : 1, 37 unsupported_mu_nc : 1, 38 otp_txbf_disable : 1, 39 previous_tlv_corrupted : 1, 40 phyrx_abort_request_info_valid : 1, 41 macrx_abort_request_info_valid : 1, 42 reserved : 2; 43 uint32_t coex_bt_tx_from_start_of_rx : 1, 44 coex_bt_tx_after_start_of_rx : 1, 45 coex_wan_tx_from_start_of_rx : 1, 46 coex_wan_tx_after_start_of_rx : 1, 47 coex_wlan_tx_from_start_of_rx : 1, 48 coex_wlan_tx_after_start_of_rx : 1, 49 mpdu_delimiter_errors_seen : 1, 50 __reserved_g_0012 : 2, 51 dialog_token : 8, 52 follow_up_dialog_token : 8, 53 bb_captured_channel : 1, 54 bb_captured_reason : 3, 55 bb_captured_timeout : 1, 56 reserved_3 : 2; 57 uint32_t before_mpdu_count_passing_fcs : 10, 58 before_mpdu_count_failing_fcs : 10, 59 after_mpdu_count_passing_fcs : 10, 60 reserved_4 : 2; 61 uint32_t after_mpdu_count_failing_fcs : 10, 62 reserved_5 : 22; 63 uint32_t phy_timestamp_tx_lower_32 : 32; 64 uint32_t phy_timestamp_tx_upper_32 : 32; 65 uint32_t bb_length : 16, 66 bb_data : 1, 67 reserved_8 : 3, 68 first_bt_broadcast_status_details: 12; 69 uint32_t rx_ppdu_duration : 24, 70 reserved_9 : 8; 71 uint32_t ast_index : 16, 72 ast_index_valid : 1, 73 reserved_10 : 3, 74 second_bt_broadcast_status_details: 12; 75 struct phyrx_abort_request_info phyrx_abort_request_info_details; 76 struct macrx_abort_request_info macrx_abort_request_info_details; 77 uint16_t pre_bt_broadcast_status_details : 12, 78 reserved_12a : 4; 79 uint32_t rx_ppdu_end_marker : 32; 80 }; 81 82 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 83 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 84 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff 85 86 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 87 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 88 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff 89 90 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 91 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 92 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff 93 94 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 95 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 96 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 97 98 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 99 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 100 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 101 102 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 103 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 104 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 105 106 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 107 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 108 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 109 110 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 111 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 112 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 113 114 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 115 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 116 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 117 118 #define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 119 #define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 120 #define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 121 122 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c 123 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 124 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 125 126 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 127 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 128 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 129 130 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 131 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 132 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 133 134 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 135 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 136 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 137 138 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 139 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 140 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 141 142 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 143 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 144 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 145 146 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c 147 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 148 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 149 150 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c 151 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 152 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 153 154 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c 155 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 156 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 157 158 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c 159 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 160 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 161 162 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c 163 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 164 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 165 166 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c 167 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 168 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 169 170 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c 171 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 172 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 173 174 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 175 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 176 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff 177 178 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 179 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 180 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 181 182 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 183 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 184 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 185 186 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 187 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 188 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 189 190 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 191 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 192 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff 193 194 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 195 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 196 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 197 198 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 199 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 200 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff 201 202 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c 203 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 204 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff 205 206 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 207 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 208 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff 209 210 #define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 211 #define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 212 #define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 213 214 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 215 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 216 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 217 218 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 219 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 220 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 221 222 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 223 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 224 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff 225 226 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 227 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 228 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 229 230 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 231 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 232 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff 233 234 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 235 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 236 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 237 238 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 239 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 240 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 241 242 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 243 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 244 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 245 246 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c 247 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 248 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff 249 250 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c 251 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 252 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 253 254 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c 255 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 256 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 257 258 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c 259 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 260 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 261 262 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c 263 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 264 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 265 266 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 267 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 268 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff 269 270 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 271 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 272 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 273 274 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 275 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 276 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff 277 278 #endif 279