1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _TCL_DATA_CMD_H_ 23 #define _TCL_DATA_CMD_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "buffer_addr_info.h" 28 29 #define NUM_OF_DWORDS_TCL_DATA_CMD 7 30 31 struct tcl_data_cmd { 32 struct buffer_addr_info buf_addr_info; 33 uint32_t buf_or_ext_desc_type : 1, 34 epd : 1, 35 encap_type : 2, 36 encrypt_type : 4, 37 src_buffer_swap : 1, 38 link_meta_swap : 1, 39 tqm_no_drop : 1, 40 reserved_2a : 1, 41 search_type : 2, 42 addrx_en : 1, 43 addry_en : 1, 44 tcl_cmd_number : 16; 45 uint32_t data_length : 16, 46 ipv4_checksum_en : 1, 47 udp_over_ipv4_checksum_en : 1, 48 udp_over_ipv6_checksum_en : 1, 49 tcp_over_ipv4_checksum_en : 1, 50 tcp_over_ipv6_checksum_en : 1, 51 to_fw : 1, 52 reserved_3a : 1, 53 packet_offset : 9; 54 uint32_t buffer_timestamp : 19, 55 buffer_timestamp_valid : 1, 56 reserved_4a : 1, 57 hlos_tid_overwrite : 1, 58 hlos_tid : 4, 59 lmac_id : 2, 60 udp_flow_override : 2, 61 reserved_4b : 2; 62 uint32_t dscp_tid_table_num : 6, 63 search_index : 20, 64 cache_set_num : 4, 65 mesh_enable : 2; 66 uint32_t reserved_6a : 20, 67 ring_id : 8, 68 looping_count : 4; 69 }; 70 71 #define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 72 #define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 73 #define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 74 75 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 76 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 77 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 78 79 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 80 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 81 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 82 83 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 84 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 85 #define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 86 87 #define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 88 #define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 89 #define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 90 91 #define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 92 #define TCL_DATA_CMD_2_EPD_LSB 1 93 #define TCL_DATA_CMD_2_EPD_MASK 0x00000002 94 95 #define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 96 #define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 97 #define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c 98 99 #define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 100 #define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 101 #define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 102 103 #define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 104 #define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 105 #define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 106 107 #define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 108 #define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 109 #define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 110 111 #define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008 112 #define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10 113 #define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400 114 115 #define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008 116 #define TCL_DATA_CMD_2_RESERVED_2A_LSB 11 117 #define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800 118 119 #define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008 120 #define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12 121 #define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000 122 123 #define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 124 #define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 125 #define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 126 127 #define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 128 #define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 129 #define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 130 131 #define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 132 #define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 133 #define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 134 135 #define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c 136 #define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 137 #define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff 138 139 #define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c 140 #define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 141 #define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 142 143 #define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c 144 #define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 145 #define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 146 147 #define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c 148 #define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 149 #define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 150 151 #define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c 152 #define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 153 #define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 154 155 #define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c 156 #define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 157 #define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 158 159 #define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c 160 #define TCL_DATA_CMD_3_TO_FW_LSB 21 161 #define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 162 163 #define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c 164 #define TCL_DATA_CMD_3_RESERVED_3A_LSB 22 165 #define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000 166 167 #define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c 168 #define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 169 #define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 170 171 #define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 172 #define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 173 #define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff 174 175 #define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 176 #define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 177 #define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 178 179 #define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010 180 #define TCL_DATA_CMD_4_RESERVED_4A_LSB 20 181 #define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000 182 183 #define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 184 #define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 185 #define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 186 187 #define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 188 #define TCL_DATA_CMD_4_HLOS_TID_LSB 22 189 #define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 190 191 #define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010 192 #define TCL_DATA_CMD_4_LMAC_ID_LSB 26 193 #define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000 194 195 #define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET 0x00000010 196 #define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB 28 197 #define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK 0x30000000 198 199 #define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010 200 #define TCL_DATA_CMD_4_RESERVED_4B_LSB 30 201 #define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xc0000000 202 203 #define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014 204 #define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0 205 #define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f 206 207 #define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014 208 #define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6 209 #define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0 210 211 #define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014 212 #define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26 213 #define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000 214 215 #define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014 216 #define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30 217 #define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000 218 219 #define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 220 #define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 221 #define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff 222 223 #define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 224 #define TCL_DATA_CMD_6_RING_ID_LSB 20 225 #define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 226 227 #define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 228 #define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 229 #define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 230 231 #endif 232