1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _TCL_GSE_CMD_H_ 23 #define _TCL_GSE_CMD_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 28 29 struct tcl_gse_cmd { 30 uint32_t control_buffer_addr_31_0 : 32; 31 uint32_t control_buffer_addr_39_32 : 8, 32 gse_ctrl : 4, 33 gse_sel : 1, 34 status_destination_ring_id : 1, 35 swap : 1, 36 index_search_en : 1, 37 cache_set_num : 4, 38 reserved_1a : 12; 39 uint32_t cmd_meta_data_31_0 : 32; 40 uint32_t cmd_meta_data_63_32 : 32; 41 uint32_t reserved_4a : 32; 42 uint32_t reserved_5a : 32; 43 uint32_t reserved_6a : 20, 44 ring_id : 8, 45 looping_count : 4; 46 }; 47 48 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 49 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 50 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 51 52 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 53 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 54 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 55 56 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 57 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 58 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 59 60 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 61 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 62 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 63 64 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 65 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 66 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 67 68 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 69 #define TCL_GSE_CMD_1_SWAP_LSB 14 70 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 71 72 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 73 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 74 #define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 75 76 #define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 77 #define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 78 #define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 79 80 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 81 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 82 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 83 84 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 85 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 86 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 87 88 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 89 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 90 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 91 92 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 93 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 94 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 95 96 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 97 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 98 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 99 100 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 101 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 102 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 103 104 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 105 #define TCL_GSE_CMD_6_RING_ID_LSB 20 106 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 107 108 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 109 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 110 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 111 112 #endif 113