1 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 21 22 #ifndef _WBM_RELEASE_RING_H_ 23 #define _WBM_RELEASE_RING_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "buffer_addr_info.h" 28 #include "tx_rate_stats_info.h" 29 30 #define NUM_OF_DWORDS_WBM_RELEASE_RING 8 31 32 struct wbm_release_ring { 33 struct buffer_addr_info released_buff_or_desc_addr_info; 34 uint32_t release_source_module : 3, 35 bm_action : 3, 36 buffer_or_desc_type : 3, 37 first_msdu_index : 4, 38 tqm_release_reason : 4, 39 rxdma_push_reason : 2, 40 rxdma_error_code : 5, 41 reo_push_reason : 2, 42 reo_error_code : 5, 43 wbm_internal_error : 1; 44 uint32_t tqm_status_number : 24, 45 transmit_count : 7, 46 msdu_continuation : 1; 47 uint32_t ack_frame_rssi : 8, 48 sw_release_details_valid : 1, 49 first_msdu : 1, 50 last_msdu : 1, 51 msdu_part_of_amsdu : 1, 52 fw_tx_notify_frame : 1, 53 buffer_timestamp : 19; 54 struct tx_rate_stats_info tx_rate_stats; 55 uint32_t sw_peer_id : 16, 56 tid : 4, 57 ring_id : 8, 58 looping_count : 4; 59 }; 60 61 #define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 62 #define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 63 #define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 64 65 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 66 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 67 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 68 69 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 70 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 71 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 72 73 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 74 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 75 #define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 76 77 #define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 78 #define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 79 #define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 80 81 #define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 82 #define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 83 #define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 84 85 #define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 86 #define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 87 #define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 88 89 #define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 90 #define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 91 #define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 92 93 #define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 94 #define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 95 #define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000 96 97 #define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 98 #define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17 99 #define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000 100 101 #define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 102 #define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19 103 #define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000 104 105 #define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 106 #define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24 107 #define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000 108 109 #define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 110 #define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26 111 #define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000 112 113 #define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 114 #define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31 115 #define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000 116 117 #define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c 118 #define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 119 #define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff 120 121 #define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c 122 #define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 123 #define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 124 125 #define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c 126 #define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31 127 #define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000 128 129 #define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 130 #define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 131 #define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff 132 133 #define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 134 #define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 135 #define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 136 137 #define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 138 #define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 139 #define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 140 141 #define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 142 #define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 143 #define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 144 145 #define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 146 #define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 147 #define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 148 149 #define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 150 #define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 151 #define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 152 153 #define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 154 #define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 155 #define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 156 157 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 158 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 159 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 160 161 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 162 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1 163 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006 164 165 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 166 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3 167 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078 168 169 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 170 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7 171 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080 172 173 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 174 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8 175 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100 176 177 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 178 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9 179 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600 180 181 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 182 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11 183 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800 184 185 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 186 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15 187 #define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000 188 189 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 190 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16 191 #define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000 192 193 #define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 194 #define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28 195 #define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000 196 197 #define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 198 #define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 199 #define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 200 201 #define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c 202 #define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 203 #define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff 204 205 #define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c 206 #define WBM_RELEASE_RING_7_TID_LSB 16 207 #define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 208 209 #define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c 210 #define WBM_RELEASE_RING_7_RING_ID_LSB 20 211 #define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 212 213 #define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 214 #define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 215 #define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 216 217 #endif 218