1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _REO_FLUSH_QUEUE_H_ 19*5113495bSYour Name #define _REO_FLUSH_QUEUE_H_ 20*5113495bSYour Name 21*5113495bSYour Name #include "uniform_reo_cmd_header.h" 22*5113495bSYour Name #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 23*5113495bSYour Name 24*5113495bSYour Name struct reo_flush_queue { 25*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 27*5113495bSYour Name uint32_t flush_desc_addr_31_0 : 32; 28*5113495bSYour Name uint32_t flush_desc_addr_39_32 : 8, 29*5113495bSYour Name block_desc_addr_usage_after_flush : 1, 30*5113495bSYour Name block_resource_index : 2, 31*5113495bSYour Name reserved_2a : 21; 32*5113495bSYour Name uint32_t reserved_3a : 32; 33*5113495bSYour Name uint32_t reserved_4a : 32; 34*5113495bSYour Name uint32_t reserved_5a : 32; 35*5113495bSYour Name uint32_t reserved_6a : 32; 36*5113495bSYour Name uint32_t reserved_7a : 32; 37*5113495bSYour Name uint32_t reserved_8a : 32; 38*5113495bSYour Name #else 39*5113495bSYour Name struct uniform_reo_cmd_header cmd_header; 40*5113495bSYour Name uint32_t flush_desc_addr_31_0 : 32; 41*5113495bSYour Name uint32_t reserved_2a : 21, 42*5113495bSYour Name block_resource_index : 2, 43*5113495bSYour Name block_desc_addr_usage_after_flush : 1, 44*5113495bSYour Name flush_desc_addr_39_32 : 8; 45*5113495bSYour Name uint32_t reserved_3a : 32; 46*5113495bSYour Name uint32_t reserved_4a : 32; 47*5113495bSYour Name uint32_t reserved_5a : 32; 48*5113495bSYour Name uint32_t reserved_6a : 32; 49*5113495bSYour Name uint32_t reserved_7a : 32; 50*5113495bSYour Name uint32_t reserved_8a : 32; 51*5113495bSYour Name #endif 52*5113495bSYour Name }; 53*5113495bSYour Name 54*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 55*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 56*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 57*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 58*5113495bSYour Name 59*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 60*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 61*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 62*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 63*5113495bSYour Name 64*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 65*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 66*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 67*5113495bSYour Name #define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 68*5113495bSYour Name 69*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 70*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 0 71*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 31 72*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff 73*5113495bSYour Name 74*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 75*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 76*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 77*5113495bSYour Name #define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff 78*5113495bSYour Name 79*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 80*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 81*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 82*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 83*5113495bSYour Name 84*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 85*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 86*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 87*5113495bSYour Name #define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x00000600 88*5113495bSYour Name 89*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x00000008 90*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 91*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 92*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0xfffff800 93*5113495bSYour Name 94*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000c 95*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_LSB 0 96*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MSB 31 97*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff 98*5113495bSYour Name 99*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x00000010 100*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 101*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 102*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0xffffffff 103*5113495bSYour Name 104*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x00000014 105*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_LSB 0 106*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MSB 31 107*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff 108*5113495bSYour Name 109*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x00000018 110*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 111*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 112*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0xffffffff 113*5113495bSYour Name 114*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000001c 115*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_LSB 0 116*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MSB 31 117*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff 118*5113495bSYour Name 119*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x00000020 120*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 121*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 122*5113495bSYour Name #define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0xffffffff 123*5113495bSYour Name 124*5113495bSYour Name #endif 125