xref: /wlan-driver/fw-api/hw/wcn7750/v1/reo_unblock_cache_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _REO_UNBLOCK_CACHE_STATUS_H_
19 #define _REO_UNBLOCK_CACHE_STATUS_H_
20 
21 #include "uniform_reo_status_header.h"
22 #define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 27
23 
24 struct reo_unblock_cache_status {
25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
26              uint32_t tlv32_ring_padding                                      : 32;
27              struct   uniform_reo_status_header                                 status_header;
28              uint32_t error_detected                                          :  1,
29                       unblock_type                                            :  1,
30                       reserved_2a                                             : 30;
31              uint32_t reserved_3a                                             : 32;
32              uint32_t reserved_4a                                             : 32;
33              uint32_t reserved_5a                                             : 32;
34              uint32_t reserved_6a                                             : 32;
35              uint32_t reserved_7a                                             : 32;
36              uint32_t reserved_8a                                             : 32;
37              uint32_t reserved_9a                                             : 32;
38              uint32_t reserved_10a                                            : 32;
39              uint32_t reserved_11a                                            : 32;
40              uint32_t reserved_12a                                            : 32;
41              uint32_t reserved_13a                                            : 32;
42              uint32_t reserved_14a                                            : 32;
43              uint32_t reserved_15a                                            : 32;
44              uint32_t reserved_16a                                            : 32;
45              uint32_t reserved_17a                                            : 32;
46              uint32_t reserved_18a                                            : 32;
47              uint32_t reserved_19a                                            : 32;
48              uint32_t reserved_20a                                            : 32;
49              uint32_t reserved_21a                                            : 32;
50              uint32_t reserved_22a                                            : 32;
51              uint32_t reserved_23a                                            : 32;
52              uint32_t reserved_24a                                            : 32;
53              uint32_t reserved_25a                                            : 28,
54                       looping_count                                           :  4;
55 #else
56              uint32_t tlv32_ring_padding                                      : 32;
57              struct   uniform_reo_status_header                                 status_header;
58              uint32_t reserved_2a                                             : 30,
59                       unblock_type                                            :  1,
60                       error_detected                                          :  1;
61              uint32_t reserved_3a                                             : 32;
62              uint32_t reserved_4a                                             : 32;
63              uint32_t reserved_5a                                             : 32;
64              uint32_t reserved_6a                                             : 32;
65              uint32_t reserved_7a                                             : 32;
66              uint32_t reserved_8a                                             : 32;
67              uint32_t reserved_9a                                             : 32;
68              uint32_t reserved_10a                                            : 32;
69              uint32_t reserved_11a                                            : 32;
70              uint32_t reserved_12a                                            : 32;
71              uint32_t reserved_13a                                            : 32;
72              uint32_t reserved_14a                                            : 32;
73              uint32_t reserved_15a                                            : 32;
74              uint32_t reserved_16a                                            : 32;
75              uint32_t reserved_17a                                            : 32;
76              uint32_t reserved_18a                                            : 32;
77              uint32_t reserved_19a                                            : 32;
78              uint32_t reserved_20a                                            : 32;
79              uint32_t reserved_21a                                            : 32;
80              uint32_t reserved_22a                                            : 32;
81              uint32_t reserved_23a                                            : 32;
82              uint32_t reserved_24a                                            : 32;
83              uint32_t looping_count                                           :  4,
84                       reserved_25a                                            : 28;
85 #endif
86 };
87 
88 #define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_OFFSET                          0x00000000
89 #define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_LSB                             0
90 #define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MSB                             31
91 #define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MASK                            0xffffffff
92 
93 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET             0x00000004
94 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                0
95 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                15
96 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK               0x0000ffff
97 
98 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET            0x00000004
99 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB               16
100 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB               25
101 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK              0x03ff0000
102 
103 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET      0x00000004
104 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB         26
105 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB         27
106 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK        0x0c000000
107 
108 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                   0x00000004
109 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                      28
110 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                      31
111 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                     0xf0000000
112 
113 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                     0x00000008
114 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                        0
115 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                        31
116 #define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                       0xffffffff
117 
118 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET                              0x0000000c
119 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB                                 0
120 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB                                 0
121 #define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK                                0x00000001
122 
123 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET                                0x0000000c
124 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB                                   1
125 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB                                   1
126 #define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK                                  0x00000002
127 
128 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET                                 0x0000000c
129 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB                                    2
130 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB                                    31
131 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK                                   0xfffffffc
132 
133 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET                                 0x00000010
134 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB                                    0
135 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB                                    31
136 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK                                   0xffffffff
137 
138 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET                                 0x00000014
139 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB                                    0
140 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB                                    31
141 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK                                   0xffffffff
142 
143 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET                                 0x00000018
144 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB                                    0
145 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB                                    31
146 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK                                   0xffffffff
147 
148 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET                                 0x0000001c
149 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB                                    0
150 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB                                    31
151 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK                                   0xffffffff
152 
153 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET                                 0x00000020
154 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB                                    0
155 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB                                    31
156 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK                                   0xffffffff
157 
158 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET                                 0x00000024
159 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB                                    0
160 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB                                    31
161 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK                                   0xffffffff
162 
163 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET                                 0x00000028
164 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB                                    0
165 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB                                    31
166 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK                                   0xffffffff
167 
168 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET                                0x0000002c
169 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB                                   0
170 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB                                   31
171 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK                                  0xffffffff
172 
173 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET                                0x00000030
174 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB                                   0
175 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB                                   31
176 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK                                  0xffffffff
177 
178 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET                                0x00000034
179 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB                                   0
180 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB                                   31
181 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK                                  0xffffffff
182 
183 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET                                0x00000038
184 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB                                   0
185 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB                                   31
186 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK                                  0xffffffff
187 
188 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET                                0x0000003c
189 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB                                   0
190 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB                                   31
191 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK                                  0xffffffff
192 
193 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET                                0x00000040
194 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB                                   0
195 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB                                   31
196 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK                                  0xffffffff
197 
198 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET                                0x00000044
199 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB                                   0
200 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB                                   31
201 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK                                  0xffffffff
202 
203 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET                                0x00000048
204 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB                                   0
205 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB                                   31
206 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK                                  0xffffffff
207 
208 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET                                0x0000004c
209 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB                                   0
210 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB                                   31
211 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK                                  0xffffffff
212 
213 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET                                0x00000050
214 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB                                   0
215 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB                                   31
216 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK                                  0xffffffff
217 
218 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET                                0x00000054
219 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB                                   0
220 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB                                   31
221 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK                                  0xffffffff
222 
223 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET                                0x00000058
224 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB                                   0
225 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB                                   31
226 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK                                  0xffffffff
227 
228 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET                                0x0000005c
229 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB                                   0
230 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB                                   31
231 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK                                  0xffffffff
232 
233 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET                                0x00000060
234 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB                                   0
235 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB                                   31
236 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK                                  0xffffffff
237 
238 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET                                0x00000064
239 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB                                   0
240 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB                                   31
241 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK                                  0xffffffff
242 
243 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET                                0x00000068
244 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB                                   0
245 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB                                   27
246 #define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK                                  0x0fffffff
247 
248 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET                               0x00000068
249 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB                                  28
250 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB                                  31
251 #define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK                                 0xf0000000
252 
253 #endif
254