1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _REO_UPDATE_RX_REO_QUEUE_H_ 19 #define _REO_UPDATE_RX_REO_QUEUE_H_ 20 21 #include "uniform_reo_cmd_header.h" 22 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 23 24 struct reo_update_rx_reo_queue { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct uniform_reo_cmd_header cmd_header; 27 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 28 uint32_t rx_reo_queue_desc_addr_39_32 : 8, 29 update_receive_queue_number : 1, 30 update_vld : 1, 31 update_associated_link_descriptor_counter : 1, 32 update_disable_duplicate_detection : 1, 33 update_soft_reorder_enable : 1, 34 update_ac : 1, 35 update_bar : 1, 36 update_rty : 1, 37 update_chk_2k_mode : 1, 38 update_oor_mode : 1, 39 update_ba_window_size : 1, 40 update_pn_check_needed : 1, 41 update_pn_shall_be_even : 1, 42 update_pn_shall_be_uneven : 1, 43 update_pn_handling_enable : 1, 44 update_pn_size : 1, 45 update_ignore_ampdu_flag : 1, 46 update_svld : 1, 47 update_ssn : 1, 48 update_seq_2k_error_detected_flag : 1, 49 update_pn_error_detected_flag : 1, 50 update_pn_valid : 1, 51 update_pn : 1, 52 clear_stat_counters : 1; 53 uint32_t receive_queue_number : 16, 54 vld : 1, 55 associated_link_descriptor_counter : 2, 56 disable_duplicate_detection : 1, 57 soft_reorder_enable : 1, 58 ac : 2, 59 bar : 1, 60 rty : 1, 61 chk_2k_mode : 1, 62 oor_mode : 1, 63 pn_check_needed : 1, 64 pn_shall_be_even : 1, 65 pn_shall_be_uneven : 1, 66 pn_handling_enable : 1, 67 ignore_ampdu_flag : 1; 68 uint32_t ba_window_size : 10, 69 pn_size : 2, 70 svld : 1, 71 ssn : 12, 72 seq_2k_error_detected_flag : 1, 73 pn_error_detected_flag : 1, 74 pn_valid : 1, 75 flush_from_cache : 1, 76 reserved_4a : 3; 77 uint32_t pn_31_0 : 32; 78 uint32_t pn_63_32 : 32; 79 uint32_t pn_95_64 : 32; 80 uint32_t pn_127_96 : 32; 81 #else 82 struct uniform_reo_cmd_header cmd_header; 83 uint32_t rx_reo_queue_desc_addr_31_0 : 32; 84 uint32_t clear_stat_counters : 1, 85 update_pn : 1, 86 update_pn_valid : 1, 87 update_pn_error_detected_flag : 1, 88 update_seq_2k_error_detected_flag : 1, 89 update_ssn : 1, 90 update_svld : 1, 91 update_ignore_ampdu_flag : 1, 92 update_pn_size : 1, 93 update_pn_handling_enable : 1, 94 update_pn_shall_be_uneven : 1, 95 update_pn_shall_be_even : 1, 96 update_pn_check_needed : 1, 97 update_ba_window_size : 1, 98 update_oor_mode : 1, 99 update_chk_2k_mode : 1, 100 update_rty : 1, 101 update_bar : 1, 102 update_ac : 1, 103 update_soft_reorder_enable : 1, 104 update_disable_duplicate_detection : 1, 105 update_associated_link_descriptor_counter : 1, 106 update_vld : 1, 107 update_receive_queue_number : 1, 108 rx_reo_queue_desc_addr_39_32 : 8; 109 uint32_t ignore_ampdu_flag : 1, 110 pn_handling_enable : 1, 111 pn_shall_be_uneven : 1, 112 pn_shall_be_even : 1, 113 pn_check_needed : 1, 114 oor_mode : 1, 115 chk_2k_mode : 1, 116 rty : 1, 117 bar : 1, 118 ac : 2, 119 soft_reorder_enable : 1, 120 disable_duplicate_detection : 1, 121 associated_link_descriptor_counter : 2, 122 vld : 1, 123 receive_queue_number : 16; 124 uint32_t reserved_4a : 3, 125 flush_from_cache : 1, 126 pn_valid : 1, 127 pn_error_detected_flag : 1, 128 seq_2k_error_detected_flag : 1, 129 ssn : 12, 130 svld : 1, 131 pn_size : 2, 132 ba_window_size : 10; 133 uint32_t pn_31_0 : 32; 134 uint32_t pn_63_32 : 32; 135 uint32_t pn_95_64 : 32; 136 uint32_t pn_127_96 : 32; 137 #endif 138 }; 139 140 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 141 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 142 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 143 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff 144 145 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 146 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 147 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 148 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 149 150 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 151 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 152 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 153 #define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 154 155 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 156 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 157 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 158 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 159 160 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 161 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 162 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 163 #define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 164 165 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 166 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 167 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 168 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 169 170 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x00000008 171 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 172 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 173 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x00000200 174 175 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 176 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 177 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 178 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 179 180 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 181 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 182 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 183 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 184 185 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 186 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 187 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 188 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 189 190 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x00000008 191 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 192 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 193 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x00002000 194 195 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x00000008 196 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 197 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 198 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x00004000 199 200 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x00000008 201 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 202 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 203 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x00008000 204 205 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 206 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 207 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 208 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x00010000 209 210 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x00000008 211 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 212 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 213 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x00020000 214 215 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 216 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 217 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 218 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 219 220 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 221 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 222 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 223 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 224 225 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 226 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 227 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 228 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 229 230 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 231 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 232 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 233 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 234 235 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 236 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 237 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 238 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 239 240 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x00000008 241 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 242 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 243 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x00800000 244 245 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 246 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 247 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 248 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 249 250 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x00000008 251 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 252 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 253 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x02000000 254 255 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x00000008 256 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 257 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 258 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x04000000 259 260 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 261 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 262 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 263 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 264 265 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 266 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 267 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 268 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 269 270 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x00000008 271 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 272 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 273 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x20000000 274 275 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x00000008 276 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 277 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 278 #define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x40000000 279 280 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 281 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 282 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 283 #define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x80000000 284 285 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 286 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 287 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 288 #define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 289 290 #define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000c 291 #define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 16 292 #define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 16 293 #define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x00010000 294 295 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c 296 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 297 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 18 298 #define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 299 300 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c 301 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 19 302 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 19 303 #define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 304 305 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000c 306 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 20 307 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 20 308 #define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00100000 309 310 #define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000c 311 #define REO_UPDATE_RX_REO_QUEUE_AC_LSB 21 312 #define REO_UPDATE_RX_REO_QUEUE_AC_MSB 22 313 #define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x00600000 314 315 #define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000c 316 #define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 23 317 #define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 23 318 #define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x00800000 319 320 #define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000c 321 #define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 24 322 #define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 24 323 #define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x01000000 324 325 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000c 326 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 25 327 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 25 328 #define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x02000000 329 330 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000c 331 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 26 332 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 26 333 #define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x04000000 334 335 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000c 336 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 27 337 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 27 338 #define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x08000000 339 340 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000c 341 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 28 342 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 28 343 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x10000000 344 345 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c 346 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 29 347 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 29 348 #define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x20000000 349 350 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000c 351 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 30 352 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 30 353 #define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x40000000 354 355 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c 356 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 31 357 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 31 358 #define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x80000000 359 360 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000010 361 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 362 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 363 #define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x000003ff 364 365 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000010 366 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 367 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 368 #define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x00000c00 369 370 #define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x00000010 371 #define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 372 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 373 #define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x00001000 374 375 #define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x00000010 376 #define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 377 #define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 378 #define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x01ffe000 379 380 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 381 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 382 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 383 #define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x02000000 384 385 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 386 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 387 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 388 #define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x04000000 389 390 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x00000010 391 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 392 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 393 #define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x08000000 394 395 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x00000010 396 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 397 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 398 #define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x10000000 399 400 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x00000010 401 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 402 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 403 #define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0xe0000000 404 405 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x00000014 406 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 0 407 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 31 408 #define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 409 410 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x00000018 411 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 412 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 413 #define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 414 415 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000001c 416 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 0 417 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 31 418 #define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 419 420 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x00000020 421 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 422 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 423 #define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 424 425 #endif 426