1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_MPDU_END_H_ 19 #define _RX_MPDU_END_H_ 20 21 #define NUM_OF_DWORDS_RX_MPDU_END 4 22 23 struct rx_mpdu_end { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t rxpcu_mpdu_filter_in_category : 2, 26 sw_frame_group_id : 7, 27 reserved_0 : 7, 28 phy_ppdu_id : 16; 29 uint32_t reserved_1a : 11, 30 unsup_ktype_short_frame : 1, 31 rx_in_tx_decrypt_byp : 1, 32 overflow_err : 1, 33 mpdu_length_err : 1, 34 tkip_mic_err : 1, 35 decrypt_err : 1, 36 unencrypted_frame_err : 1, 37 pn_fields_contain_valid_info : 1, 38 fcs_err : 1, 39 msdu_length_err : 1, 40 rxdma0_destination_ring : 3, 41 rxdma1_destination_ring : 3, 42 decrypt_status_code : 3, 43 rx_bitmap_not_updated : 1, 44 reserved_1b : 1; 45 uint32_t reserved_2a : 15, 46 rxpcu_mgmt_sequence_nr_valid : 1, 47 rxpcu_mgmt_sequence_nr : 16; 48 uint32_t __reserved_g_0002 : 32; 49 #else 50 uint32_t phy_ppdu_id : 16, 51 reserved_0 : 7, 52 sw_frame_group_id : 7, 53 rxpcu_mpdu_filter_in_category : 2; 54 uint32_t reserved_1b : 1, 55 rx_bitmap_not_updated : 1, 56 decrypt_status_code : 3, 57 rxdma1_destination_ring : 3, 58 rxdma0_destination_ring : 3, 59 msdu_length_err : 1, 60 fcs_err : 1, 61 pn_fields_contain_valid_info : 1, 62 unencrypted_frame_err : 1, 63 decrypt_err : 1, 64 tkip_mic_err : 1, 65 mpdu_length_err : 1, 66 overflow_err : 1, 67 rx_in_tx_decrypt_byp : 1, 68 unsup_ktype_short_frame : 1, 69 reserved_1a : 11; 70 uint32_t rxpcu_mgmt_sequence_nr : 16, 71 rxpcu_mgmt_sequence_nr_valid : 1, 72 reserved_2a : 15; 73 uint32_t __reserved_g_0002 : 32; 74 #endif 75 }; 76 77 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 78 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 79 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 80 #define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 81 82 #define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 83 #define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 84 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 85 #define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc 86 87 #define RX_MPDU_END_RESERVED_0_OFFSET 0x00000000 88 #define RX_MPDU_END_RESERVED_0_LSB 9 89 #define RX_MPDU_END_RESERVED_0_MSB 15 90 #define RX_MPDU_END_RESERVED_0_MASK 0x0000fe00 91 92 #define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x00000000 93 #define RX_MPDU_END_PHY_PPDU_ID_LSB 16 94 #define RX_MPDU_END_PHY_PPDU_ID_MSB 31 95 #define RX_MPDU_END_PHY_PPDU_ID_MASK 0xffff0000 96 97 #define RX_MPDU_END_RESERVED_1A_OFFSET 0x00000004 98 #define RX_MPDU_END_RESERVED_1A_LSB 0 99 #define RX_MPDU_END_RESERVED_1A_MSB 10 100 #define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff 101 102 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 103 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 11 104 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 11 105 #define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 106 107 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 108 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 12 109 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 12 110 #define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 111 112 #define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x00000004 113 #define RX_MPDU_END_OVERFLOW_ERR_LSB 13 114 #define RX_MPDU_END_OVERFLOW_ERR_MSB 13 115 #define RX_MPDU_END_OVERFLOW_ERR_MASK 0x00002000 116 117 #define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000004 118 #define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 14 119 #define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 14 120 #define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x00004000 121 122 #define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x00000004 123 #define RX_MPDU_END_TKIP_MIC_ERR_LSB 15 124 #define RX_MPDU_END_TKIP_MIC_ERR_MSB 15 125 #define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x00008000 126 127 #define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x00000004 128 #define RX_MPDU_END_DECRYPT_ERR_LSB 16 129 #define RX_MPDU_END_DECRYPT_ERR_MSB 16 130 #define RX_MPDU_END_DECRYPT_ERR_MASK 0x00010000 131 132 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 133 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 17 134 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 17 135 #define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 136 137 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 138 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 139 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 18 140 #define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 141 142 #define RX_MPDU_END_FCS_ERR_OFFSET 0x00000004 143 #define RX_MPDU_END_FCS_ERR_LSB 19 144 #define RX_MPDU_END_FCS_ERR_MSB 19 145 #define RX_MPDU_END_FCS_ERR_MASK 0x00080000 146 147 #define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000004 148 #define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 20 149 #define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 20 150 #define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x00100000 151 152 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 153 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 21 154 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 23 155 #define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e00000 156 157 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 158 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 24 159 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 26 160 #define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x07000000 161 162 #define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x00000004 163 #define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 27 164 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 29 165 #define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x38000000 166 167 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 168 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 30 169 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 30 170 #define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x40000000 171 172 #define RX_MPDU_END_RESERVED_1B_OFFSET 0x00000004 173 #define RX_MPDU_END_RESERVED_1B_LSB 31 174 #define RX_MPDU_END_RESERVED_1B_MSB 31 175 #define RX_MPDU_END_RESERVED_1B_MASK 0x80000000 176 177 #define RX_MPDU_END_RESERVED_2A_OFFSET 0x00000008 178 #define RX_MPDU_END_RESERVED_2A_LSB 0 179 #define RX_MPDU_END_RESERVED_2A_MSB 14 180 #define RX_MPDU_END_RESERVED_2A_MASK 0x00007fff 181 182 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x00000008 183 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 184 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 185 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x00008000 186 187 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x00000008 188 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 189 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 190 #define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0xffff0000 191 192 #endif 193