1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_REO_QUEUE_H_ 19 #define _RX_REO_QUEUE_H_ 20 21 #include "uniform_descriptor_header.h" 22 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 23 24 struct rx_reo_queue { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct uniform_descriptor_header descriptor_header; 27 uint32_t receive_queue_number : 16, 28 reserved_1b : 16; 29 uint32_t vld : 1, 30 associated_link_descriptor_counter : 2, 31 disable_duplicate_detection : 1, 32 soft_reorder_enable : 1, 33 ac : 2, 34 bar : 1, 35 rty : 1, 36 chk_2k_mode : 1, 37 oor_mode : 1, 38 ba_window_size : 10, 39 pn_check_needed : 1, 40 pn_shall_be_even : 1, 41 pn_shall_be_uneven : 1, 42 pn_handling_enable : 1, 43 pn_size : 2, 44 ignore_ampdu_flag : 1, 45 reserved_2b : 4; 46 uint32_t svld : 1, 47 ssn : 12, 48 current_index : 10, 49 seq_2k_error_detected_flag : 1, 50 pn_error_detected_flag : 1, 51 reserved_3a : 6, 52 pn_valid : 1; 53 uint32_t pn_31_0 : 32; 54 uint32_t pn_63_32 : 32; 55 uint32_t pn_95_64 : 32; 56 uint32_t pn_127_96 : 32; 57 uint32_t last_rx_enqueue_timestamp : 32; 58 uint32_t last_rx_dequeue_timestamp : 32; 59 uint32_t ptr_to_next_aging_queue_31_0 : 32; 60 uint32_t ptr_to_next_aging_queue_39_32 : 8, 61 reserved_11a : 24; 62 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 63 uint32_t ptr_to_previous_aging_queue_39_32 : 8, 64 statistics_counter_index : 6, 65 reserved_13a : 18; 66 uint32_t rx_bitmap_31_0 : 32; 67 uint32_t rx_bitmap_63_32 : 32; 68 uint32_t rx_bitmap_95_64 : 32; 69 uint32_t rx_bitmap_127_96 : 32; 70 uint32_t rx_bitmap_159_128 : 32; 71 uint32_t rx_bitmap_191_160 : 32; 72 uint32_t rx_bitmap_223_192 : 32; 73 uint32_t rx_bitmap_255_224 : 32; 74 uint32_t rx_bitmap_287_256 : 32; 75 uint32_t current_mpdu_count : 7, 76 current_msdu_count : 25; 77 uint32_t last_sn_reg_index : 4, 78 timeout_count : 6, 79 forward_due_to_bar_count : 6, 80 duplicate_count : 16; 81 uint32_t frames_in_order_count : 24, 82 bar_received_count : 8; 83 uint32_t mpdu_frames_processed_count : 32; 84 uint32_t msdu_frames_processed_count : 32; 85 uint32_t total_processed_byte_count : 32; 86 uint32_t late_receive_mpdu_count : 12, 87 window_jump_2k : 4, 88 hole_count : 16; 89 uint32_t aging_drop_mpdu_count : 16, 90 aging_drop_interval : 8, 91 reserved_30 : 8; 92 uint32_t reserved_31 : 32; 93 #else 94 struct uniform_descriptor_header descriptor_header; 95 uint32_t reserved_1b : 16, 96 receive_queue_number : 16; 97 uint32_t reserved_2b : 4, 98 ignore_ampdu_flag : 1, 99 pn_size : 2, 100 pn_handling_enable : 1, 101 pn_shall_be_uneven : 1, 102 pn_shall_be_even : 1, 103 pn_check_needed : 1, 104 ba_window_size : 10, 105 oor_mode : 1, 106 chk_2k_mode : 1, 107 rty : 1, 108 bar : 1, 109 ac : 2, 110 soft_reorder_enable : 1, 111 disable_duplicate_detection : 1, 112 associated_link_descriptor_counter : 2, 113 vld : 1; 114 uint32_t pn_valid : 1, 115 reserved_3a : 6, 116 pn_error_detected_flag : 1, 117 seq_2k_error_detected_flag : 1, 118 current_index : 10, 119 ssn : 12, 120 svld : 1; 121 uint32_t pn_31_0 : 32; 122 uint32_t pn_63_32 : 32; 123 uint32_t pn_95_64 : 32; 124 uint32_t pn_127_96 : 32; 125 uint32_t last_rx_enqueue_timestamp : 32; 126 uint32_t last_rx_dequeue_timestamp : 32; 127 uint32_t ptr_to_next_aging_queue_31_0 : 32; 128 uint32_t reserved_11a : 24, 129 ptr_to_next_aging_queue_39_32 : 8; 130 uint32_t ptr_to_previous_aging_queue_31_0 : 32; 131 uint32_t reserved_13a : 18, 132 statistics_counter_index : 6, 133 ptr_to_previous_aging_queue_39_32 : 8; 134 uint32_t rx_bitmap_31_0 : 32; 135 uint32_t rx_bitmap_63_32 : 32; 136 uint32_t rx_bitmap_95_64 : 32; 137 uint32_t rx_bitmap_127_96 : 32; 138 uint32_t rx_bitmap_159_128 : 32; 139 uint32_t rx_bitmap_191_160 : 32; 140 uint32_t rx_bitmap_223_192 : 32; 141 uint32_t rx_bitmap_255_224 : 32; 142 uint32_t rx_bitmap_287_256 : 32; 143 uint32_t current_msdu_count : 25, 144 current_mpdu_count : 7; 145 uint32_t duplicate_count : 16, 146 forward_due_to_bar_count : 6, 147 timeout_count : 6, 148 last_sn_reg_index : 4; 149 uint32_t bar_received_count : 8, 150 frames_in_order_count : 24; 151 uint32_t mpdu_frames_processed_count : 32; 152 uint32_t msdu_frames_processed_count : 32; 153 uint32_t total_processed_byte_count : 32; 154 uint32_t hole_count : 16, 155 window_jump_2k : 4, 156 late_receive_mpdu_count : 12; 157 uint32_t reserved_30 : 8, 158 aging_drop_interval : 8, 159 aging_drop_mpdu_count : 16; 160 uint32_t reserved_31 : 32; 161 #endif 162 }; 163 164 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 165 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 166 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 167 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 168 169 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 170 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 171 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 172 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 173 174 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 175 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 176 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 177 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 178 179 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 180 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 181 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 182 #define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 183 184 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 185 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 186 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 187 #define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 188 189 #define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 190 #define RX_REO_QUEUE_RESERVED_1B_LSB 16 191 #define RX_REO_QUEUE_RESERVED_1B_MSB 31 192 #define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 193 194 #define RX_REO_QUEUE_VLD_OFFSET 0x00000008 195 #define RX_REO_QUEUE_VLD_LSB 0 196 #define RX_REO_QUEUE_VLD_MSB 0 197 #define RX_REO_QUEUE_VLD_MASK 0x00000001 198 199 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 200 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 201 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 202 #define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 203 204 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 205 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 206 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 207 #define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 208 209 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 210 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 211 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 212 #define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 213 214 #define RX_REO_QUEUE_AC_OFFSET 0x00000008 215 #define RX_REO_QUEUE_AC_LSB 5 216 #define RX_REO_QUEUE_AC_MSB 6 217 #define RX_REO_QUEUE_AC_MASK 0x00000060 218 219 #define RX_REO_QUEUE_BAR_OFFSET 0x00000008 220 #define RX_REO_QUEUE_BAR_LSB 7 221 #define RX_REO_QUEUE_BAR_MSB 7 222 #define RX_REO_QUEUE_BAR_MASK 0x00000080 223 224 #define RX_REO_QUEUE_RTY_OFFSET 0x00000008 225 #define RX_REO_QUEUE_RTY_LSB 8 226 #define RX_REO_QUEUE_RTY_MSB 8 227 #define RX_REO_QUEUE_RTY_MASK 0x00000100 228 229 #define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 230 #define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 231 #define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 232 #define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 233 234 #define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 235 #define RX_REO_QUEUE_OOR_MODE_LSB 10 236 #define RX_REO_QUEUE_OOR_MODE_MSB 10 237 #define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 238 239 #define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 240 #define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 241 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 242 #define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 243 244 #define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 245 #define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 246 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 247 #define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 248 249 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 250 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 251 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 252 #define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 253 254 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 255 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 256 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 257 #define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 258 259 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 260 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 261 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 262 #define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 263 264 #define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 265 #define RX_REO_QUEUE_PN_SIZE_LSB 25 266 #define RX_REO_QUEUE_PN_SIZE_MSB 26 267 #define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 268 269 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 270 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 271 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 272 #define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 273 274 #define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 275 #define RX_REO_QUEUE_RESERVED_2B_LSB 28 276 #define RX_REO_QUEUE_RESERVED_2B_MSB 31 277 #define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 278 279 #define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c 280 #define RX_REO_QUEUE_SVLD_LSB 0 281 #define RX_REO_QUEUE_SVLD_MSB 0 282 #define RX_REO_QUEUE_SVLD_MASK 0x00000001 283 284 #define RX_REO_QUEUE_SSN_OFFSET 0x0000000c 285 #define RX_REO_QUEUE_SSN_LSB 1 286 #define RX_REO_QUEUE_SSN_MSB 12 287 #define RX_REO_QUEUE_SSN_MASK 0x00001ffe 288 289 #define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c 290 #define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 291 #define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 292 #define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 293 294 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 295 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 296 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 297 #define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 298 299 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 300 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 301 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 302 #define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 303 304 #define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c 305 #define RX_REO_QUEUE_RESERVED_3A_LSB 25 306 #define RX_REO_QUEUE_RESERVED_3A_MSB 30 307 #define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 308 309 #define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c 310 #define RX_REO_QUEUE_PN_VALID_LSB 31 311 #define RX_REO_QUEUE_PN_VALID_MSB 31 312 #define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 313 314 #define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 315 #define RX_REO_QUEUE_PN_31_0_LSB 0 316 #define RX_REO_QUEUE_PN_31_0_MSB 31 317 #define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff 318 319 #define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 320 #define RX_REO_QUEUE_PN_63_32_LSB 0 321 #define RX_REO_QUEUE_PN_63_32_MSB 31 322 #define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff 323 324 #define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 325 #define RX_REO_QUEUE_PN_95_64_LSB 0 326 #define RX_REO_QUEUE_PN_95_64_MSB 31 327 #define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff 328 329 #define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c 330 #define RX_REO_QUEUE_PN_127_96_LSB 0 331 #define RX_REO_QUEUE_PN_127_96_MSB 31 332 #define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff 333 334 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 335 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 336 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 337 #define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 338 339 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 340 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 341 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 342 #define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 343 344 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 345 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 346 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 347 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 348 349 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 350 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 351 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 352 #define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 353 354 #define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c 355 #define RX_REO_QUEUE_RESERVED_11A_LSB 8 356 #define RX_REO_QUEUE_RESERVED_11A_MSB 31 357 #define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 358 359 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 360 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 361 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 362 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 363 364 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 365 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 366 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 367 #define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 368 369 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 370 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 371 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 372 #define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 373 374 #define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 375 #define RX_REO_QUEUE_RESERVED_13A_LSB 14 376 #define RX_REO_QUEUE_RESERVED_13A_MSB 31 377 #define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 378 379 #define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 380 #define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 381 #define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 382 #define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff 383 384 #define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c 385 #define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 386 #define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 387 #define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff 388 389 #define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 390 #define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 391 #define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 392 #define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff 393 394 #define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 395 #define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 396 #define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 397 #define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff 398 399 #define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 400 #define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 401 #define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 402 #define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff 403 404 #define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c 405 #define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 406 #define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 407 #define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff 408 409 #define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 410 #define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 411 #define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 412 #define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff 413 414 #define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 415 #define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 416 #define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 417 #define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff 418 419 #define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 420 #define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 421 #define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 422 #define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff 423 424 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c 425 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 426 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 427 #define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f 428 429 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c 430 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 431 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 432 #define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 433 434 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 435 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 436 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 437 #define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f 438 439 #define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 440 #define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 441 #define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 442 #define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 443 444 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 445 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 446 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 447 #define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 448 449 #define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 450 #define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 451 #define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 452 #define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 453 454 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 455 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 456 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 457 #define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 458 459 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 460 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 461 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 462 #define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 463 464 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 465 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 466 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 467 #define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 468 469 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c 470 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 471 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 472 #define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 473 474 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 475 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 476 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 477 #define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 478 479 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 480 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 481 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 482 #define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 483 484 #define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 485 #define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 486 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 487 #define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 488 489 #define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 490 #define RX_REO_QUEUE_HOLE_COUNT_LSB 16 491 #define RX_REO_QUEUE_HOLE_COUNT_MSB 31 492 #define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 493 494 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 495 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 496 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 497 #define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff 498 499 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 500 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 501 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 502 #define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 503 504 #define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 505 #define RX_REO_QUEUE_RESERVED_30_LSB 24 506 #define RX_REO_QUEUE_RESERVED_30_MSB 31 507 #define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 508 509 #define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c 510 #define RX_REO_QUEUE_RESERVED_31_LSB 0 511 #define RX_REO_QUEUE_RESERVED_31_MSB 31 512 #define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff 513 514 #endif 515