xref: /wlan-driver/fw-api/hw/wcn7750/v1/tcl_gse_cmd.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _TCL_GSE_CMD_H_
19 #define _TCL_GSE_CMD_H_
20 
21 #define NUM_OF_DWORDS_TCL_GSE_CMD 8
22 
23 struct tcl_gse_cmd {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t control_buffer_addr_31_0                                : 32;
26              uint32_t control_buffer_addr_39_32                               :  8,
27                       gse_ctrl                                                :  4,
28                       gse_sel                                                 :  1,
29                       status_destination_ring_id                              :  1,
30                       swap                                                    :  1,
31                       index_search_en                                         :  1,
32                       cache_set_num                                           :  4,
33                       reserved_1a                                             : 12;
34              uint32_t tcl_cmd_type                                            :  1,
35                       reserved_2a                                             : 31;
36              uint32_t cmd_meta_data_31_0                                      : 32;
37              uint32_t cmd_meta_data_63_32                                     : 32;
38              uint32_t reserved_5a                                             : 32;
39              uint32_t reserved_6a                                             : 32;
40              uint32_t reserved_7a                                             : 20,
41                       ring_id                                                 :  8,
42                       looping_count                                           :  4;
43 #else
44              uint32_t control_buffer_addr_31_0                                : 32;
45              uint32_t reserved_1a                                             : 12,
46                       cache_set_num                                           :  4,
47                       index_search_en                                         :  1,
48                       swap                                                    :  1,
49                       status_destination_ring_id                              :  1,
50                       gse_sel                                                 :  1,
51                       gse_ctrl                                                :  4,
52                       control_buffer_addr_39_32                               :  8;
53              uint32_t reserved_2a                                             : 31,
54                       tcl_cmd_type                                            :  1;
55              uint32_t cmd_meta_data_31_0                                      : 32;
56              uint32_t cmd_meta_data_63_32                                     : 32;
57              uint32_t reserved_5a                                             : 32;
58              uint32_t reserved_6a                                             : 32;
59              uint32_t looping_count                                           :  4,
60                       ring_id                                                 :  8,
61                       reserved_7a                                             : 20;
62 #endif
63 };
64 
65 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET                                 0x00000000
66 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB                                    0
67 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB                                    31
68 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK                                   0xffffffff
69 
70 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET                                0x00000004
71 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB                                   0
72 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB                                   7
73 #define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK                                  0x000000ff
74 
75 #define TCL_GSE_CMD_GSE_CTRL_OFFSET                                                 0x00000004
76 #define TCL_GSE_CMD_GSE_CTRL_LSB                                                    8
77 #define TCL_GSE_CMD_GSE_CTRL_MSB                                                    11
78 #define TCL_GSE_CMD_GSE_CTRL_MASK                                                   0x00000f00
79 
80 #define TCL_GSE_CMD_GSE_SEL_OFFSET                                                  0x00000004
81 #define TCL_GSE_CMD_GSE_SEL_LSB                                                     12
82 #define TCL_GSE_CMD_GSE_SEL_MSB                                                     12
83 #define TCL_GSE_CMD_GSE_SEL_MASK                                                    0x00001000
84 
85 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET                               0x00000004
86 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB                                  13
87 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB                                  13
88 #define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK                                 0x00002000
89 
90 #define TCL_GSE_CMD_SWAP_OFFSET                                                     0x00000004
91 #define TCL_GSE_CMD_SWAP_LSB                                                        14
92 #define TCL_GSE_CMD_SWAP_MSB                                                        14
93 #define TCL_GSE_CMD_SWAP_MASK                                                       0x00004000
94 
95 #define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET                                          0x00000004
96 #define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB                                             15
97 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB                                             15
98 #define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK                                            0x00008000
99 
100 #define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET                                            0x00000004
101 #define TCL_GSE_CMD_CACHE_SET_NUM_LSB                                               16
102 #define TCL_GSE_CMD_CACHE_SET_NUM_MSB                                               19
103 #define TCL_GSE_CMD_CACHE_SET_NUM_MASK                                              0x000f0000
104 
105 #define TCL_GSE_CMD_RESERVED_1A_OFFSET                                              0x00000004
106 #define TCL_GSE_CMD_RESERVED_1A_LSB                                                 20
107 #define TCL_GSE_CMD_RESERVED_1A_MSB                                                 31
108 #define TCL_GSE_CMD_RESERVED_1A_MASK                                                0xfff00000
109 
110 #define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET                                             0x00000008
111 #define TCL_GSE_CMD_TCL_CMD_TYPE_LSB                                                0
112 #define TCL_GSE_CMD_TCL_CMD_TYPE_MSB                                                0
113 #define TCL_GSE_CMD_TCL_CMD_TYPE_MASK                                               0x00000001
114 
115 #define TCL_GSE_CMD_RESERVED_2A_OFFSET                                              0x00000008
116 #define TCL_GSE_CMD_RESERVED_2A_LSB                                                 1
117 #define TCL_GSE_CMD_RESERVED_2A_MSB                                                 31
118 #define TCL_GSE_CMD_RESERVED_2A_MASK                                                0xfffffffe
119 
120 #define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET                                       0x0000000c
121 #define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB                                          0
122 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB                                          31
123 #define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK                                         0xffffffff
124 
125 #define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET                                      0x00000010
126 #define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB                                         0
127 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB                                         31
128 #define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK                                        0xffffffff
129 
130 #define TCL_GSE_CMD_RESERVED_5A_OFFSET                                              0x00000014
131 #define TCL_GSE_CMD_RESERVED_5A_LSB                                                 0
132 #define TCL_GSE_CMD_RESERVED_5A_MSB                                                 31
133 #define TCL_GSE_CMD_RESERVED_5A_MASK                                                0xffffffff
134 
135 #define TCL_GSE_CMD_RESERVED_6A_OFFSET                                              0x00000018
136 #define TCL_GSE_CMD_RESERVED_6A_LSB                                                 0
137 #define TCL_GSE_CMD_RESERVED_6A_MSB                                                 31
138 #define TCL_GSE_CMD_RESERVED_6A_MASK                                                0xffffffff
139 
140 #define TCL_GSE_CMD_RESERVED_7A_OFFSET                                              0x0000001c
141 #define TCL_GSE_CMD_RESERVED_7A_LSB                                                 0
142 #define TCL_GSE_CMD_RESERVED_7A_MSB                                                 19
143 #define TCL_GSE_CMD_RESERVED_7A_MASK                                                0x000fffff
144 
145 #define TCL_GSE_CMD_RING_ID_OFFSET                                                  0x0000001c
146 #define TCL_GSE_CMD_RING_ID_LSB                                                     20
147 #define TCL_GSE_CMD_RING_ID_MSB                                                     27
148 #define TCL_GSE_CMD_RING_ID_MASK                                                    0x0ff00000
149 
150 #define TCL_GSE_CMD_LOOPING_COUNT_OFFSET                                            0x0000001c
151 #define TCL_GSE_CMD_LOOPING_COUNT_LSB                                               28
152 #define TCL_GSE_CMD_LOOPING_COUNT_MSB                                               31
153 #define TCL_GSE_CMD_LOOPING_COUNT_MASK                                              0xf0000000
154 
155 #endif
156