1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name #ifndef __DP_RH_TX_H 19*5113495bSYour Name #define __DP_RH_TX_H 20*5113495bSYour Name 21*5113495bSYour Name #include <dp_types.h> 22*5113495bSYour Name 23*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_NATIVE_WIFI 30 24*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_802_11_RAW 36 25*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_ETHERNET 14 26*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_IP 16 27*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_802_1Q 4 28*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_LLC_SNAP 8 29*5113495bSYour Name 30*5113495bSYour Name #define DP_RH_TX_HDR_SIZE_OUTER_HDR_MAX DP_RH_TX_HDR_SIZE_802_11_RAW 31*5113495bSYour Name 32*5113495bSYour Name #define DP_RH_TX_TLV_HDR_SIZE sizeof(struct tlv_32_hdr) 33*5113495bSYour Name #define DP_RH_TX_TCL_DESC_SIZE (HAL_TX_DESC_LEN_BYTES + DP_RH_TX_TLV_HDR_SIZE) 34*5113495bSYour Name 35*5113495bSYour Name /* 36*5113495bSYour Name * NB: intentionally not using kernel-doc comment because the kernel-doc 37*5113495bSYour Name * script does not handle the qdf_dma_mem_context macro 38*5113495bSYour Name * struct dp_tx_tcl_desc_pool_s - Tx Extension Descriptor Pool 39*5113495bSYour Name * @elem_count: Number of descriptors in the pool 40*5113495bSYour Name * @elem_size: Size of each descriptor 41*5113495bSYour Name * @desc_pages: multiple page allocation information for actual descriptors 42*5113495bSYour Name * @freelist: freelist of TCL descriptors 43*5113495bSYour Name * @memctx: 44*5113495bSYour Name */ 45*5113495bSYour Name struct dp_tx_tcl_desc_pool_s { 46*5113495bSYour Name uint16_t elem_count; 47*5113495bSYour Name int elem_size; 48*5113495bSYour Name struct qdf_mem_multi_page_t desc_pages; 49*5113495bSYour Name uint32_t *freelist; 50*5113495bSYour Name qdf_dma_mem_context(memctx); 51*5113495bSYour Name }; 52*5113495bSYour Name 53*5113495bSYour Name /** 54*5113495bSYour Name * dp_tx_hw_enqueue_rh() - Enqueue to TCL HW for transmit 55*5113495bSYour Name * @soc: DP Soc Handle 56*5113495bSYour Name * @vdev: DP vdev handle 57*5113495bSYour Name * @tx_desc: Tx Descriptor Handle 58*5113495bSYour Name * @fw_metadata: Metadata to send to Target Firmware along with frame 59*5113495bSYour Name * @tx_exc_metadata: Handle that holds exception path meta data 60*5113495bSYour Name * @msdu_info: Holds the MSDU information to be transmitted 61*5113495bSYour Name * 62*5113495bSYour Name * Gets the next free TCL HW DMA descriptor and sets up required parameters 63*5113495bSYour Name * from software Tx descriptor 64*5113495bSYour Name * 65*5113495bSYour Name * Return: QDF_STATUS_SUCCESS: success 66*5113495bSYour Name * QDF_STATUS_E_RESOURCES: Error return 67*5113495bSYour Name */ 68*5113495bSYour Name QDF_STATUS 69*5113495bSYour Name dp_tx_hw_enqueue_rh(struct dp_soc *soc, struct dp_vdev *vdev, 70*5113495bSYour Name struct dp_tx_desc_s *tx_desc, uint16_t fw_metadata, 71*5113495bSYour Name struct cdp_tx_exception_metadata *tx_exc_metadata, 72*5113495bSYour Name struct dp_tx_msdu_info_s *msdu_info); 73*5113495bSYour Name /** 74*5113495bSYour Name * dp_tx_comp_get_params_from_hal_desc_rh() - Get TX desc from HAL comp desc 75*5113495bSYour Name * @soc: DP soc handle 76*5113495bSYour Name * @tx_comp_hal_desc: HAL TX Comp Descriptor 77*5113495bSYour Name * @r_tx_desc: SW Tx Descriptor retrieved from HAL desc. 78*5113495bSYour Name * 79*5113495bSYour Name * Return: QDF_STATUS return codes 80*5113495bSYour Name */ 81*5113495bSYour Name QDF_STATUS 82*5113495bSYour Name dp_tx_comp_get_params_from_hal_desc_rh(struct dp_soc *soc, 83*5113495bSYour Name void *tx_comp_hal_desc, 84*5113495bSYour Name struct dp_tx_desc_s **r_tx_desc); 85*5113495bSYour Name 86*5113495bSYour Name /** 87*5113495bSYour Name * dp_tx_process_htt_completion_rh() - Tx HTT Completion Indication Handler 88*5113495bSYour Name * @soc: Handle to DP soc structure 89*5113495bSYour Name * @tx_desc: software descriptor head pointer 90*5113495bSYour Name * @status : Tx completion status from HTT descriptor 91*5113495bSYour Name * @ring_id: ring number 92*5113495bSYour Name * 93*5113495bSYour Name * This function will process HTT Tx indication messages from Target 94*5113495bSYour Name * 95*5113495bSYour Name * Return: none 96*5113495bSYour Name */ 97*5113495bSYour Name void dp_tx_process_htt_completion_rh(struct dp_soc *soc, 98*5113495bSYour Name struct dp_tx_desc_s *tx_desc, 99*5113495bSYour Name uint8_t *status, 100*5113495bSYour Name uint8_t ring_id); 101*5113495bSYour Name 102*5113495bSYour Name /** 103*5113495bSYour Name * dp_tx_desc_pool_init_rh() - Initialize Tx Descriptor pool(s) 104*5113495bSYour Name * @soc: Handle to DP Soc structure 105*5113495bSYour Name * @num_elem: pool descriptor number 106*5113495bSYour Name * @pool_id: pool to allocate 107*5113495bSYour Name * @spcl_tx_desc: if special desc 108*5113495bSYour Name * 109*5113495bSYour Name * Return: QDF_STATUS_SUCCESS - success, others - failure 110*5113495bSYour Name */ 111*5113495bSYour Name QDF_STATUS dp_tx_desc_pool_init_rh(struct dp_soc *soc, 112*5113495bSYour Name uint32_t num_elem, 113*5113495bSYour Name uint8_t pool_id, 114*5113495bSYour Name bool spcl_tx_desc); 115*5113495bSYour Name 116*5113495bSYour Name /** 117*5113495bSYour Name * dp_tx_desc_pool_deinit_rh() - De-initialize Tx Descriptor pool(s) 118*5113495bSYour Name * @soc: Handle to DP Soc structure 119*5113495bSYour Name * @tx_desc_pool: Tx descriptor pool handler 120*5113495bSYour Name * @pool_id: pool to deinit 121*5113495bSYour Name * @spcl_tx_desc: if special desc 122*5113495bSYour Name * 123*5113495bSYour Name * Return: None. 124*5113495bSYour Name */ 125*5113495bSYour Name void dp_tx_desc_pool_deinit_rh(struct dp_soc *soc, 126*5113495bSYour Name struct dp_tx_desc_pool_s *tx_desc_pool, 127*5113495bSYour Name uint8_t pool_id, bool spcl_tx_desc); 128*5113495bSYour Name 129*5113495bSYour Name /** 130*5113495bSYour Name * dp_tx_compute_tx_delay_rh() - Compute HW Tx completion delay 131*5113495bSYour Name * @soc: Handle to DP Soc structure 132*5113495bSYour Name * @vdev: vdev 133*5113495bSYour Name * @ts: Tx completion status 134*5113495bSYour Name * @delay_us: Delay to be calculated in microseconds 135*5113495bSYour Name * 136*5113495bSYour Name * Return: QDF_STATUS 137*5113495bSYour Name */ 138*5113495bSYour Name QDF_STATUS dp_tx_compute_tx_delay_rh(struct dp_soc *soc, 139*5113495bSYour Name struct dp_vdev *vdev, 140*5113495bSYour Name struct hal_tx_completion_status *ts, 141*5113495bSYour Name uint32_t *delay_us); 142*5113495bSYour Name 143*5113495bSYour Name /** 144*5113495bSYour Name * dp_tx_desc_pool_alloc_rh() - Allocate coherent memory for TCL descriptors 145*5113495bSYour Name * @soc: Handle to DP Soc structure 146*5113495bSYour Name * @num_elem: Number of elements to allocate 147*5113495bSYour Name * @pool_id: TCL descriptor pool ID 148*5113495bSYour Name * 149*5113495bSYour Name * Return: QDF_STATUS_SUCCESS - success, others - failure 150*5113495bSYour Name */ 151*5113495bSYour Name QDF_STATUS dp_tx_desc_pool_alloc_rh(struct dp_soc *soc, uint32_t num_elem, 152*5113495bSYour Name uint8_t pool_id); 153*5113495bSYour Name 154*5113495bSYour Name /** 155*5113495bSYour Name * dp_tx_desc_pool_free_rh() - Free TCL descriptor memory 156*5113495bSYour Name * @soc: Handle to DP Soc structure 157*5113495bSYour Name * @pool_id: TCL descriptor pool ID 158*5113495bSYour Name * 159*5113495bSYour Name * Return: none 160*5113495bSYour Name */ 161*5113495bSYour Name void dp_tx_desc_pool_free_rh(struct dp_soc *soc, uint8_t pool_id); 162*5113495bSYour Name 163*5113495bSYour Name /** 164*5113495bSYour Name * dp_tx_compl_handler_rh() - TX completion handler for Rhine 165*5113495bSYour Name * @soc: Handle to DP Soc structure 166*5113495bSYour Name * @htt_msg: TX completion HTT message 167*5113495bSYour Name * 168*5113495bSYour Name * Return: none 169*5113495bSYour Name */ 170*5113495bSYour Name void dp_tx_compl_handler_rh(struct dp_soc *soc, qdf_nbuf_t htt_msg); 171*5113495bSYour Name 172*5113495bSYour Name /** 173*5113495bSYour Name * dp_flush_tx_ring_rh() - flush tx ring write index 174*5113495bSYour Name * @pdev: dp pdev handle 175*5113495bSYour Name * @ring_id: Tx ring id 176*5113495bSYour Name * 177*5113495bSYour Name * Return: 0 on success and error code on failure 178*5113495bSYour Name */ 179*5113495bSYour Name int dp_flush_tx_ring_rh(struct dp_pdev *pdev, int ring_id); 180*5113495bSYour Name #endif 181