1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 7*5113495bSYour Name * above copyright notice and this permission notice appear in all 8*5113495bSYour Name * copies. 9*5113495bSYour Name * 10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 18*5113495bSYour Name */ 19*5113495bSYour Name 20*5113495bSYour Name #ifndef _HAL_BE_API_H_ 21*5113495bSYour Name #define _HAL_BE_API_H_ 22*5113495bSYour Name 23*5113495bSYour Name #include "hal_hw_headers.h" 24*5113495bSYour Name #include "hal_rx.h" 25*5113495bSYour Name 26*5113495bSYour Name #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \ 27*5113495bSYour Name ((struct rx_msdu_ext_desc_info *) \ 28*5113495bSYour Name _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 29*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) 30*5113495bSYour Name 31*5113495bSYour Name /** 32*5113495bSYour Name * hal_reo_setup_generic_be - Initialize HW REO block 33*5113495bSYour Name * 34*5113495bSYour Name * @soc: Opaque HAL SOC handle 35*5113495bSYour Name * @reoparams: parameters needed by HAL for REO config 36*5113495bSYour Name * @qref_reset: reset qref 37*5113495bSYour Name */ 38*5113495bSYour Name void hal_reo_setup_generic_be(struct hal_soc *soc, 39*5113495bSYour Name void *reoparams, int qref_reset); 40*5113495bSYour Name 41*5113495bSYour Name /** 42*5113495bSYour Name * hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension 43*5113495bSYour Name * descriptor pointer. 44*5113495bSYour Name * @msdu_details_ptr: msdu details 45*5113495bSYour Name * 46*5113495bSYour Name * Return: msdu exntension descriptor pointer. 47*5113495bSYour Name */ 48*5113495bSYour Name void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr); 49*5113495bSYour Name 50*5113495bSYour Name /** 51*5113495bSYour Name * hal_set_link_desc_addr_be - Setup link descriptor in a buffer_addr_info 52*5113495bSYour Name * HW structure 53*5113495bSYour Name * 54*5113495bSYour Name * @desc: Descriptor entry (from WBM_IDLE_LINK ring) 55*5113495bSYour Name * @cookie: SW cookie for the buffer/descriptor 56*5113495bSYour Name * @link_desc_paddr: Physical address of link descriptor entry 57*5113495bSYour Name * @bm_id: idle link BM id 58*5113495bSYour Name * 59*5113495bSYour Name */ 60*5113495bSYour Name void hal_set_link_desc_addr_be(void *desc, uint32_t cookie, 61*5113495bSYour Name qdf_dma_addr_t link_desc_paddr, 62*5113495bSYour Name uint8_t bm_id); 63*5113495bSYour Name 64*5113495bSYour Name /** 65*5113495bSYour Name * hal_hw_txrx_default_ops_attach_be() - Add default ops for BE chips 66*5113495bSYour Name * @soc: hal_soc handle 67*5113495bSYour Name * 68*5113495bSYour Name * Return: None 69*5113495bSYour Name */ 70*5113495bSYour Name void hal_hw_txrx_default_ops_attach_be(struct hal_soc *soc); 71*5113495bSYour Name 72*5113495bSYour Name uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc); 73*5113495bSYour Name 74*5113495bSYour Name /** 75*5113495bSYour Name * hal_rx_ret_buf_manager_get_be() - Get return buffer manager from ring desc 76*5113495bSYour Name * @ring_desc: ring descriptor 77*5113495bSYour Name * 78*5113495bSYour Name * Return: rbm 79*5113495bSYour Name */ 80*5113495bSYour Name uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc); 81*5113495bSYour Name 82*5113495bSYour Name /** 83*5113495bSYour Name * hal_rx_wbm_err_info_get_generic_be() - Retrieves WBM error code and reason and 84*5113495bSYour Name * save it to hal_wbm_err_desc_info structure passed by caller 85*5113495bSYour Name * @wbm_desc: wbm ring descriptor 86*5113495bSYour Name * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter. 87*5113495bSYour Name * 88*5113495bSYour Name * Return: void 89*5113495bSYour Name */ 90*5113495bSYour Name void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1); 91*5113495bSYour Name 92*5113495bSYour Name /** 93*5113495bSYour Name * hal_reo_qdesc_setup_be() - Setup HW REO queue descriptor 94*5113495bSYour Name * @hal_soc_hdl: Opaque HAL SOC handle 95*5113495bSYour Name * @tid: TID 96*5113495bSYour Name * @ba_window_size: BlockAck window size 97*5113495bSYour Name * @start_seq: Starting sequence number 98*5113495bSYour Name * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory 99*5113495bSYour Name * @hw_qdesc_paddr: Physical address of REO queue descriptor memory 100*5113495bSYour Name * @pn_type: PN type (one of the types defined in 'enum hal_pn_type') 101*5113495bSYour Name * @vdev_stats_id: vdev_stats_id to be programmed in REO Queue Descriptor 102*5113495bSYour Name */ 103*5113495bSYour Name void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, 104*5113495bSYour Name int tid, uint32_t ba_window_size, 105*5113495bSYour Name uint32_t start_seq, void *hw_qdesc_vaddr, 106*5113495bSYour Name qdf_dma_addr_t hw_qdesc_paddr, 107*5113495bSYour Name int pn_type, uint8_t vdev_stats_id); 108*5113495bSYour Name 109*5113495bSYour Name /** 110*5113495bSYour Name * hal_cookie_conversion_reg_cfg_be() - set cookie conversion relevant register 111*5113495bSYour Name * for REO/WBM 112*5113495bSYour Name * @hal_soc_hdl: Handle to HAL SoC structure 113*5113495bSYour Name * @cc_cfg: structure pointer for HW cookie conversion configuration 114*5113495bSYour Name * 115*5113495bSYour Name * Return: None 116*5113495bSYour Name */ 117*5113495bSYour Name void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl, 118*5113495bSYour Name struct hal_hw_cc_config *cc_cfg); 119*5113495bSYour Name 120*5113495bSYour Name /** 121*5113495bSYour Name * hal_reo_ix_remap_value_get_be() - Calculate reo remap register value from 122*5113495bSYour Name * ring_id_mask which is used for hash based 123*5113495bSYour Name * reo distribution 124*5113495bSYour Name * @hal_soc_hdl: Handle to HAL SoC structure 125*5113495bSYour Name * @rx_ring_mask: mask value indicating the rx rings 0th bit set indicate 126*5113495bSYour Name * REO2SW1 is included in hash distribution 127*5113495bSYour Name * 128*5113495bSYour Name * Return: REO remap value 129*5113495bSYour Name */ 130*5113495bSYour Name uint32_t 131*5113495bSYour Name hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl, 132*5113495bSYour Name uint8_t rx_ring_mask); 133*5113495bSYour Name 134*5113495bSYour Name /** 135*5113495bSYour Name * hal_reo_ring_remap_value_get_be() - return REO remap value 136*5113495bSYour Name * @rx_ring_id: REO2SW ring mask 137*5113495bSYour Name * 138*5113495bSYour Name * Return: REO remap value 139*5113495bSYour Name */ 140*5113495bSYour Name uint8_t 141*5113495bSYour Name hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id); 142*5113495bSYour Name 143*5113495bSYour Name /** 144*5113495bSYour Name * hal_setup_reo_swap() - Set the swap flag for big endian machines 145*5113495bSYour Name * @soc: HAL soc handle 146*5113495bSYour Name * 147*5113495bSYour Name * Return: None 148*5113495bSYour Name */ 149*5113495bSYour Name void hal_setup_reo_swap(struct hal_soc *soc); 150*5113495bSYour Name 151*5113495bSYour Name /** 152*5113495bSYour Name * hal_get_idle_link_bm_id_be() - Get idle link BM id from chid_id 153*5113495bSYour Name * @chip_id: mlo chip_id 154*5113495bSYour Name * 155*5113495bSYour Name * Returns: RBM ID 156*5113495bSYour Name */ 157*5113495bSYour Name uint8_t hal_get_idle_link_bm_id_be(uint8_t chip_id); 158*5113495bSYour Name #endif /* _HAL_BE_API_H_ */ 159