1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for
6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the
7*5113495bSYour Name * above copyright notice and this permission notice appear in all
8*5113495bSYour Name * copies.
9*5113495bSYour Name *
10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE.
18*5113495bSYour Name */
19*5113495bSYour Name
20*5113495bSYour Name #include <qdf_module.h>
21*5113495bSYour Name #include "hal_be_api.h"
22*5113495bSYour Name #include "hal_be_hw_headers.h"
23*5113495bSYour Name #include "hal_be_reo.h"
24*5113495bSYour Name #include "hal_tx.h" //HAL_SET_FLD
25*5113495bSYour Name #include "hal_be_rx.h" //HAL_RX_BUF_RBM_GET
26*5113495bSYour Name #include "rx_reo_queue_1k.h"
27*5113495bSYour Name #include "hal_be_rx_tlv.h"
28*5113495bSYour Name
29*5113495bSYour Name /*
30*5113495bSYour Name * The 4 bits REO destination ring value is defined as: 0: TCL
31*5113495bSYour Name * 1:SW1 2:SW2 3:SW3 4:SW4 5:Release 6:FW(WIFI) 7:SW5
32*5113495bSYour Name * 8:SW6 9:SW7 10:SW8 11: NOT_USED.
33*5113495bSYour Name *
34*5113495bSYour Name */
35*5113495bSYour Name uint32_t reo_dest_ring_remap[] = {REO_REMAP_SW1, REO_REMAP_SW2,
36*5113495bSYour Name REO_REMAP_SW3, REO_REMAP_SW4,
37*5113495bSYour Name REO_REMAP_SW5, REO_REMAP_SW6,
38*5113495bSYour Name REO_REMAP_SW7, REO_REMAP_SW8};
39*5113495bSYour Name /*
40*5113495bSYour Name * WBM idle link descriptor for Return Buffer Manager in case of
41*5113495bSYour Name * multi-chip configuration.
42*5113495bSYour Name */
43*5113495bSYour Name #define HAL_NUM_CHIPS 4
44*5113495bSYour Name #define HAL_WBM_CHIP_INVALID 0
45*5113495bSYour Name #define HAL_WBM_CHIP0_IDLE_DESC_MAP 1
46*5113495bSYour Name #define HAL_WBM_CHIP1_IDLE_DESC_MAP 2
47*5113495bSYour Name #define HAL_WBM_CHIP2_IDLE_DESC_MAP 3
48*5113495bSYour Name #define HAL_WBM_CHIP3_IDLE_DESC_MAP 12
49*5113495bSYour Name
50*5113495bSYour Name uint8_t wbm_idle_link_bm_map[] = {HAL_WBM_CHIP0_IDLE_DESC_MAP,
51*5113495bSYour Name HAL_WBM_CHIP1_IDLE_DESC_MAP,
52*5113495bSYour Name HAL_WBM_CHIP2_IDLE_DESC_MAP,
53*5113495bSYour Name HAL_WBM_CHIP3_IDLE_DESC_MAP};
54*5113495bSYour Name
55*5113495bSYour Name #if defined(QDF_BIG_ENDIAN_MACHINE)
hal_setup_reo_swap(struct hal_soc * soc)56*5113495bSYour Name void hal_setup_reo_swap(struct hal_soc *soc)
57*5113495bSYour Name {
58*5113495bSYour Name uint32_t reg_val;
59*5113495bSYour Name
60*5113495bSYour Name reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
61*5113495bSYour Name REO_REG_REG_BASE));
62*5113495bSYour Name
63*5113495bSYour Name reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1);
64*5113495bSYour Name reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1);
65*5113495bSYour Name
66*5113495bSYour Name HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
67*5113495bSYour Name REO_REG_REG_BASE), reg_val);
68*5113495bSYour Name }
69*5113495bSYour Name #else
hal_setup_reo_swap(struct hal_soc * soc)70*5113495bSYour Name void hal_setup_reo_swap(struct hal_soc *soc)
71*5113495bSYour Name {
72*5113495bSYour Name }
73*5113495bSYour Name #endif
74*5113495bSYour Name
75*5113495bSYour Name /**
76*5113495bSYour Name * hal_tx_init_data_ring_be() - Initialize all the TCL Descriptors in SRNG
77*5113495bSYour Name * @hal_soc_hdl: Handle to HAL SoC structure
78*5113495bSYour Name * @hal_ring_hdl: Handle to HAL SRNG structure
79*5113495bSYour Name *
80*5113495bSYour Name * Return: none
81*5113495bSYour Name */
82*5113495bSYour Name static void
hal_tx_init_data_ring_be(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)83*5113495bSYour Name hal_tx_init_data_ring_be(hal_soc_handle_t hal_soc_hdl,
84*5113495bSYour Name hal_ring_handle_t hal_ring_hdl)
85*5113495bSYour Name {
86*5113495bSYour Name }
87*5113495bSYour Name
hal_reo_setup_generic_be(struct hal_soc * soc,void * reoparams,int qref_reset)88*5113495bSYour Name void hal_reo_setup_generic_be(struct hal_soc *soc, void *reoparams,
89*5113495bSYour Name int qref_reset)
90*5113495bSYour Name {
91*5113495bSYour Name uint32_t reg_val;
92*5113495bSYour Name struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
93*5113495bSYour Name
94*5113495bSYour Name reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
95*5113495bSYour Name REO_REG_REG_BASE));
96*5113495bSYour Name
97*5113495bSYour Name hal_reo_config(soc, reg_val, reo_params);
98*5113495bSYour Name /* Other ring enable bits and REO_ENABLE will be set by FW */
99*5113495bSYour Name
100*5113495bSYour Name /* TODO: Setup destination ring mapping if enabled */
101*5113495bSYour Name
102*5113495bSYour Name /* TODO: Error destination ring setting is left to default.
103*5113495bSYour Name * Default setting is to send all errors to release ring.
104*5113495bSYour Name */
105*5113495bSYour Name
106*5113495bSYour Name /* Set the reo descriptor swap bits in case of BIG endian platform */
107*5113495bSYour Name hal_setup_reo_swap(soc);
108*5113495bSYour Name
109*5113495bSYour Name HAL_REG_WRITE(soc,
110*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
111*5113495bSYour Name HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
112*5113495bSYour Name
113*5113495bSYour Name HAL_REG_WRITE(soc,
114*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
115*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
116*5113495bSYour Name
117*5113495bSYour Name HAL_REG_WRITE(soc,
118*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
119*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
120*5113495bSYour Name
121*5113495bSYour Name HAL_REG_WRITE(soc,
122*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
123*5113495bSYour Name (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
124*5113495bSYour Name
125*5113495bSYour Name /*
126*5113495bSYour Name * When hash based routing is enabled, routing of the rx packet
127*5113495bSYour Name * is done based on the following value: 1 _ _ _ _ The last 4
128*5113495bSYour Name * bits are based on hash[3:0]. This means the possible values
129*5113495bSYour Name * are 0x10 to 0x1f. This value is used to look-up the
130*5113495bSYour Name * ring ID configured in Destination_Ring_Ctrl_IX_* register.
131*5113495bSYour Name * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
132*5113495bSYour Name * registers need to be configured to set-up the 16 entries to
133*5113495bSYour Name * map the hash values to a ring number. There are 3 bits per
134*5113495bSYour Name * hash entry – which are mapped as follows:
135*5113495bSYour Name * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
136*5113495bSYour Name * 7: NOT_USED.
137*5113495bSYour Name */
138*5113495bSYour Name if (reo_params->rx_hash_enabled) {
139*5113495bSYour Name HAL_REG_WRITE(soc,
140*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
141*5113495bSYour Name REO_REG_REG_BASE),
142*5113495bSYour Name reo_params->remap1);
143*5113495bSYour Name
144*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
145*5113495bSYour Name HAL_REG_READ(soc,
146*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
147*5113495bSYour Name REO_REG_REG_BASE)));
148*5113495bSYour Name
149*5113495bSYour Name HAL_REG_WRITE(soc,
150*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
151*5113495bSYour Name REO_REG_REG_BASE),
152*5113495bSYour Name reo_params->remap2);
153*5113495bSYour Name
154*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
155*5113495bSYour Name HAL_REG_READ(soc,
156*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
157*5113495bSYour Name REO_REG_REG_BASE)));
158*5113495bSYour Name }
159*5113495bSYour Name
160*5113495bSYour Name /* TODO: Check if the following registers shoould be setup by host:
161*5113495bSYour Name * AGING_CONTROL
162*5113495bSYour Name * HIGH_MEMORY_THRESHOLD
163*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
164*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_CTRL
165*5113495bSYour Name */
166*5113495bSYour Name }
167*5113495bSYour Name
hal_set_link_desc_addr_be(void * desc,uint32_t cookie,qdf_dma_addr_t link_desc_paddr,uint8_t bm_id)168*5113495bSYour Name void hal_set_link_desc_addr_be(void *desc, uint32_t cookie,
169*5113495bSYour Name qdf_dma_addr_t link_desc_paddr,
170*5113495bSYour Name uint8_t bm_id)
171*5113495bSYour Name {
172*5113495bSYour Name uint32_t *buf_addr = (uint32_t *)desc;
173*5113495bSYour Name
174*5113495bSYour Name HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO, BUFFER_ADDR_31_0,
175*5113495bSYour Name link_desc_paddr & 0xffffffff);
176*5113495bSYour Name HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO, BUFFER_ADDR_39_32,
177*5113495bSYour Name (uint64_t)link_desc_paddr >> 32);
178*5113495bSYour Name HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO, RETURN_BUFFER_MANAGER,
179*5113495bSYour Name bm_id);
180*5113495bSYour Name HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO, SW_BUFFER_COOKIE,
181*5113495bSYour Name cookie);
182*5113495bSYour Name }
183*5113495bSYour Name
hal_get_rx_max_ba_window_be(int tid)184*5113495bSYour Name static uint16_t hal_get_rx_max_ba_window_be(int tid)
185*5113495bSYour Name {
186*5113495bSYour Name return HAL_RX_BA_WINDOW_256;
187*5113495bSYour Name }
188*5113495bSYour Name
hal_get_reo_qdesc_size_be(uint32_t ba_window_size,int tid)189*5113495bSYour Name static uint32_t hal_get_reo_qdesc_size_be(uint32_t ba_window_size, int tid)
190*5113495bSYour Name {
191*5113495bSYour Name /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
192*5113495bSYour Name * NON_QOS_TID until HW issues are resolved.
193*5113495bSYour Name */
194*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
195*5113495bSYour Name ba_window_size = hal_get_rx_max_ba_window_be(tid);
196*5113495bSYour Name
197*5113495bSYour Name /* Return descriptor size corresponding to window size of 2 since
198*5113495bSYour Name * we set ba_window_size to 2 while setting up REO descriptors as
199*5113495bSYour Name * a WAR to get 2k jump exception aggregates are received without
200*5113495bSYour Name * a BA session.
201*5113495bSYour Name */
202*5113495bSYour Name if (ba_window_size <= 1) {
203*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
204*5113495bSYour Name return sizeof(struct rx_reo_queue) +
205*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
206*5113495bSYour Name else
207*5113495bSYour Name return sizeof(struct rx_reo_queue);
208*5113495bSYour Name }
209*5113495bSYour Name
210*5113495bSYour Name if (ba_window_size <= 105)
211*5113495bSYour Name return sizeof(struct rx_reo_queue) +
212*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
213*5113495bSYour Name
214*5113495bSYour Name if (ba_window_size <= 210)
215*5113495bSYour Name return sizeof(struct rx_reo_queue) +
216*5113495bSYour Name (2 * sizeof(struct rx_reo_queue_ext));
217*5113495bSYour Name
218*5113495bSYour Name return sizeof(struct rx_reo_queue) +
219*5113495bSYour Name (3 * sizeof(struct rx_reo_queue_ext));
220*5113495bSYour Name }
221*5113495bSYour Name
hal_rx_msdu_ext_desc_info_get_ptr_be(void * msdu_details_ptr)222*5113495bSYour Name void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr)
223*5113495bSYour Name {
224*5113495bSYour Name return HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr);
225*5113495bSYour Name }
226*5113495bSYour Name
227*5113495bSYour Name #if defined(QCA_WIFI_KIWI) && !defined(QCA_WIFI_KIWI_V2)
228*5113495bSYour Name static inline uint32_t
hal_wbm2sw_release_source_get(void * hal_desc,enum hal_be_wbm_release_dir dir)229*5113495bSYour Name hal_wbm2sw_release_source_get(void *hal_desc, enum hal_be_wbm_release_dir dir)
230*5113495bSYour Name {
231*5113495bSYour Name uint32_t buf_src;
232*5113495bSYour Name
233*5113495bSYour Name buf_src = HAL_WBM2SW_RELEASE_SRC_GET(hal_desc);
234*5113495bSYour Name switch (buf_src) {
235*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_RXDMA:
236*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_RXDMA;
237*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_REO:
238*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_REO;
239*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_FW_RX:
240*5113495bSYour Name if (dir != HAL_BE_WBM_RELEASE_DIR_RX)
241*5113495bSYour Name qdf_assert_always(0);
242*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_FW;
243*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_SW_RX:
244*5113495bSYour Name if (dir != HAL_BE_WBM_RELEASE_DIR_RX)
245*5113495bSYour Name qdf_assert_always(0);
246*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_SW;
247*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_TQM:
248*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_TQM;
249*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_FW_TX:
250*5113495bSYour Name if (dir != HAL_BE_WBM_RELEASE_DIR_TX)
251*5113495bSYour Name qdf_assert_always(0);
252*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_FW;
253*5113495bSYour Name case HAL_BE_RX_WBM_ERR_SRC_SW_TX:
254*5113495bSYour Name if (dir != HAL_BE_WBM_RELEASE_DIR_TX)
255*5113495bSYour Name qdf_assert_always(0);
256*5113495bSYour Name return HAL_RX_WBM_ERR_SRC_SW;
257*5113495bSYour Name default:
258*5113495bSYour Name qdf_assert_always(0);
259*5113495bSYour Name }
260*5113495bSYour Name
261*5113495bSYour Name return buf_src;
262*5113495bSYour Name }
263*5113495bSYour Name #else
264*5113495bSYour Name static inline uint32_t
hal_wbm2sw_release_source_get(void * hal_desc,enum hal_be_wbm_release_dir dir)265*5113495bSYour Name hal_wbm2sw_release_source_get(void *hal_desc, enum hal_be_wbm_release_dir dir)
266*5113495bSYour Name {
267*5113495bSYour Name return HAL_WBM2SW_RELEASE_SRC_GET(hal_desc);
268*5113495bSYour Name }
269*5113495bSYour Name #endif
270*5113495bSYour Name
hal_tx_comp_get_buffer_source_generic_be(void * hal_desc)271*5113495bSYour Name uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc)
272*5113495bSYour Name {
273*5113495bSYour Name return hal_wbm2sw_release_source_get(hal_desc,
274*5113495bSYour Name HAL_BE_WBM_RELEASE_DIR_TX);
275*5113495bSYour Name }
276*5113495bSYour Name
277*5113495bSYour Name /**
278*5113495bSYour Name * hal_tx_comp_get_release_reason_generic_be() - TQM Release reason
279*5113495bSYour Name * @hal_desc: completion ring descriptor pointer
280*5113495bSYour Name *
281*5113495bSYour Name * This function will return the type of pointer - buffer or descriptor
282*5113495bSYour Name *
283*5113495bSYour Name * Return: buffer type
284*5113495bSYour Name */
hal_tx_comp_get_release_reason_generic_be(void * hal_desc)285*5113495bSYour Name static uint8_t hal_tx_comp_get_release_reason_generic_be(void *hal_desc)
286*5113495bSYour Name {
287*5113495bSYour Name uint32_t comp_desc = *(uint32_t *)(((uint8_t *)hal_desc) +
288*5113495bSYour Name WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET);
289*5113495bSYour Name
290*5113495bSYour Name return (comp_desc &
291*5113495bSYour Name WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK) >>
292*5113495bSYour Name WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB;
293*5113495bSYour Name }
294*5113495bSYour Name
295*5113495bSYour Name /**
296*5113495bSYour Name * hal_get_wbm_internal_error_generic_be() - is WBM internal error
297*5113495bSYour Name * @hal_desc: completion ring descriptor pointer
298*5113495bSYour Name *
299*5113495bSYour Name * This function will return 0 or 1 - is it WBM internal error or not
300*5113495bSYour Name *
301*5113495bSYour Name * Return: uint8_t
302*5113495bSYour Name */
hal_get_wbm_internal_error_generic_be(void * hal_desc)303*5113495bSYour Name static uint8_t hal_get_wbm_internal_error_generic_be(void *hal_desc)
304*5113495bSYour Name {
305*5113495bSYour Name /*
306*5113495bSYour Name * TODO - This func is called by tx comp and wbm error handler
307*5113495bSYour Name * Check if one needs to use WBM2SW-TX and other WBM2SW-RX
308*5113495bSYour Name */
309*5113495bSYour Name uint32_t comp_desc =
310*5113495bSYour Name *(uint32_t *)(((uint8_t *)hal_desc) +
311*5113495bSYour Name HAL_WBM_INTERNAL_ERROR_OFFSET);
312*5113495bSYour Name
313*5113495bSYour Name return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >>
314*5113495bSYour Name HAL_WBM_INTERNAL_ERROR_LSB;
315*5113495bSYour Name }
316*5113495bSYour Name
317*5113495bSYour Name /**
318*5113495bSYour Name * hal_rx_wbm_err_src_get_be() - Get WBM error source from descriptor
319*5113495bSYour Name * @ring_desc: ring descriptor
320*5113495bSYour Name *
321*5113495bSYour Name * Return: wbm error source
322*5113495bSYour Name */
hal_rx_wbm_err_src_get_be(hal_ring_desc_t ring_desc)323*5113495bSYour Name static uint32_t hal_rx_wbm_err_src_get_be(hal_ring_desc_t ring_desc)
324*5113495bSYour Name {
325*5113495bSYour Name return hal_wbm2sw_release_source_get(ring_desc,
326*5113495bSYour Name HAL_BE_WBM_RELEASE_DIR_RX);
327*5113495bSYour Name }
328*5113495bSYour Name
hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc)329*5113495bSYour Name uint8_t hal_rx_ret_buf_manager_get_be(hal_ring_desc_t ring_desc)
330*5113495bSYour Name {
331*5113495bSYour Name /*
332*5113495bSYour Name * The following macro takes buf_addr_info as argument,
333*5113495bSYour Name * but since buf_addr_info is the first field in ring_desc
334*5113495bSYour Name * Hence the following call is OK
335*5113495bSYour Name */
336*5113495bSYour Name return HAL_RX_BUF_RBM_GET(ring_desc);
337*5113495bSYour Name }
338*5113495bSYour Name
339*5113495bSYour Name #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc) (((*(((uint32_t *)wbm_desc) + \
340*5113495bSYour Name (WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET >> 2))) & \
341*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK) >> \
342*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB)
343*5113495bSYour Name
344*5113495bSYour Name #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc) (((*(((uint32_t *)wbm_desc) + \
345*5113495bSYour Name (WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET >> 2))) & \
346*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK) >> \
347*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB)
348*5113495bSYour Name
349*5113495bSYour Name #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc) \
350*5113495bSYour Name (((*(((uint32_t *)wbm_desc) + \
351*5113495bSYour Name (WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET >> 2))) & \
352*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK) >> \
353*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB)
354*5113495bSYour Name
355*5113495bSYour Name #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc) \
356*5113495bSYour Name (((*(((uint32_t *)wbm_desc) + \
357*5113495bSYour Name (WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET >> 2))) & \
358*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK) >> \
359*5113495bSYour Name WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB)
360*5113495bSYour Name
hal_rx_wbm_err_info_get_generic_be(void * wbm_desc,void * wbm_er_info1)361*5113495bSYour Name void hal_rx_wbm_err_info_get_generic_be(void *wbm_desc, void *wbm_er_info1)
362*5113495bSYour Name {
363*5113495bSYour Name struct hal_wbm_err_desc_info *wbm_er_info =
364*5113495bSYour Name (struct hal_wbm_err_desc_info *)wbm_er_info1;
365*5113495bSYour Name
366*5113495bSYour Name wbm_er_info->wbm_err_src = hal_rx_wbm_err_src_get_be(wbm_desc);
367*5113495bSYour Name wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc);
368*5113495bSYour Name wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc);
369*5113495bSYour Name wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc);
370*5113495bSYour Name wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc);
371*5113495bSYour Name }
372*5113495bSYour Name
hal_rx_reo_buf_paddr_get_be(hal_ring_desc_t rx_desc,struct hal_buf_info * buf_info)373*5113495bSYour Name static void hal_rx_reo_buf_paddr_get_be(hal_ring_desc_t rx_desc,
374*5113495bSYour Name struct hal_buf_info *buf_info)
375*5113495bSYour Name {
376*5113495bSYour Name struct reo_destination_ring *reo_ring =
377*5113495bSYour Name (struct reo_destination_ring *)rx_desc;
378*5113495bSYour Name
379*5113495bSYour Name buf_info->paddr =
380*5113495bSYour Name (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
381*5113495bSYour Name ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
382*5113495bSYour Name buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
383*5113495bSYour Name }
384*5113495bSYour Name
hal_rx_msdu_link_desc_set_be(hal_soc_handle_t hal_soc_hdl,void * src_srng_desc,hal_buff_addrinfo_t buf_addr_info,uint8_t bm_action)385*5113495bSYour Name static void hal_rx_msdu_link_desc_set_be(hal_soc_handle_t hal_soc_hdl,
386*5113495bSYour Name void *src_srng_desc,
387*5113495bSYour Name hal_buff_addrinfo_t buf_addr_info,
388*5113495bSYour Name uint8_t bm_action)
389*5113495bSYour Name {
390*5113495bSYour Name /*
391*5113495bSYour Name * The offsets for fields used in this function are same in
392*5113495bSYour Name * wbm_release_ring for Lithium and wbm_release_ring_tx
393*5113495bSYour Name * for Beryllium. hence we can use wbm_release_ring directly.
394*5113495bSYour Name */
395*5113495bSYour Name struct wbm_release_ring *wbm_rel_srng =
396*5113495bSYour Name (struct wbm_release_ring *)src_srng_desc;
397*5113495bSYour Name uint32_t addr_31_0;
398*5113495bSYour Name uint8_t addr_39_32;
399*5113495bSYour Name
400*5113495bSYour Name /* Structure copy !!! */
401*5113495bSYour Name wbm_rel_srng->released_buff_or_desc_addr_info =
402*5113495bSYour Name *((struct buffer_addr_info *)buf_addr_info);
403*5113495bSYour Name
404*5113495bSYour Name addr_31_0 =
405*5113495bSYour Name wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
406*5113495bSYour Name addr_39_32 =
407*5113495bSYour Name wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
408*5113495bSYour Name
409*5113495bSYour Name HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
410*5113495bSYour Name RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
411*5113495bSYour Name HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION,
412*5113495bSYour Name bm_action);
413*5113495bSYour Name HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING,
414*5113495bSYour Name BUFFER_OR_DESC_TYPE,
415*5113495bSYour Name HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
416*5113495bSYour Name
417*5113495bSYour Name /* WBM error is indicated when any of the link descriptors given to
418*5113495bSYour Name * WBM has a NULL address, and one those paths is the link descriptors
419*5113495bSYour Name * released from host after processing RXDMA errors,
420*5113495bSYour Name * or from Rx defrag path, and we want to add an assert here to ensure
421*5113495bSYour Name * host is not releasing descriptors with NULL address.
422*5113495bSYour Name */
423*5113495bSYour Name
424*5113495bSYour Name if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
425*5113495bSYour Name hal_dump_wbm_rel_desc(src_srng_desc);
426*5113495bSYour Name qdf_assert_always(0);
427*5113495bSYour Name }
428*5113495bSYour Name }
429*5113495bSYour Name
430*5113495bSYour Name /**
431*5113495bSYour Name * hal_rx_buf_cookie_rbm_get_be() - Get the cookie and return buffer
432*5113495bSYour Name * manager from the REO entrance ring desc
433*5113495bSYour Name * @buf_addr_info_hdl: Buffer address info element from ring desc
434*5113495bSYour Name * @buf_info_hdl: structure to return the buffer information
435*5113495bSYour Name *
436*5113495bSYour Name * Return: void
437*5113495bSYour Name */
438*5113495bSYour Name static
hal_rx_buf_cookie_rbm_get_be(uint32_t * buf_addr_info_hdl,hal_buf_info_t buf_info_hdl)439*5113495bSYour Name void hal_rx_buf_cookie_rbm_get_be(uint32_t *buf_addr_info_hdl,
440*5113495bSYour Name hal_buf_info_t buf_info_hdl)
441*5113495bSYour Name {
442*5113495bSYour Name struct hal_buf_info *buf_info =
443*5113495bSYour Name (struct hal_buf_info *)buf_info_hdl;
444*5113495bSYour Name struct buffer_addr_info *buf_addr_info =
445*5113495bSYour Name (struct buffer_addr_info *)buf_addr_info_hdl;
446*5113495bSYour Name
447*5113495bSYour Name buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
448*5113495bSYour Name /*
449*5113495bSYour Name * buffer addr info is the first member of ring desc, so the typecast
450*5113495bSYour Name * can be done.
451*5113495bSYour Name */
452*5113495bSYour Name buf_info->rbm = hal_rx_ret_buf_manager_get_be(
453*5113495bSYour Name (hal_ring_desc_t)buf_addr_info);
454*5113495bSYour Name }
455*5113495bSYour Name
456*5113495bSYour Name /**
457*5113495bSYour Name * hal_rx_en_mcast_fp_data_filter_generic_be() - Is mcast filter pass enabled
458*5113495bSYour Name *
459*5113495bSYour Name * Return: true default for BE WIN
460*5113495bSYour Name */
461*5113495bSYour Name static inline
hal_rx_en_mcast_fp_data_filter_generic_be(void)462*5113495bSYour Name bool hal_rx_en_mcast_fp_data_filter_generic_be(void)
463*5113495bSYour Name {
464*5113495bSYour Name return true;
465*5113495bSYour Name }
466*5113495bSYour Name
467*5113495bSYour Name /**
468*5113495bSYour Name * hal_rxdma_buff_addr_info_set_be() - set the buffer_addr_info of the
469*5113495bSYour Name * rxdma ring entry.
470*5113495bSYour Name * @rxdma_entry: descriptor entry
471*5113495bSYour Name * @paddr: physical address of nbuf data pointer.
472*5113495bSYour Name * @cookie: SW cookie used as a index to SW rx desc.
473*5113495bSYour Name * @manager: who owns the nbuf (host, NSS, etc...).
474*5113495bSYour Name *
475*5113495bSYour Name */
476*5113495bSYour Name static inline void
hal_rxdma_buff_addr_info_set_be(void * rxdma_entry,qdf_dma_addr_t paddr,uint32_t cookie,uint8_t manager)477*5113495bSYour Name hal_rxdma_buff_addr_info_set_be(void *rxdma_entry,
478*5113495bSYour Name qdf_dma_addr_t paddr, uint32_t cookie,
479*5113495bSYour Name uint8_t manager)
480*5113495bSYour Name {
481*5113495bSYour Name uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
482*5113495bSYour Name uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
483*5113495bSYour Name
484*5113495bSYour Name HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
485*5113495bSYour Name HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
486*5113495bSYour Name HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
487*5113495bSYour Name HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
488*5113495bSYour Name }
489*5113495bSYour Name
490*5113495bSYour Name /**
491*5113495bSYour Name * hal_rx_get_reo_error_code_be() - Get REO error code from ring desc
492*5113495bSYour Name * @rx_desc: rx descriptor
493*5113495bSYour Name *
494*5113495bSYour Name * Return: REO error code
495*5113495bSYour Name */
hal_rx_get_reo_error_code_be(hal_ring_desc_t rx_desc)496*5113495bSYour Name static uint32_t hal_rx_get_reo_error_code_be(hal_ring_desc_t rx_desc)
497*5113495bSYour Name {
498*5113495bSYour Name struct reo_destination_ring *reo_desc =
499*5113495bSYour Name (struct reo_destination_ring *)rx_desc;
500*5113495bSYour Name
501*5113495bSYour Name return HAL_RX_REO_ERROR_GET(reo_desc);
502*5113495bSYour Name }
503*5113495bSYour Name
504*5113495bSYour Name /**
505*5113495bSYour Name * hal_gen_reo_remap_val_generic_be() - Generate the reo map value
506*5113495bSYour Name * @remap_reg: remap register
507*5113495bSYour Name * @ix0_map: mapping values for reo
508*5113495bSYour Name *
509*5113495bSYour Name * Return: IX0 reo remap register value to be written
510*5113495bSYour Name */
511*5113495bSYour Name static uint32_t
hal_gen_reo_remap_val_generic_be(enum hal_reo_remap_reg remap_reg,uint8_t * ix0_map)512*5113495bSYour Name hal_gen_reo_remap_val_generic_be(enum hal_reo_remap_reg remap_reg,
513*5113495bSYour Name uint8_t *ix0_map)
514*5113495bSYour Name {
515*5113495bSYour Name uint32_t ix_val = 0;
516*5113495bSYour Name
517*5113495bSYour Name switch (remap_reg) {
518*5113495bSYour Name case HAL_REO_REMAP_REG_IX0:
519*5113495bSYour Name ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) |
520*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[1], 1) |
521*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[2], 2) |
522*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[3], 3) |
523*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[4], 4) |
524*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[5], 5) |
525*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[6], 6) |
526*5113495bSYour Name HAL_REO_REMAP_IX0(ix0_map[7], 7);
527*5113495bSYour Name break;
528*5113495bSYour Name case HAL_REO_REMAP_REG_IX2:
529*5113495bSYour Name ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) |
530*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[1], 17) |
531*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[2], 18) |
532*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[3], 19) |
533*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[4], 20) |
534*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[5], 21) |
535*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[6], 22) |
536*5113495bSYour Name HAL_REO_REMAP_IX2(ix0_map[7], 23);
537*5113495bSYour Name break;
538*5113495bSYour Name default:
539*5113495bSYour Name break;
540*5113495bSYour Name }
541*5113495bSYour Name
542*5113495bSYour Name return ix_val;
543*5113495bSYour Name }
544*5113495bSYour Name
hal_rx_err_status_get_be(hal_ring_desc_t rx_desc)545*5113495bSYour Name static uint8_t hal_rx_err_status_get_be(hal_ring_desc_t rx_desc)
546*5113495bSYour Name {
547*5113495bSYour Name return HAL_RX_ERROR_STATUS_GET(rx_desc);
548*5113495bSYour Name }
549*5113495bSYour Name
hal_reo_status_update_be(hal_soc_handle_t hal_soc_hdl,hal_ring_desc_t reo_desc,void * st_handle,uint32_t tlv,int * num_ref)550*5113495bSYour Name static QDF_STATUS hal_reo_status_update_be(hal_soc_handle_t hal_soc_hdl,
551*5113495bSYour Name hal_ring_desc_t reo_desc,
552*5113495bSYour Name void *st_handle,
553*5113495bSYour Name uint32_t tlv, int *num_ref)
554*5113495bSYour Name {
555*5113495bSYour Name union hal_reo_status *reo_status_ref;
556*5113495bSYour Name
557*5113495bSYour Name reo_status_ref = (union hal_reo_status *)st_handle;
558*5113495bSYour Name
559*5113495bSYour Name switch (tlv) {
560*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
561*5113495bSYour Name hal_reo_queue_stats_status_be(reo_desc,
562*5113495bSYour Name &reo_status_ref->queue_status,
563*5113495bSYour Name hal_soc_hdl);
564*5113495bSYour Name *num_ref = reo_status_ref->queue_status.header.cmd_num;
565*5113495bSYour Name break;
566*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
567*5113495bSYour Name hal_reo_flush_queue_status_be(reo_desc,
568*5113495bSYour Name &reo_status_ref->fl_queue_status,
569*5113495bSYour Name hal_soc_hdl);
570*5113495bSYour Name *num_ref = reo_status_ref->fl_queue_status.header.cmd_num;
571*5113495bSYour Name break;
572*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
573*5113495bSYour Name hal_reo_flush_cache_status_be(reo_desc,
574*5113495bSYour Name &reo_status_ref->fl_cache_status,
575*5113495bSYour Name hal_soc_hdl);
576*5113495bSYour Name *num_ref = reo_status_ref->fl_cache_status.header.cmd_num;
577*5113495bSYour Name break;
578*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
579*5113495bSYour Name hal_reo_unblock_cache_status_be
580*5113495bSYour Name (reo_desc, hal_soc_hdl,
581*5113495bSYour Name &reo_status_ref->unblk_cache_status);
582*5113495bSYour Name *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num;
583*5113495bSYour Name break;
584*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
585*5113495bSYour Name hal_reo_flush_timeout_list_status_be(
586*5113495bSYour Name reo_desc,
587*5113495bSYour Name &reo_status_ref->fl_timeout_status,
588*5113495bSYour Name hal_soc_hdl);
589*5113495bSYour Name *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num;
590*5113495bSYour Name break;
591*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
592*5113495bSYour Name hal_reo_desc_thres_reached_status_be(
593*5113495bSYour Name reo_desc,
594*5113495bSYour Name &reo_status_ref->thres_status,
595*5113495bSYour Name hal_soc_hdl);
596*5113495bSYour Name *num_ref = reo_status_ref->thres_status.header.cmd_num;
597*5113495bSYour Name break;
598*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
599*5113495bSYour Name hal_reo_rx_update_queue_status_be(
600*5113495bSYour Name reo_desc,
601*5113495bSYour Name &reo_status_ref->rx_queue_status,
602*5113495bSYour Name hal_soc_hdl);
603*5113495bSYour Name *num_ref = reo_status_ref->rx_queue_status.header.cmd_num;
604*5113495bSYour Name break;
605*5113495bSYour Name default:
606*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN,
607*5113495bSYour Name "hal_soc %pK: no handler for TLV:%d",
608*5113495bSYour Name hal_soc_hdl, tlv);
609*5113495bSYour Name return QDF_STATUS_E_FAILURE;
610*5113495bSYour Name } /* switch */
611*5113495bSYour Name
612*5113495bSYour Name return QDF_STATUS_SUCCESS;
613*5113495bSYour Name }
614*5113495bSYour Name
hal_rx_reo_buf_type_get_be(hal_ring_desc_t rx_desc)615*5113495bSYour Name static uint8_t hal_rx_reo_buf_type_get_be(hal_ring_desc_t rx_desc)
616*5113495bSYour Name {
617*5113495bSYour Name return HAL_RX_REO_BUF_TYPE_GET(rx_desc);
618*5113495bSYour Name }
619*5113495bSYour Name
620*5113495bSYour Name #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
621*5113495bSYour Name #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
622*5113495bSYour Name #endif
hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,struct hal_hw_cc_config * cc_cfg)623*5113495bSYour Name void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
624*5113495bSYour Name struct hal_hw_cc_config *cc_cfg)
625*5113495bSYour Name {
626*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
627*5113495bSYour Name
628*5113495bSYour Name hal_soc->ops->hal_cookie_conversion_reg_cfg_be(hal_soc_hdl, cc_cfg);
629*5113495bSYour Name }
630*5113495bSYour Name qdf_export_symbol(hal_cookie_conversion_reg_cfg_be);
631*5113495bSYour Name
632*5113495bSYour Name static inline void
hal_msdu_desc_info_set_be(hal_soc_handle_t hal_soc_hdl,void * msdu_desc,uint32_t dst_ind,uint32_t nbuf_len)633*5113495bSYour Name hal_msdu_desc_info_set_be(hal_soc_handle_t hal_soc_hdl,
634*5113495bSYour Name void *msdu_desc, uint32_t dst_ind,
635*5113495bSYour Name uint32_t nbuf_len)
636*5113495bSYour Name {
637*5113495bSYour Name struct rx_msdu_desc_info *msdu_desc_info =
638*5113495bSYour Name (struct rx_msdu_desc_info *)msdu_desc;
639*5113495bSYour Name struct rx_msdu_ext_desc_info *msdu_ext_desc_info =
640*5113495bSYour Name (struct rx_msdu_ext_desc_info *)(msdu_desc_info + 1);
641*5113495bSYour Name
642*5113495bSYour Name HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
643*5113495bSYour Name FIRST_MSDU_IN_MPDU_FLAG, 1);
644*5113495bSYour Name HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
645*5113495bSYour Name LAST_MSDU_IN_MPDU_FLAG, 1);
646*5113495bSYour Name HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
647*5113495bSYour Name MSDU_CONTINUATION, 0x0);
648*5113495bSYour Name HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
649*5113495bSYour Name MSDU_LENGTH, nbuf_len);
650*5113495bSYour Name HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
651*5113495bSYour Name SA_IS_VALID, 1);
652*5113495bSYour Name HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info,
653*5113495bSYour Name DA_IS_VALID, 1);
654*5113495bSYour Name HAL_RX_MSDU_REO_DST_IND_SET(msdu_ext_desc_info,
655*5113495bSYour Name REO_DESTINATION_INDICATION, dst_ind);
656*5113495bSYour Name }
657*5113495bSYour Name
658*5113495bSYour Name static inline void
hal_mpdu_desc_info_set_be(hal_soc_handle_t hal_soc_hdl,void * ent_desc,void * mpdu_desc,uint32_t seq_no)659*5113495bSYour Name hal_mpdu_desc_info_set_be(hal_soc_handle_t hal_soc_hdl,
660*5113495bSYour Name void *ent_desc,
661*5113495bSYour Name void *mpdu_desc,
662*5113495bSYour Name uint32_t seq_no)
663*5113495bSYour Name {
664*5113495bSYour Name struct rx_mpdu_desc_info *mpdu_desc_info =
665*5113495bSYour Name (struct rx_mpdu_desc_info *)mpdu_desc;
666*5113495bSYour Name uint8_t *desc = (uint8_t *)ent_desc;
667*5113495bSYour Name
668*5113495bSYour Name HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING,
669*5113495bSYour Name MPDU_SEQUENCE_NUMBER, seq_no);
670*5113495bSYour Name
671*5113495bSYour Name HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
672*5113495bSYour Name MSDU_COUNT, 0x1);
673*5113495bSYour Name HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
674*5113495bSYour Name FRAGMENT_FLAG, 0x1);
675*5113495bSYour Name HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info,
676*5113495bSYour Name RAW_MPDU, 0x0);
677*5113495bSYour Name }
678*5113495bSYour Name
679*5113495bSYour Name /**
680*5113495bSYour Name * hal_rx_msdu_reo_dst_ind_get_be() - Gets the REO destination ring ID
681*5113495bSYour Name * from the msdu desc info
682*5113495bSYour Name * @hal_soc_hdl: hal_soc handle
683*5113495bSYour Name * @msdu_link_desc : Opaque cookie pointer used by HAL to get to
684*5113495bSYour Name * the current descriptor
685*5113495bSYour Name *
686*5113495bSYour Name * Return: dst_ind (REO destination ring ID)
687*5113495bSYour Name */
688*5113495bSYour Name static inline
hal_rx_msdu_reo_dst_ind_get_be(hal_soc_handle_t hal_soc_hdl,void * msdu_link_desc)689*5113495bSYour Name uint32_t hal_rx_msdu_reo_dst_ind_get_be(hal_soc_handle_t hal_soc_hdl,
690*5113495bSYour Name void *msdu_link_desc)
691*5113495bSYour Name {
692*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
693*5113495bSYour Name struct rx_msdu_details *msdu_details;
694*5113495bSYour Name struct rx_msdu_desc_info *msdu_desc_info;
695*5113495bSYour Name struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
696*5113495bSYour Name uint32_t dst_ind;
697*5113495bSYour Name
698*5113495bSYour Name msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
699*5113495bSYour Name
700*5113495bSYour Name /* The first msdu in the link should exist */
701*5113495bSYour Name msdu_desc_info = hal_rx_msdu_ext_desc_info_get_ptr(&msdu_details[0],
702*5113495bSYour Name hal_soc);
703*5113495bSYour Name dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
704*5113495bSYour Name return dst_ind;
705*5113495bSYour Name }
706*5113495bSYour Name
707*5113495bSYour Name uint32_t
hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl,uint8_t rx_ring_mask)708*5113495bSYour Name hal_reo_ix_remap_value_get_be(hal_soc_handle_t hal_soc_hdl,
709*5113495bSYour Name uint8_t rx_ring_mask)
710*5113495bSYour Name {
711*5113495bSYour Name uint32_t num_rings = 0;
712*5113495bSYour Name uint32_t i = 0;
713*5113495bSYour Name uint32_t ring_remap_arr[HAL_MAX_REO2SW_RINGS] = {0};
714*5113495bSYour Name uint32_t reo_remap_val = 0;
715*5113495bSYour Name uint32_t ring_idx = 0;
716*5113495bSYour Name uint8_t ix_map[HAL_NUM_RX_RING_PER_IX_MAP] = {0};
717*5113495bSYour Name
718*5113495bSYour Name /* create reo ring remap array */
719*5113495bSYour Name while (i < HAL_MAX_REO2SW_RINGS) {
720*5113495bSYour Name if (rx_ring_mask & (1 << i)) {
721*5113495bSYour Name ring_remap_arr[num_rings] = reo_dest_ring_remap[i];
722*5113495bSYour Name num_rings++;
723*5113495bSYour Name }
724*5113495bSYour Name i++;
725*5113495bSYour Name }
726*5113495bSYour Name
727*5113495bSYour Name for (i = 0; i < HAL_NUM_RX_RING_PER_IX_MAP; i++) {
728*5113495bSYour Name if (rx_ring_mask) {
729*5113495bSYour Name ix_map[i] = ring_remap_arr[ring_idx];
730*5113495bSYour Name ring_idx = ((ring_idx + 1) % num_rings);
731*5113495bSYour Name } else {
732*5113495bSYour Name /* if ring mask is zero configure to release to WBM */
733*5113495bSYour Name ix_map[i] = REO_REMAP_RELEASE;
734*5113495bSYour Name }
735*5113495bSYour Name }
736*5113495bSYour Name
737*5113495bSYour Name reo_remap_val = HAL_REO_REMAP_IX0(ix_map[0], 0) |
738*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[1], 1) |
739*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[2], 2) |
740*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[3], 3) |
741*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[4], 4) |
742*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[5], 5) |
743*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[6], 6) |
744*5113495bSYour Name HAL_REO_REMAP_IX0(ix_map[7], 7);
745*5113495bSYour Name
746*5113495bSYour Name return reo_remap_val;
747*5113495bSYour Name }
748*5113495bSYour Name
749*5113495bSYour Name qdf_export_symbol(hal_reo_ix_remap_value_get_be);
750*5113495bSYour Name
hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id)751*5113495bSYour Name uint8_t hal_reo_ring_remap_value_get_be(uint8_t rx_ring_id)
752*5113495bSYour Name {
753*5113495bSYour Name if (rx_ring_id >= HAL_MAX_REO2SW_RINGS)
754*5113495bSYour Name return REO_REMAP_RELEASE;
755*5113495bSYour Name
756*5113495bSYour Name return reo_dest_ring_remap[rx_ring_id];
757*5113495bSYour Name }
758*5113495bSYour Name
759*5113495bSYour Name qdf_export_symbol(hal_reo_ring_remap_value_get_be);
760*5113495bSYour Name
hal_get_idle_link_bm_id_be(uint8_t chip_id)761*5113495bSYour Name uint8_t hal_get_idle_link_bm_id_be(uint8_t chip_id)
762*5113495bSYour Name {
763*5113495bSYour Name if (chip_id >= HAL_NUM_CHIPS)
764*5113495bSYour Name return HAL_WBM_CHIP_INVALID;
765*5113495bSYour Name
766*5113495bSYour Name return wbm_idle_link_bm_map[chip_id];
767*5113495bSYour Name }
768*5113495bSYour Name
769*5113495bSYour Name #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
770*5113495bSYour Name #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
771*5113495bSYour Name static inline void
hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,struct hal_buf_info * buf_info)772*5113495bSYour Name hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,
773*5113495bSYour Name struct hal_buf_info *buf_info)
774*5113495bSYour Name {
775*5113495bSYour Name if (hal_rx_wbm_get_cookie_convert_done(rx_desc))
776*5113495bSYour Name buf_info->paddr =
777*5113495bSYour Name (HAL_RX_WBM_COMP_BUF_ADDR_31_0_GET(rx_desc) |
778*5113495bSYour Name ((uint64_t)(HAL_RX_WBM_COMP_BUF_ADDR_39_32_GET(rx_desc)) << 32));
779*5113495bSYour Name else
780*5113495bSYour Name buf_info->paddr =
781*5113495bSYour Name (HAL_RX_WBM_BUF_ADDR_31_0_GET(rx_desc) |
782*5113495bSYour Name ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(rx_desc)) << 32));
783*5113495bSYour Name }
784*5113495bSYour Name #else
785*5113495bSYour Name static inline void
hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,struct hal_buf_info * buf_info)786*5113495bSYour Name hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,
787*5113495bSYour Name struct hal_buf_info *buf_info)
788*5113495bSYour Name {
789*5113495bSYour Name buf_info->paddr =
790*5113495bSYour Name (HAL_RX_WBM_COMP_BUF_ADDR_31_0_GET(rx_desc) |
791*5113495bSYour Name ((uint64_t)(HAL_RX_WBM_COMP_BUF_ADDR_39_32_GET(rx_desc)) << 32));
792*5113495bSYour Name }
793*5113495bSYour Name #endif
794*5113495bSYour Name #else /* !DP_FEATURE_HW_COOKIE_CONVERSION */
795*5113495bSYour Name static inline void
hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,struct hal_buf_info * buf_info)796*5113495bSYour Name hal_rx_wbm_rel_buf_paddr_get_be(hal_ring_desc_t rx_desc,
797*5113495bSYour Name struct hal_buf_info *buf_info)
798*5113495bSYour Name {
799*5113495bSYour Name buf_info->paddr =
800*5113495bSYour Name (HAL_RX_WBM_BUF_ADDR_31_0_GET(rx_desc) |
801*5113495bSYour Name ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(rx_desc)) << 32));
802*5113495bSYour Name }
803*5113495bSYour Name #endif
804*5113495bSYour Name
805*5113495bSYour Name #ifdef DP_UMAC_HW_RESET_SUPPORT
806*5113495bSYour Name /**
807*5113495bSYour Name * hal_unregister_reo_send_cmd_be() - Unregister Reo send command callback.
808*5113495bSYour Name * @hal_soc: HAL soc handle
809*5113495bSYour Name *
810*5113495bSYour Name * Return: None
811*5113495bSYour Name */
812*5113495bSYour Name static
hal_unregister_reo_send_cmd_be(struct hal_soc * hal_soc)813*5113495bSYour Name void hal_unregister_reo_send_cmd_be(struct hal_soc *hal_soc)
814*5113495bSYour Name {
815*5113495bSYour Name hal_soc->ops->hal_reo_send_cmd = NULL;
816*5113495bSYour Name }
817*5113495bSYour Name
818*5113495bSYour Name /**
819*5113495bSYour Name * hal_register_reo_send_cmd_be() - Register Reo send command callback.
820*5113495bSYour Name * @hal_soc: HAL soc handle
821*5113495bSYour Name *
822*5113495bSYour Name * Return: None
823*5113495bSYour Name */
824*5113495bSYour Name static
hal_register_reo_send_cmd_be(struct hal_soc * hal_soc)825*5113495bSYour Name void hal_register_reo_send_cmd_be(struct hal_soc *hal_soc)
826*5113495bSYour Name {
827*5113495bSYour Name hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_be;
828*5113495bSYour Name }
829*5113495bSYour Name
830*5113495bSYour Name /**
831*5113495bSYour Name * hal_reset_rx_reo_tid_q_be() - reset the reo tid queue.
832*5113495bSYour Name * @hal_soc: HAL soc handle
833*5113495bSYour Name * @hw_qdesc_vaddr: start address of the tid queue
834*5113495bSYour Name * @size: size of address pointed by hw_qdesc_vaddr
835*5113495bSYour Name *
836*5113495bSYour Name * Return: None
837*5113495bSYour Name */
838*5113495bSYour Name static void
hal_reset_rx_reo_tid_q_be(struct hal_soc * hal_soc,void * hw_qdesc_vaddr,uint32_t size)839*5113495bSYour Name hal_reset_rx_reo_tid_q_be(struct hal_soc *hal_soc, void *hw_qdesc_vaddr,
840*5113495bSYour Name uint32_t size)
841*5113495bSYour Name {
842*5113495bSYour Name struct rx_reo_queue *hw_qdesc = (struct rx_reo_queue *)hw_qdesc_vaddr;
843*5113495bSYour Name int i;
844*5113495bSYour Name
845*5113495bSYour Name if (!hw_qdesc)
846*5113495bSYour Name return;
847*5113495bSYour Name
848*5113495bSYour Name hw_qdesc->svld = 0;
849*5113495bSYour Name hw_qdesc->ssn = 0;
850*5113495bSYour Name hw_qdesc->current_index = 0;
851*5113495bSYour Name hw_qdesc->pn_valid = 0;
852*5113495bSYour Name hw_qdesc->pn_31_0 = 0;
853*5113495bSYour Name hw_qdesc->pn_63_32 = 0;
854*5113495bSYour Name hw_qdesc->pn_95_64 = 0;
855*5113495bSYour Name hw_qdesc->pn_127_96 = 0;
856*5113495bSYour Name hw_qdesc->last_rx_enqueue_timestamp = 0;
857*5113495bSYour Name hw_qdesc->last_rx_dequeue_timestamp = 0;
858*5113495bSYour Name hw_qdesc->ptr_to_next_aging_queue_39_32 = 0;
859*5113495bSYour Name hw_qdesc->ptr_to_next_aging_queue_31_0 = 0;
860*5113495bSYour Name hw_qdesc->ptr_to_previous_aging_queue_31_0 = 0;
861*5113495bSYour Name hw_qdesc->ptr_to_previous_aging_queue_39_32 = 0;
862*5113495bSYour Name hw_qdesc->rx_bitmap_31_0 = 0;
863*5113495bSYour Name hw_qdesc->rx_bitmap_63_32 = 0;
864*5113495bSYour Name hw_qdesc->rx_bitmap_95_64 = 0;
865*5113495bSYour Name hw_qdesc->rx_bitmap_127_96 = 0;
866*5113495bSYour Name hw_qdesc->rx_bitmap_159_128 = 0;
867*5113495bSYour Name hw_qdesc->rx_bitmap_191_160 = 0;
868*5113495bSYour Name hw_qdesc->rx_bitmap_223_192 = 0;
869*5113495bSYour Name hw_qdesc->rx_bitmap_255_224 = 0;
870*5113495bSYour Name hw_qdesc->rx_bitmap_287_256 = 0;
871*5113495bSYour Name hw_qdesc->current_msdu_count = 0;
872*5113495bSYour Name hw_qdesc->current_mpdu_count = 0;
873*5113495bSYour Name hw_qdesc->last_sn_reg_index = 0;
874*5113495bSYour Name
875*5113495bSYour Name if (size > sizeof(struct rx_reo_queue)) {
876*5113495bSYour Name struct rx_reo_queue_ext *ext_desc;
877*5113495bSYour Name struct rx_reo_queue_1k *kdesc;
878*5113495bSYour Name
879*5113495bSYour Name i = ((size - sizeof(struct rx_reo_queue)) /
880*5113495bSYour Name sizeof(struct rx_reo_queue_ext));
881*5113495bSYour Name
882*5113495bSYour Name if (i > 10) {
883*5113495bSYour Name i = 10;
884*5113495bSYour Name kdesc = (struct rx_reo_queue_1k *)
885*5113495bSYour Name (hw_qdesc_vaddr + sizeof(struct rx_reo_queue) +
886*5113495bSYour Name (10 * sizeof(struct rx_reo_queue_ext)));
887*5113495bSYour Name
888*5113495bSYour Name kdesc->rx_bitmap_319_288 = 0;
889*5113495bSYour Name kdesc->rx_bitmap_351_320 = 0;
890*5113495bSYour Name kdesc->rx_bitmap_383_352 = 0;
891*5113495bSYour Name kdesc->rx_bitmap_415_384 = 0;
892*5113495bSYour Name kdesc->rx_bitmap_447_416 = 0;
893*5113495bSYour Name kdesc->rx_bitmap_479_448 = 0;
894*5113495bSYour Name kdesc->rx_bitmap_511_480 = 0;
895*5113495bSYour Name kdesc->rx_bitmap_543_512 = 0;
896*5113495bSYour Name kdesc->rx_bitmap_575_544 = 0;
897*5113495bSYour Name kdesc->rx_bitmap_607_576 = 0;
898*5113495bSYour Name kdesc->rx_bitmap_639_608 = 0;
899*5113495bSYour Name kdesc->rx_bitmap_671_640 = 0;
900*5113495bSYour Name kdesc->rx_bitmap_703_672 = 0;
901*5113495bSYour Name kdesc->rx_bitmap_735_704 = 0;
902*5113495bSYour Name kdesc->rx_bitmap_767_736 = 0;
903*5113495bSYour Name kdesc->rx_bitmap_799_768 = 0;
904*5113495bSYour Name kdesc->rx_bitmap_831_800 = 0;
905*5113495bSYour Name kdesc->rx_bitmap_863_832 = 0;
906*5113495bSYour Name kdesc->rx_bitmap_895_864 = 0;
907*5113495bSYour Name kdesc->rx_bitmap_927_896 = 0;
908*5113495bSYour Name kdesc->rx_bitmap_959_928 = 0;
909*5113495bSYour Name kdesc->rx_bitmap_991_960 = 0;
910*5113495bSYour Name kdesc->rx_bitmap_1023_992 = 0;
911*5113495bSYour Name }
912*5113495bSYour Name
913*5113495bSYour Name ext_desc = (struct rx_reo_queue_ext *)
914*5113495bSYour Name (hw_qdesc_vaddr + (sizeof(struct rx_reo_queue)));
915*5113495bSYour Name
916*5113495bSYour Name while (i > 0) {
917*5113495bSYour Name qdf_mem_zero(&ext_desc->mpdu_link_pointer_0,
918*5113495bSYour Name (15 * sizeof(struct rx_mpdu_link_ptr)));
919*5113495bSYour Name
920*5113495bSYour Name ext_desc++;
921*5113495bSYour Name i--;
922*5113495bSYour Name }
923*5113495bSYour Name }
924*5113495bSYour Name }
925*5113495bSYour Name #endif
926*5113495bSYour Name
hal_rx_get_phy_ppdu_id_size_be(void)927*5113495bSYour Name static inline uint8_t hal_rx_get_phy_ppdu_id_size_be(void)
928*5113495bSYour Name {
929*5113495bSYour Name return sizeof(uint64_t);
930*5113495bSYour Name }
931*5113495bSYour Name
hal_hw_txrx_default_ops_attach_be(struct hal_soc * hal_soc)932*5113495bSYour Name void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
933*5113495bSYour Name {
934*5113495bSYour Name hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_be;
935*5113495bSYour Name hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_be;
936*5113495bSYour Name hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_be;
937*5113495bSYour Name hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_be;
938*5113495bSYour Name hal_soc->ops->hal_get_reo_reg_base_offset =
939*5113495bSYour Name hal_get_reo_reg_base_offset_be;
940*5113495bSYour Name hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_be;
941*5113495bSYour Name hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_be;
942*5113495bSYour Name hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_be;
943*5113495bSYour Name hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_be;
944*5113495bSYour Name
945*5113495bSYour Name hal_soc->ops->hal_rx_ret_buf_manager_get =
946*5113495bSYour Name hal_rx_ret_buf_manager_get_be;
947*5113495bSYour Name hal_soc->ops->hal_rxdma_buff_addr_info_set =
948*5113495bSYour Name hal_rxdma_buff_addr_info_set_be;
949*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_be;
950*5113495bSYour Name hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_be;
951*5113495bSYour Name hal_soc->ops->hal_gen_reo_remap_val =
952*5113495bSYour Name hal_gen_reo_remap_val_generic_be;
953*5113495bSYour Name hal_soc->ops->hal_tx_comp_get_buffer_source =
954*5113495bSYour Name hal_tx_comp_get_buffer_source_generic_be;
955*5113495bSYour Name hal_soc->ops->hal_tx_comp_get_release_reason =
956*5113495bSYour Name hal_tx_comp_get_release_reason_generic_be;
957*5113495bSYour Name hal_soc->ops->hal_get_wbm_internal_error =
958*5113495bSYour Name hal_get_wbm_internal_error_generic_be;
959*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_desc_info_get =
960*5113495bSYour Name hal_rx_mpdu_desc_info_get_be;
961*5113495bSYour Name hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_be;
962*5113495bSYour Name hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_be;
963*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_be;
964*5113495bSYour Name hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get =
965*5113495bSYour Name hal_rx_wbm_rel_buf_paddr_get_be;
966*5113495bSYour Name
967*5113495bSYour Name hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_be;
968*5113495bSYour Name hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_be;
969*5113495bSYour Name hal_soc->ops->hal_reo_status_update = hal_reo_status_update_be;
970*5113495bSYour Name hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_be;
971*5113495bSYour Name hal_soc->ops->hal_rx_msdu_reo_dst_ind_get =
972*5113495bSYour Name hal_rx_msdu_reo_dst_ind_get_be;
973*5113495bSYour Name hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_be;
974*5113495bSYour Name hal_soc->ops->hal_rx_msdu_ext_desc_info_get_ptr =
975*5113495bSYour Name hal_rx_msdu_ext_desc_info_get_ptr_be;
976*5113495bSYour Name hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_be;
977*5113495bSYour Name hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_be;
978*5113495bSYour Name #ifdef DP_UMAC_HW_RESET_SUPPORT
979*5113495bSYour Name hal_soc->ops->hal_unregister_reo_send_cmd =
980*5113495bSYour Name hal_unregister_reo_send_cmd_be;
981*5113495bSYour Name hal_soc->ops->hal_register_reo_send_cmd = hal_register_reo_send_cmd_be;
982*5113495bSYour Name hal_soc->ops->hal_reset_rx_reo_tid_q = hal_reset_rx_reo_tid_q_be;
983*5113495bSYour Name #endif
984*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_be;
985*5113495bSYour Name #ifndef CONFIG_WORD_BASED_TLV
986*5113495bSYour Name hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_be;
987*5113495bSYour Name #endif
988*5113495bSYour Name hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
989*5113495bSYour Name hal_set_reo_ent_desc_reo_dest_ind_be;
990*5113495bSYour Name hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
991*5113495bSYour Name hal_get_reo_ent_desc_qdesc_addr_be;
992*5113495bSYour Name hal_soc->ops->hal_rx_en_mcast_fp_data_filter =
993*5113495bSYour Name hal_rx_en_mcast_fp_data_filter_generic_be;
994*5113495bSYour Name hal_soc->ops->hal_rx_get_phy_ppdu_id_size =
995*5113495bSYour Name hal_rx_get_phy_ppdu_id_size_be;
996*5113495bSYour Name hal_soc->ops->hal_rx_phy_legacy_get_rssi =
997*5113495bSYour Name hal_rx_phy_legacy_get_rssi_be;
998*5113495bSYour Name hal_soc->ops->hal_rx_parse_eht_sig_hdr = hal_rx_parse_eht_sig_hdr_be;
999*5113495bSYour Name }
1000