1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for
6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the
7*5113495bSYour Name * above copyright notice and this permission notice appear in all
8*5113495bSYour Name * copies.
9*5113495bSYour Name *
10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE.
18*5113495bSYour Name */
19*5113495bSYour Name
20*5113495bSYour Name #include "qdf_module.h"
21*5113495bSYour Name #include "hal_hw_headers.h"
22*5113495bSYour Name #include "hal_be_hw_headers.h"
23*5113495bSYour Name #include "hal_reo.h"
24*5113495bSYour Name #include "hal_be_reo.h"
25*5113495bSYour Name #include "hal_be_api.h"
26*5113495bSYour Name
hal_get_reo_reg_base_offset_be(void)27*5113495bSYour Name uint32_t hal_get_reo_reg_base_offset_be(void)
28*5113495bSYour Name {
29*5113495bSYour Name return REO_REG_REG_BASE;
30*5113495bSYour Name }
31*5113495bSYour Name
hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl,int tid,uint32_t ba_window_size,uint32_t start_seq,void * hw_qdesc_vaddr,qdf_dma_addr_t hw_qdesc_paddr,int pn_type,uint8_t vdev_stats_id)32*5113495bSYour Name void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, int tid,
33*5113495bSYour Name uint32_t ba_window_size,
34*5113495bSYour Name uint32_t start_seq, void *hw_qdesc_vaddr,
35*5113495bSYour Name qdf_dma_addr_t hw_qdesc_paddr,
36*5113495bSYour Name int pn_type, uint8_t vdev_stats_id)
37*5113495bSYour Name {
38*5113495bSYour Name uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
39*5113495bSYour Name uint32_t *reo_queue_ext_desc;
40*5113495bSYour Name uint32_t reg_val;
41*5113495bSYour Name uint32_t pn_enable;
42*5113495bSYour Name uint32_t pn_size = 0;
43*5113495bSYour Name
44*5113495bSYour Name qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
45*5113495bSYour Name
46*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
47*5113495bSYour Name HAL_REO_QUEUE_DESC);
48*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
49*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER,
50*5113495bSYour Name RESERVED_0A, 0xDDBEEF);
51*5113495bSYour Name
52*5113495bSYour Name /* This a just a SW meta data and will be copied to REO destination
53*5113495bSYour Name * descriptors indicated by hardware.
54*5113495bSYour Name * TODO: Setting TID in this field. See if we should set something else.
55*5113495bSYour Name */
56*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
57*5113495bSYour Name RECEIVE_QUEUE_NUMBER, tid);
58*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
59*5113495bSYour Name VLD, 1);
60*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
61*5113495bSYour Name ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
62*5113495bSYour Name HAL_RX_LINK_DESC_CNTR);
63*5113495bSYour Name
64*5113495bSYour Name /*
65*5113495bSYour Name * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
66*5113495bSYour Name */
67*5113495bSYour Name
68*5113495bSYour Name reg_val = TID_TO_WME_AC(tid);
69*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, AC, reg_val);
70*5113495bSYour Name
71*5113495bSYour Name if (ba_window_size < 1)
72*5113495bSYour Name ba_window_size = 1;
73*5113495bSYour Name
74*5113495bSYour Name /* WAR to get 2k exception in Non BA case.
75*5113495bSYour Name * Setting window size to 2 to get 2k jump exception
76*5113495bSYour Name * when we receive aggregates in Non BA case
77*5113495bSYour Name */
78*5113495bSYour Name ba_window_size = hal_update_non_ba_win_size(tid, ba_window_size);
79*5113495bSYour Name
80*5113495bSYour Name /* Set RTY bit for non-BA case. Duplicate detection is currently not
81*5113495bSYour Name * done by HW in non-BA case if RTY bit is not set.
82*5113495bSYour Name * TODO: This is a temporary War and should be removed once HW fix is
83*5113495bSYour Name * made to check and discard duplicates even if RTY bit is not set.
84*5113495bSYour Name */
85*5113495bSYour Name if (ba_window_size == 1)
86*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, RTY, 1);
87*5113495bSYour Name
88*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, BA_WINDOW_SIZE,
89*5113495bSYour Name ba_window_size - 1);
90*5113495bSYour Name
91*5113495bSYour Name switch (pn_type) {
92*5113495bSYour Name case HAL_PN_WPA:
93*5113495bSYour Name pn_enable = 1;
94*5113495bSYour Name pn_size = PN_SIZE_48;
95*5113495bSYour Name break;
96*5113495bSYour Name case HAL_PN_WAPI_EVEN:
97*5113495bSYour Name case HAL_PN_WAPI_UNEVEN:
98*5113495bSYour Name pn_enable = 1;
99*5113495bSYour Name pn_size = PN_SIZE_128;
100*5113495bSYour Name break;
101*5113495bSYour Name default:
102*5113495bSYour Name pn_enable = 0;
103*5113495bSYour Name break;
104*5113495bSYour Name }
105*5113495bSYour Name
106*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, PN_CHECK_NEEDED,
107*5113495bSYour Name pn_enable);
108*5113495bSYour Name
109*5113495bSYour Name if (pn_type == HAL_PN_WAPI_EVEN)
110*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
111*5113495bSYour Name PN_SHALL_BE_EVEN, 1);
112*5113495bSYour Name else if (pn_type == HAL_PN_WAPI_UNEVEN)
113*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
114*5113495bSYour Name PN_SHALL_BE_UNEVEN, 1);
115*5113495bSYour Name
116*5113495bSYour Name /*
117*5113495bSYour Name * TODO: Need to check if PN handling in SW needs to be enabled
118*5113495bSYour Name * So far this is not a requirement
119*5113495bSYour Name */
120*5113495bSYour Name
121*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, PN_SIZE,
122*5113495bSYour Name pn_size);
123*5113495bSYour Name
124*5113495bSYour Name /* TODO: Check if RX_REO_QUEUE_IGNORE_AMPDU_FLAG need to be set
125*5113495bSYour Name * based on BA window size and/or AMPDU capabilities
126*5113495bSYour Name */
127*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE,
128*5113495bSYour Name IGNORE_AMPDU_FLAG, 1);
129*5113495bSYour Name
130*5113495bSYour Name if (start_seq <= 0xfff)
131*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, SSN,
132*5113495bSYour Name start_seq);
133*5113495bSYour Name
134*5113495bSYour Name /* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
135*5113495bSYour Name * but REO is not delivering packets if we set it to 1. Need to enable
136*5113495bSYour Name * this once the issue is resolved
137*5113495bSYour Name */
138*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE, SVLD, 0);
139*5113495bSYour Name
140*5113495bSYour Name hal_update_stats_counter_index(reo_queue_desc, vdev_stats_id);
141*5113495bSYour Name
142*5113495bSYour Name /* TODO: Check if we should set start PN for WAPI */
143*5113495bSYour Name
144*5113495bSYour Name /* TODO: HW queue descriptors are currently allocated for max BA
145*5113495bSYour Name * window size for all QOS TIDs so that same descriptor can be used
146*5113495bSYour Name * later when ADDBA request is received. This should be changed to
147*5113495bSYour Name * allocate HW queue descriptors based on BA window size being
148*5113495bSYour Name * negotiated (0 for non BA cases), and reallocate when BA window
149*5113495bSYour Name * size changes and also send WMI message to FW to change the REO
150*5113495bSYour Name * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
151*5113495bSYour Name */
152*5113495bSYour Name if (tid == HAL_NON_QOS_TID)
153*5113495bSYour Name return;
154*5113495bSYour Name
155*5113495bSYour Name reo_queue_ext_desc = (uint32_t *)
156*5113495bSYour Name (((struct rx_reo_queue *)reo_queue_desc) + 1);
157*5113495bSYour Name qdf_mem_zero(reo_queue_ext_desc, 3 *
158*5113495bSYour Name sizeof(struct rx_reo_queue_ext));
159*5113495bSYour Name /* Initialize first reo queue extension descriptor */
160*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
161*5113495bSYour Name HAL_DESC_REO_OWNED,
162*5113495bSYour Name HAL_REO_QUEUE_EXT_DESC);
163*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
164*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_ext_desc,
165*5113495bSYour Name UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
166*5113495bSYour Name 0xADBEEF);
167*5113495bSYour Name /* Initialize second reo queue extension descriptor */
168*5113495bSYour Name reo_queue_ext_desc = (uint32_t *)
169*5113495bSYour Name (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
170*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
171*5113495bSYour Name HAL_DESC_REO_OWNED,
172*5113495bSYour Name HAL_REO_QUEUE_EXT_DESC);
173*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
174*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_ext_desc,
175*5113495bSYour Name UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
176*5113495bSYour Name 0xBDBEEF);
177*5113495bSYour Name /* Initialize third reo queue extension descriptor */
178*5113495bSYour Name reo_queue_ext_desc = (uint32_t *)
179*5113495bSYour Name (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
180*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
181*5113495bSYour Name HAL_DESC_REO_OWNED,
182*5113495bSYour Name HAL_REO_QUEUE_EXT_DESC);
183*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
184*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_ext_desc,
185*5113495bSYour Name UNIFORM_DESCRIPTOR_HEADER, RESERVED_0A,
186*5113495bSYour Name 0xCDBEEF);
187*5113495bSYour Name }
188*5113495bSYour Name
189*5113495bSYour Name qdf_export_symbol(hal_reo_qdesc_setup_be);
190*5113495bSYour Name
191*5113495bSYour Name static void
hal_reo_cmd_set_descr_addr_be(uint32_t * reo_desc,enum hal_reo_cmd_type type,uint32_t paddr_lo,uint8_t paddr_hi)192*5113495bSYour Name hal_reo_cmd_set_descr_addr_be(uint32_t *reo_desc,
193*5113495bSYour Name enum hal_reo_cmd_type type,
194*5113495bSYour Name uint32_t paddr_lo,
195*5113495bSYour Name uint8_t paddr_hi)
196*5113495bSYour Name {
197*5113495bSYour Name struct reo_get_queue_stats *reo_get_queue_stats;
198*5113495bSYour Name struct reo_flush_queue *reo_flush_queue;
199*5113495bSYour Name struct reo_flush_cache *reo_flush_cache;
200*5113495bSYour Name struct reo_update_rx_reo_queue *reo_update_rx_reo_queue;
201*5113495bSYour Name
202*5113495bSYour Name switch (type) {
203*5113495bSYour Name case CMD_GET_QUEUE_STATS:
204*5113495bSYour Name reo_get_queue_stats = (struct reo_get_queue_stats *)reo_desc;
205*5113495bSYour Name reo_get_queue_stats->rx_reo_queue_desc_addr_31_0 = paddr_lo;
206*5113495bSYour Name reo_get_queue_stats->rx_reo_queue_desc_addr_39_32 = paddr_hi;
207*5113495bSYour Name break;
208*5113495bSYour Name case CMD_FLUSH_QUEUE:
209*5113495bSYour Name reo_flush_queue = (struct reo_flush_queue *)reo_desc;
210*5113495bSYour Name reo_flush_queue->flush_desc_addr_31_0 = paddr_lo;
211*5113495bSYour Name reo_flush_queue->flush_desc_addr_39_32 = paddr_hi;
212*5113495bSYour Name break;
213*5113495bSYour Name case CMD_FLUSH_CACHE:
214*5113495bSYour Name reo_flush_cache = (struct reo_flush_cache *)reo_desc;
215*5113495bSYour Name reo_flush_cache->flush_addr_31_0 = paddr_lo;
216*5113495bSYour Name reo_flush_cache->flush_addr_39_32 = paddr_hi;
217*5113495bSYour Name break;
218*5113495bSYour Name case CMD_UPDATE_RX_REO_QUEUE:
219*5113495bSYour Name reo_update_rx_reo_queue =
220*5113495bSYour Name (struct reo_update_rx_reo_queue *)reo_desc;
221*5113495bSYour Name reo_update_rx_reo_queue->rx_reo_queue_desc_addr_31_0 = paddr_lo;
222*5113495bSYour Name reo_update_rx_reo_queue->rx_reo_queue_desc_addr_39_32 =
223*5113495bSYour Name paddr_hi;
224*5113495bSYour Name break;
225*5113495bSYour Name default:
226*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
227*5113495bSYour Name "%s: Invalid REO command type", __func__);
228*5113495bSYour Name break;
229*5113495bSYour Name }
230*5113495bSYour Name }
231*5113495bSYour Name
232*5113495bSYour Name static int
hal_reo_cmd_queue_stats_be(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)233*5113495bSYour Name hal_reo_cmd_queue_stats_be(hal_ring_handle_t hal_ring_hdl,
234*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
235*5113495bSYour Name struct hal_reo_cmd_params *cmd)
236*5113495bSYour Name {
237*5113495bSYour Name uint32_t *reo_desc, val;
238*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
239*5113495bSYour Name struct reo_get_queue_stats *reo_get_queue_stats;
240*5113495bSYour Name
241*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
242*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
243*5113495bSYour Name if (!reo_desc) {
244*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
245*5113495bSYour Name hal_warn_rl("Out of cmd ring entries");
246*5113495bSYour Name return -EBUSY;
247*5113495bSYour Name }
248*5113495bSYour Name
249*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_GET_QUEUE_STATS_E,
250*5113495bSYour Name sizeof(struct reo_get_queue_stats));
251*5113495bSYour Name
252*5113495bSYour Name /*
253*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
254*5113495bSYour Name * the field after TLV header
255*5113495bSYour Name */
256*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
257*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
258*5113495bSYour Name sizeof(struct reo_get_queue_stats) -
259*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
260*5113495bSYour Name
261*5113495bSYour Name reo_get_queue_stats = (struct reo_get_queue_stats *)reo_desc;
262*5113495bSYour Name reo_get_queue_stats->cmd_header.reo_status_required =
263*5113495bSYour Name cmd->std.need_status;
264*5113495bSYour Name
265*5113495bSYour Name hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_GET_QUEUE_STATS,
266*5113495bSYour Name cmd->std.addr_lo,
267*5113495bSYour Name cmd->std.addr_hi);
268*5113495bSYour Name
269*5113495bSYour Name reo_get_queue_stats->clear_stats = cmd->u.stats_params.clear;
270*5113495bSYour Name
271*5113495bSYour Name hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
272*5113495bSYour Name HIF_RTPM_ID_HAL_REO_CMD);
273*5113495bSYour Name
274*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
275*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
276*5113495bSYour Name val);
277*5113495bSYour Name }
278*5113495bSYour Name
279*5113495bSYour Name static int
hal_reo_cmd_flush_queue_be(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)280*5113495bSYour Name hal_reo_cmd_flush_queue_be(hal_ring_handle_t hal_ring_hdl,
281*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
282*5113495bSYour Name struct hal_reo_cmd_params *cmd)
283*5113495bSYour Name {
284*5113495bSYour Name uint32_t *reo_desc, val;
285*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
286*5113495bSYour Name struct reo_flush_queue *reo_flush_queue;
287*5113495bSYour Name
288*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
289*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
290*5113495bSYour Name if (!reo_desc) {
291*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
292*5113495bSYour Name hal_warn_rl("Out of cmd ring entries");
293*5113495bSYour Name return -EBUSY;
294*5113495bSYour Name }
295*5113495bSYour Name
296*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_QUEUE_E,
297*5113495bSYour Name sizeof(struct reo_flush_queue));
298*5113495bSYour Name
299*5113495bSYour Name /*
300*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
301*5113495bSYour Name * the field after TLV header
302*5113495bSYour Name */
303*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
304*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
305*5113495bSYour Name sizeof(struct reo_flush_queue) -
306*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
307*5113495bSYour Name
308*5113495bSYour Name reo_flush_queue = (struct reo_flush_queue *)reo_desc;
309*5113495bSYour Name reo_flush_queue->cmd_header.reo_status_required = cmd->std.need_status;
310*5113495bSYour Name
311*5113495bSYour Name hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_FLUSH_QUEUE,
312*5113495bSYour Name cmd->std.addr_lo, cmd->std.addr_hi);
313*5113495bSYour Name
314*5113495bSYour Name reo_flush_queue->block_desc_addr_usage_after_flush =
315*5113495bSYour Name cmd->u.fl_queue_params.block_use_after_flush;
316*5113495bSYour Name
317*5113495bSYour Name if (cmd->u.fl_queue_params.block_use_after_flush)
318*5113495bSYour Name reo_flush_queue->block_resource_index =
319*5113495bSYour Name cmd->u.fl_queue_params.index;
320*5113495bSYour Name
321*5113495bSYour Name hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
322*5113495bSYour Name HIF_RTPM_ID_HAL_REO_CMD);
323*5113495bSYour Name
324*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
325*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
326*5113495bSYour Name val);
327*5113495bSYour Name }
328*5113495bSYour Name
329*5113495bSYour Name static int
hal_reo_cmd_flush_cache_be(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)330*5113495bSYour Name hal_reo_cmd_flush_cache_be(hal_ring_handle_t hal_ring_hdl,
331*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
332*5113495bSYour Name struct hal_reo_cmd_params *cmd)
333*5113495bSYour Name {
334*5113495bSYour Name uint32_t *reo_desc, val;
335*5113495bSYour Name struct hal_reo_cmd_flush_cache_params *cp;
336*5113495bSYour Name uint8_t index = 0;
337*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
338*5113495bSYour Name struct reo_flush_cache *reo_flush_cache;
339*5113495bSYour Name
340*5113495bSYour Name cp = &cmd->u.fl_cache_params;
341*5113495bSYour Name
342*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
343*5113495bSYour Name
344*5113495bSYour Name /* We need a cache block resource for this operation, and REO HW has
345*5113495bSYour Name * only 4 such blocking resources. These resources are managed using
346*5113495bSYour Name * reo_res_bitmap, and we return failure if none is available.
347*5113495bSYour Name */
348*5113495bSYour Name if (cp->block_use_after_flush) {
349*5113495bSYour Name index = hal_find_zero_bit(hal_soc->reo_res_bitmap);
350*5113495bSYour Name if (index > 3) {
351*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
352*5113495bSYour Name hal_warn_rl("No blocking resource available!");
353*5113495bSYour Name return -EBUSY;
354*5113495bSYour Name }
355*5113495bSYour Name hal_soc->index = index;
356*5113495bSYour Name }
357*5113495bSYour Name
358*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
359*5113495bSYour Name if (!reo_desc) {
360*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
361*5113495bSYour Name hal_srng_dump(hal_ring_handle_to_hal_srng(hal_ring_hdl));
362*5113495bSYour Name return -EBUSY;
363*5113495bSYour Name }
364*5113495bSYour Name
365*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_CACHE_E,
366*5113495bSYour Name sizeof(struct reo_flush_cache));
367*5113495bSYour Name
368*5113495bSYour Name /*
369*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
370*5113495bSYour Name * the field after TLV header
371*5113495bSYour Name */
372*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
373*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
374*5113495bSYour Name sizeof(struct reo_flush_cache) -
375*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
376*5113495bSYour Name
377*5113495bSYour Name reo_flush_cache = (struct reo_flush_cache *)reo_desc;
378*5113495bSYour Name reo_flush_cache->cmd_header.reo_status_required = cmd->std.need_status;
379*5113495bSYour Name
380*5113495bSYour Name hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_FLUSH_CACHE,
381*5113495bSYour Name cmd->std.addr_lo, cmd->std.addr_hi);
382*5113495bSYour Name
383*5113495bSYour Name reo_flush_cache->forward_all_mpdus_in_queue = cp->fwd_mpdus_in_queue;
384*5113495bSYour Name
385*5113495bSYour Name /* set it to 0 for now */
386*5113495bSYour Name cp->rel_block_index = 0;
387*5113495bSYour Name reo_flush_cache->release_cache_block_index = cp->rel_block_index;
388*5113495bSYour Name
389*5113495bSYour Name if (cp->block_use_after_flush) {
390*5113495bSYour Name reo_flush_cache->cache_block_resource_index = index;
391*5113495bSYour Name }
392*5113495bSYour Name
393*5113495bSYour Name reo_flush_cache->flush_without_invalidate = cp->flush_no_inval;
394*5113495bSYour Name reo_flush_cache->flush_queue_1k_desc = cp->flush_q_1k_desc;
395*5113495bSYour Name reo_flush_cache->block_cache_usage_after_flush =
396*5113495bSYour Name cp->block_use_after_flush;
397*5113495bSYour Name reo_flush_cache->flush_entire_cache = cp->flush_entire_cache;
398*5113495bSYour Name
399*5113495bSYour Name hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
400*5113495bSYour Name HIF_RTPM_ID_HAL_REO_CMD);
401*5113495bSYour Name
402*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
403*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
404*5113495bSYour Name val);
405*5113495bSYour Name }
406*5113495bSYour Name
407*5113495bSYour Name static int
hal_reo_cmd_unblock_cache_be(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)408*5113495bSYour Name hal_reo_cmd_unblock_cache_be(hal_ring_handle_t hal_ring_hdl,
409*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
410*5113495bSYour Name struct hal_reo_cmd_params *cmd)
411*5113495bSYour Name
412*5113495bSYour Name {
413*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
414*5113495bSYour Name uint32_t *reo_desc, val;
415*5113495bSYour Name uint8_t index = 0;
416*5113495bSYour Name struct reo_unblock_cache *reo_unblock_cache;
417*5113495bSYour Name
418*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
419*5113495bSYour Name
420*5113495bSYour Name if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
421*5113495bSYour Name index = hal_find_one_bit(hal_soc->reo_res_bitmap);
422*5113495bSYour Name if (index > 3) {
423*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
424*5113495bSYour Name qdf_print("No blocking resource to unblock!");
425*5113495bSYour Name return -EBUSY;
426*5113495bSYour Name }
427*5113495bSYour Name }
428*5113495bSYour Name
429*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
430*5113495bSYour Name if (!reo_desc) {
431*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
432*5113495bSYour Name hal_warn_rl("Out of cmd ring entries");
433*5113495bSYour Name return -EBUSY;
434*5113495bSYour Name }
435*5113495bSYour Name
436*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_UNBLOCK_CACHE_E,
437*5113495bSYour Name sizeof(struct reo_unblock_cache));
438*5113495bSYour Name
439*5113495bSYour Name /*
440*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
441*5113495bSYour Name * the field after TLV header
442*5113495bSYour Name */
443*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
444*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
445*5113495bSYour Name sizeof(struct reo_unblock_cache) -
446*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
447*5113495bSYour Name
448*5113495bSYour Name reo_unblock_cache = (struct reo_unblock_cache *)reo_desc;
449*5113495bSYour Name reo_unblock_cache->cmd_header.reo_status_required =
450*5113495bSYour Name cmd->std.need_status;
451*5113495bSYour Name reo_unblock_cache->unblock_type = cmd->u.unblk_cache_params.type;
452*5113495bSYour Name
453*5113495bSYour Name if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX)
454*5113495bSYour Name reo_unblock_cache->cache_block_resource_index =
455*5113495bSYour Name cmd->u.unblk_cache_params.index;
456*5113495bSYour Name
457*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
458*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
459*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
460*5113495bSYour Name val);
461*5113495bSYour Name }
462*5113495bSYour Name
463*5113495bSYour Name static int
hal_reo_cmd_flush_timeout_list_be(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)464*5113495bSYour Name hal_reo_cmd_flush_timeout_list_be(hal_ring_handle_t hal_ring_hdl,
465*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
466*5113495bSYour Name struct hal_reo_cmd_params *cmd)
467*5113495bSYour Name {
468*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
469*5113495bSYour Name uint32_t *reo_desc, val;
470*5113495bSYour Name struct reo_flush_timeout_list *reo_flush_timeout_list;
471*5113495bSYour Name
472*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
473*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
474*5113495bSYour Name if (!reo_desc) {
475*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
476*5113495bSYour Name hal_warn_rl("Out of cmd ring entries");
477*5113495bSYour Name return -EBUSY;
478*5113495bSYour Name }
479*5113495bSYour Name
480*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_TIMEOUT_LIST_E,
481*5113495bSYour Name sizeof(struct reo_flush_timeout_list));
482*5113495bSYour Name
483*5113495bSYour Name /*
484*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
485*5113495bSYour Name * the field after TLV header
486*5113495bSYour Name */
487*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
488*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
489*5113495bSYour Name sizeof(struct reo_flush_timeout_list) -
490*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
491*5113495bSYour Name
492*5113495bSYour Name reo_flush_timeout_list = (struct reo_flush_timeout_list *)reo_desc;
493*5113495bSYour Name reo_flush_timeout_list->cmd_header.reo_status_required =
494*5113495bSYour Name cmd->std.need_status;
495*5113495bSYour Name reo_flush_timeout_list->ac_timout_list =
496*5113495bSYour Name cmd->u.fl_tim_list_params.ac_list;
497*5113495bSYour Name reo_flush_timeout_list->minimum_release_desc_count =
498*5113495bSYour Name cmd->u.fl_tim_list_params.min_rel_desc;
499*5113495bSYour Name reo_flush_timeout_list->minimum_forward_buf_count =
500*5113495bSYour Name cmd->u.fl_tim_list_params.min_fwd_buf;
501*5113495bSYour Name
502*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
503*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
504*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
505*5113495bSYour Name val);
506*5113495bSYour Name }
507*5113495bSYour Name
508*5113495bSYour Name static int
hal_reo_cmd_update_rx_queue_be(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)509*5113495bSYour Name hal_reo_cmd_update_rx_queue_be(hal_ring_handle_t hal_ring_hdl,
510*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
511*5113495bSYour Name struct hal_reo_cmd_params *cmd)
512*5113495bSYour Name {
513*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
514*5113495bSYour Name uint32_t *reo_desc, val;
515*5113495bSYour Name struct hal_reo_cmd_update_queue_params *p;
516*5113495bSYour Name struct reo_update_rx_reo_queue *reo_update_rx_reo_queue;
517*5113495bSYour Name
518*5113495bSYour Name p = &cmd->u.upd_queue_params;
519*5113495bSYour Name
520*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
521*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
522*5113495bSYour Name if (!reo_desc) {
523*5113495bSYour Name hal_srng_access_end_reap(hal_soc, hal_ring_hdl);
524*5113495bSYour Name hal_warn_rl("Out of cmd ring entries");
525*5113495bSYour Name return -EBUSY;
526*5113495bSYour Name }
527*5113495bSYour Name
528*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_UPDATE_RX_REO_QUEUE_E,
529*5113495bSYour Name sizeof(struct reo_update_rx_reo_queue));
530*5113495bSYour Name
531*5113495bSYour Name /*
532*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
533*5113495bSYour Name * the field after TLV header
534*5113495bSYour Name */
535*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
536*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
537*5113495bSYour Name sizeof(struct reo_update_rx_reo_queue) -
538*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
539*5113495bSYour Name
540*5113495bSYour Name reo_update_rx_reo_queue = (struct reo_update_rx_reo_queue *)reo_desc;
541*5113495bSYour Name reo_update_rx_reo_queue->cmd_header.reo_status_required =
542*5113495bSYour Name cmd->std.need_status;
543*5113495bSYour Name
544*5113495bSYour Name hal_reo_cmd_set_descr_addr_be(reo_desc, CMD_UPDATE_RX_REO_QUEUE,
545*5113495bSYour Name cmd->std.addr_lo, cmd->std.addr_hi);
546*5113495bSYour Name
547*5113495bSYour Name reo_update_rx_reo_queue->update_receive_queue_number =
548*5113495bSYour Name p->update_rx_queue_num;
549*5113495bSYour Name reo_update_rx_reo_queue->update_vld = p->update_vld;
550*5113495bSYour Name reo_update_rx_reo_queue->update_associated_link_descriptor_counter =
551*5113495bSYour Name p->update_assoc_link_desc;
552*5113495bSYour Name reo_update_rx_reo_queue->update_disable_duplicate_detection =
553*5113495bSYour Name p->update_disable_dup_detect;
554*5113495bSYour Name reo_update_rx_reo_queue->update_soft_reorder_enable =
555*5113495bSYour Name p->update_soft_reorder_enab;
556*5113495bSYour Name reo_update_rx_reo_queue->update_ac = p->update_ac;
557*5113495bSYour Name reo_update_rx_reo_queue->update_bar = p->update_bar;
558*5113495bSYour Name reo_update_rx_reo_queue->update_rty = p->update_rty;
559*5113495bSYour Name reo_update_rx_reo_queue->update_chk_2k_mode = p->update_chk_2k_mode;
560*5113495bSYour Name reo_update_rx_reo_queue->update_oor_mode = p->update_oor_mode;
561*5113495bSYour Name reo_update_rx_reo_queue->update_ba_window_size =
562*5113495bSYour Name p->update_ba_window_size;
563*5113495bSYour Name reo_update_rx_reo_queue->update_pn_check_needed =
564*5113495bSYour Name p->update_pn_check_needed;
565*5113495bSYour Name reo_update_rx_reo_queue->update_pn_shall_be_even = p->update_pn_even;
566*5113495bSYour Name reo_update_rx_reo_queue->update_pn_shall_be_uneven =
567*5113495bSYour Name p->update_pn_uneven;
568*5113495bSYour Name reo_update_rx_reo_queue->update_pn_handling_enable =
569*5113495bSYour Name p->update_pn_hand_enab;
570*5113495bSYour Name reo_update_rx_reo_queue->update_pn_size = p->update_pn_size;
571*5113495bSYour Name reo_update_rx_reo_queue->update_ignore_ampdu_flag =
572*5113495bSYour Name p->update_ignore_ampdu;
573*5113495bSYour Name reo_update_rx_reo_queue->update_svld = p->update_svld;
574*5113495bSYour Name reo_update_rx_reo_queue->update_ssn = p->update_ssn;
575*5113495bSYour Name reo_update_rx_reo_queue->update_seq_2k_error_detected_flag =
576*5113495bSYour Name p->update_seq_2k_err_detect;
577*5113495bSYour Name reo_update_rx_reo_queue->update_pn_valid = p->update_pn_valid;
578*5113495bSYour Name reo_update_rx_reo_queue->update_pn = p->update_pn;
579*5113495bSYour Name reo_update_rx_reo_queue->receive_queue_number = p->rx_queue_num;
580*5113495bSYour Name reo_update_rx_reo_queue->vld = p->vld;
581*5113495bSYour Name reo_update_rx_reo_queue->associated_link_descriptor_counter =
582*5113495bSYour Name p->assoc_link_desc;
583*5113495bSYour Name reo_update_rx_reo_queue->disable_duplicate_detection =
584*5113495bSYour Name p->disable_dup_detect;
585*5113495bSYour Name reo_update_rx_reo_queue->soft_reorder_enable = p->soft_reorder_enab;
586*5113495bSYour Name reo_update_rx_reo_queue->ac = p->ac;
587*5113495bSYour Name reo_update_rx_reo_queue->bar = p->bar;
588*5113495bSYour Name reo_update_rx_reo_queue->chk_2k_mode = p->chk_2k_mode;
589*5113495bSYour Name reo_update_rx_reo_queue->rty = p->rty;
590*5113495bSYour Name reo_update_rx_reo_queue->oor_mode = p->oor_mode;
591*5113495bSYour Name reo_update_rx_reo_queue->pn_check_needed = p->pn_check_needed;
592*5113495bSYour Name reo_update_rx_reo_queue->pn_shall_be_even = p->pn_even;
593*5113495bSYour Name reo_update_rx_reo_queue->pn_shall_be_uneven = p->pn_uneven;
594*5113495bSYour Name reo_update_rx_reo_queue->pn_handling_enable = p->pn_hand_enab;
595*5113495bSYour Name reo_update_rx_reo_queue->ignore_ampdu_flag = p->ignore_ampdu;
596*5113495bSYour Name
597*5113495bSYour Name if (p->ba_window_size < 1)
598*5113495bSYour Name p->ba_window_size = 1;
599*5113495bSYour Name /*
600*5113495bSYour Name * WAR to get 2k exception in Non BA case.
601*5113495bSYour Name * Setting window size to 2 to get 2k jump exception
602*5113495bSYour Name * when we receive aggregates in Non BA case
603*5113495bSYour Name */
604*5113495bSYour Name if (p->ba_window_size == 1)
605*5113495bSYour Name p->ba_window_size++;
606*5113495bSYour Name
607*5113495bSYour Name reo_update_rx_reo_queue->ba_window_size = p->ba_window_size - 1;
608*5113495bSYour Name reo_update_rx_reo_queue->pn_size = p->pn_size;
609*5113495bSYour Name reo_update_rx_reo_queue->svld = p->svld;
610*5113495bSYour Name reo_update_rx_reo_queue->ssn = p->ssn;
611*5113495bSYour Name reo_update_rx_reo_queue->seq_2k_error_detected_flag =
612*5113495bSYour Name p->seq_2k_err_detect;
613*5113495bSYour Name reo_update_rx_reo_queue->pn_error_detected_flag = p->pn_err_detect;
614*5113495bSYour Name reo_update_rx_reo_queue->pn_31_0 = p->pn_31_0;
615*5113495bSYour Name reo_update_rx_reo_queue->pn_63_32 = p->pn_63_32;
616*5113495bSYour Name reo_update_rx_reo_queue->pn_95_64 = p->pn_95_64;
617*5113495bSYour Name reo_update_rx_reo_queue->pn_127_96 = p->pn_127_96;
618*5113495bSYour Name
619*5113495bSYour Name hal_srng_access_end_v1(hal_soc_hdl, hal_ring_hdl,
620*5113495bSYour Name HIF_RTPM_ID_HAL_REO_CMD);
621*5113495bSYour Name
622*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
623*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER, REO_CMD_NUMBER,
624*5113495bSYour Name val);
625*5113495bSYour Name }
626*5113495bSYour Name
hal_reo_send_cmd_be(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,enum hal_reo_cmd_type cmd,void * params)627*5113495bSYour Name int hal_reo_send_cmd_be(hal_soc_handle_t hal_soc_hdl,
628*5113495bSYour Name hal_ring_handle_t hal_ring_hdl,
629*5113495bSYour Name enum hal_reo_cmd_type cmd,
630*5113495bSYour Name void *params)
631*5113495bSYour Name {
632*5113495bSYour Name struct hal_reo_cmd_params *cmd_params =
633*5113495bSYour Name (struct hal_reo_cmd_params *)params;
634*5113495bSYour Name int num = 0;
635*5113495bSYour Name
636*5113495bSYour Name switch (cmd) {
637*5113495bSYour Name case CMD_GET_QUEUE_STATS:
638*5113495bSYour Name num = hal_reo_cmd_queue_stats_be(hal_ring_hdl,
639*5113495bSYour Name hal_soc_hdl, cmd_params);
640*5113495bSYour Name break;
641*5113495bSYour Name case CMD_FLUSH_QUEUE:
642*5113495bSYour Name num = hal_reo_cmd_flush_queue_be(hal_ring_hdl,
643*5113495bSYour Name hal_soc_hdl, cmd_params);
644*5113495bSYour Name break;
645*5113495bSYour Name case CMD_FLUSH_CACHE:
646*5113495bSYour Name num = hal_reo_cmd_flush_cache_be(hal_ring_hdl,
647*5113495bSYour Name hal_soc_hdl, cmd_params);
648*5113495bSYour Name break;
649*5113495bSYour Name case CMD_UNBLOCK_CACHE:
650*5113495bSYour Name num = hal_reo_cmd_unblock_cache_be(hal_ring_hdl,
651*5113495bSYour Name hal_soc_hdl, cmd_params);
652*5113495bSYour Name break;
653*5113495bSYour Name case CMD_FLUSH_TIMEOUT_LIST:
654*5113495bSYour Name num = hal_reo_cmd_flush_timeout_list_be(hal_ring_hdl,
655*5113495bSYour Name hal_soc_hdl,
656*5113495bSYour Name cmd_params);
657*5113495bSYour Name break;
658*5113495bSYour Name case CMD_UPDATE_RX_REO_QUEUE:
659*5113495bSYour Name num = hal_reo_cmd_update_rx_queue_be(hal_ring_hdl,
660*5113495bSYour Name hal_soc_hdl, cmd_params);
661*5113495bSYour Name break;
662*5113495bSYour Name default:
663*5113495bSYour Name hal_err("Invalid REO command type: %d", cmd);
664*5113495bSYour Name return -EINVAL;
665*5113495bSYour Name };
666*5113495bSYour Name
667*5113495bSYour Name return num;
668*5113495bSYour Name }
669*5113495bSYour Name
670*5113495bSYour Name void
hal_reo_queue_stats_status_be(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)671*5113495bSYour Name hal_reo_queue_stats_status_be(hal_ring_desc_t ring_desc,
672*5113495bSYour Name void *st_handle,
673*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
674*5113495bSYour Name {
675*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
676*5113495bSYour Name struct hal_reo_queue_status *st =
677*5113495bSYour Name (struct hal_reo_queue_status *)st_handle;
678*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
679*5113495bSYour Name uint64_t val;
680*5113495bSYour Name
681*5113495bSYour Name /*
682*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
683*5113495bSYour Name * from the field after TLV header
684*5113495bSYour Name */
685*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
686*5113495bSYour Name
687*5113495bSYour Name /* header */
688*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
689*5113495bSYour Name &(st->header), hal_soc);
690*5113495bSYour Name
691*5113495bSYour Name /* SSN */
692*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS, SSN)];
693*5113495bSYour Name st->ssn = HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS, SSN, val);
694*5113495bSYour Name
695*5113495bSYour Name /* current index */
696*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
697*5113495bSYour Name CURRENT_INDEX)];
698*5113495bSYour Name st->curr_idx =
699*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
700*5113495bSYour Name CURRENT_INDEX, val);
701*5113495bSYour Name
702*5113495bSYour Name /* PN bits */
703*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
704*5113495bSYour Name PN_31_0)];
705*5113495bSYour Name st->pn_31_0 =
706*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
707*5113495bSYour Name PN_31_0, val);
708*5113495bSYour Name
709*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
710*5113495bSYour Name PN_63_32)];
711*5113495bSYour Name st->pn_63_32 =
712*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
713*5113495bSYour Name PN_63_32, val);
714*5113495bSYour Name
715*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
716*5113495bSYour Name PN_95_64)];
717*5113495bSYour Name st->pn_95_64 =
718*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
719*5113495bSYour Name PN_95_64, val);
720*5113495bSYour Name
721*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
722*5113495bSYour Name PN_127_96)];
723*5113495bSYour Name st->pn_127_96 =
724*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
725*5113495bSYour Name PN_127_96, val);
726*5113495bSYour Name
727*5113495bSYour Name /* timestamps */
728*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
729*5113495bSYour Name LAST_RX_ENQUEUE_TIMESTAMP)];
730*5113495bSYour Name st->last_rx_enq_tstamp =
731*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
732*5113495bSYour Name LAST_RX_ENQUEUE_TIMESTAMP, val);
733*5113495bSYour Name
734*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
735*5113495bSYour Name LAST_RX_DEQUEUE_TIMESTAMP)];
736*5113495bSYour Name st->last_rx_deq_tstamp =
737*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
738*5113495bSYour Name LAST_RX_DEQUEUE_TIMESTAMP, val);
739*5113495bSYour Name
740*5113495bSYour Name /* rx bitmap */
741*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
742*5113495bSYour Name RX_BITMAP_31_0)];
743*5113495bSYour Name st->rx_bitmap_31_0 =
744*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
745*5113495bSYour Name RX_BITMAP_31_0, val);
746*5113495bSYour Name
747*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
748*5113495bSYour Name RX_BITMAP_63_32)];
749*5113495bSYour Name st->rx_bitmap_63_32 =
750*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
751*5113495bSYour Name RX_BITMAP_63_32, val);
752*5113495bSYour Name
753*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
754*5113495bSYour Name RX_BITMAP_95_64)];
755*5113495bSYour Name st->rx_bitmap_95_64 =
756*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
757*5113495bSYour Name RX_BITMAP_95_64, val);
758*5113495bSYour Name
759*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
760*5113495bSYour Name RX_BITMAP_127_96)];
761*5113495bSYour Name st->rx_bitmap_127_96 =
762*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
763*5113495bSYour Name RX_BITMAP_127_96, val);
764*5113495bSYour Name
765*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
766*5113495bSYour Name RX_BITMAP_159_128)];
767*5113495bSYour Name st->rx_bitmap_159_128 =
768*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
769*5113495bSYour Name RX_BITMAP_159_128, val);
770*5113495bSYour Name
771*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
772*5113495bSYour Name RX_BITMAP_191_160)];
773*5113495bSYour Name st->rx_bitmap_191_160 =
774*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
775*5113495bSYour Name RX_BITMAP_191_160, val);
776*5113495bSYour Name
777*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
778*5113495bSYour Name RX_BITMAP_223_192)];
779*5113495bSYour Name st->rx_bitmap_223_192 =
780*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
781*5113495bSYour Name RX_BITMAP_223_192, val);
782*5113495bSYour Name
783*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
784*5113495bSYour Name RX_BITMAP_255_224)];
785*5113495bSYour Name st->rx_bitmap_255_224 =
786*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
787*5113495bSYour Name RX_BITMAP_255_224, val);
788*5113495bSYour Name
789*5113495bSYour Name /* various counts */
790*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
791*5113495bSYour Name CURRENT_MPDU_COUNT)];
792*5113495bSYour Name st->curr_mpdu_cnt =
793*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
794*5113495bSYour Name CURRENT_MPDU_COUNT, val);
795*5113495bSYour Name
796*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
797*5113495bSYour Name CURRENT_MSDU_COUNT)];
798*5113495bSYour Name st->curr_msdu_cnt =
799*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
800*5113495bSYour Name CURRENT_MSDU_COUNT, val);
801*5113495bSYour Name
802*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
803*5113495bSYour Name TIMEOUT_COUNT)];
804*5113495bSYour Name st->fwd_timeout_cnt =
805*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
806*5113495bSYour Name TIMEOUT_COUNT, val);
807*5113495bSYour Name
808*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
809*5113495bSYour Name FORWARD_DUE_TO_BAR_COUNT)];
810*5113495bSYour Name st->fwd_bar_cnt =
811*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
812*5113495bSYour Name FORWARD_DUE_TO_BAR_COUNT, val);
813*5113495bSYour Name
814*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
815*5113495bSYour Name DUPLICATE_COUNT)];
816*5113495bSYour Name st->dup_cnt =
817*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
818*5113495bSYour Name DUPLICATE_COUNT, val);
819*5113495bSYour Name
820*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
821*5113495bSYour Name FRAMES_IN_ORDER_COUNT)];
822*5113495bSYour Name st->frms_in_order_cnt =
823*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
824*5113495bSYour Name FRAMES_IN_ORDER_COUNT, val);
825*5113495bSYour Name
826*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
827*5113495bSYour Name BAR_RECEIVED_COUNT)];
828*5113495bSYour Name st->bar_rcvd_cnt =
829*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
830*5113495bSYour Name BAR_RECEIVED_COUNT, val);
831*5113495bSYour Name
832*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
833*5113495bSYour Name MPDU_FRAMES_PROCESSED_COUNT)];
834*5113495bSYour Name st->mpdu_frms_cnt =
835*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
836*5113495bSYour Name MPDU_FRAMES_PROCESSED_COUNT, val);
837*5113495bSYour Name
838*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
839*5113495bSYour Name MSDU_FRAMES_PROCESSED_COUNT)];
840*5113495bSYour Name st->msdu_frms_cnt =
841*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
842*5113495bSYour Name MSDU_FRAMES_PROCESSED_COUNT, val);
843*5113495bSYour Name
844*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
845*5113495bSYour Name TOTAL_PROCESSED_BYTE_COUNT)];
846*5113495bSYour Name st->total_cnt =
847*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
848*5113495bSYour Name TOTAL_PROCESSED_BYTE_COUNT, val);
849*5113495bSYour Name
850*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
851*5113495bSYour Name LATE_RECEIVE_MPDU_COUNT)];
852*5113495bSYour Name st->late_recv_mpdu_cnt =
853*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
854*5113495bSYour Name LATE_RECEIVE_MPDU_COUNT, val);
855*5113495bSYour Name
856*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
857*5113495bSYour Name WINDOW_JUMP_2K)];
858*5113495bSYour Name st->win_jump_2k =
859*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
860*5113495bSYour Name WINDOW_JUMP_2K, val);
861*5113495bSYour Name
862*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
863*5113495bSYour Name HOLE_COUNT)];
864*5113495bSYour Name st->hole_cnt =
865*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS,
866*5113495bSYour Name HOLE_COUNT, val);
867*5113495bSYour Name }
868*5113495bSYour Name
869*5113495bSYour Name void
hal_reo_flush_queue_status_be(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)870*5113495bSYour Name hal_reo_flush_queue_status_be(hal_ring_desc_t ring_desc,
871*5113495bSYour Name void *st_handle,
872*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
873*5113495bSYour Name {
874*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
875*5113495bSYour Name struct hal_reo_flush_queue_status *st =
876*5113495bSYour Name (struct hal_reo_flush_queue_status *)st_handle;
877*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
878*5113495bSYour Name uint64_t val;
879*5113495bSYour Name
880*5113495bSYour Name /*
881*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
882*5113495bSYour Name * from the field after TLV header
883*5113495bSYour Name */
884*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
885*5113495bSYour Name
886*5113495bSYour Name /* header */
887*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
888*5113495bSYour Name &(st->header), hal_soc);
889*5113495bSYour Name
890*5113495bSYour Name /* error bit */
891*5113495bSYour Name val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS,
892*5113495bSYour Name ERROR_DETECTED)];
893*5113495bSYour Name st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS, ERROR_DETECTED,
894*5113495bSYour Name val);
895*5113495bSYour Name }
896*5113495bSYour Name
897*5113495bSYour Name void
hal_reo_flush_cache_status_be(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)898*5113495bSYour Name hal_reo_flush_cache_status_be(hal_ring_desc_t ring_desc,
899*5113495bSYour Name void *st_handle,
900*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
901*5113495bSYour Name {
902*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
903*5113495bSYour Name struct hal_reo_flush_cache_status *st =
904*5113495bSYour Name (struct hal_reo_flush_cache_status *)st_handle;
905*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
906*5113495bSYour Name uint64_t val;
907*5113495bSYour Name
908*5113495bSYour Name /*
909*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
910*5113495bSYour Name * from the field after TLV header
911*5113495bSYour Name */
912*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
913*5113495bSYour Name
914*5113495bSYour Name /* header */
915*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
916*5113495bSYour Name &(st->header), hal_soc);
917*5113495bSYour Name
918*5113495bSYour Name /* error bit */
919*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
920*5113495bSYour Name ERROR_DETECTED)];
921*5113495bSYour Name st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS, ERROR_DETECTED,
922*5113495bSYour Name val);
923*5113495bSYour Name
924*5113495bSYour Name /* block error */
925*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
926*5113495bSYour Name BLOCK_ERROR_DETAILS)];
927*5113495bSYour Name st->block_error = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
928*5113495bSYour Name BLOCK_ERROR_DETAILS,
929*5113495bSYour Name val);
930*5113495bSYour Name if (!st->block_error)
931*5113495bSYour Name qdf_set_bit(hal_soc->index,
932*5113495bSYour Name (unsigned long *)&hal_soc->reo_res_bitmap);
933*5113495bSYour Name
934*5113495bSYour Name /* cache flush status */
935*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
936*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_HIT)];
937*5113495bSYour Name st->cache_flush_status = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
938*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_HIT,
939*5113495bSYour Name val);
940*5113495bSYour Name
941*5113495bSYour Name /* cache flush descriptor type */
942*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
943*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE)];
944*5113495bSYour Name st->cache_flush_status_desc_type =
945*5113495bSYour Name HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
946*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE,
947*5113495bSYour Name val);
948*5113495bSYour Name
949*5113495bSYour Name /* cache flush count */
950*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
951*5113495bSYour Name CACHE_CONTROLLER_FLUSH_COUNT)];
952*5113495bSYour Name st->cache_flush_cnt =
953*5113495bSYour Name HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS,
954*5113495bSYour Name CACHE_CONTROLLER_FLUSH_COUNT,
955*5113495bSYour Name val);
956*5113495bSYour Name }
957*5113495bSYour Name
958*5113495bSYour Name void
hal_reo_unblock_cache_status_be(hal_ring_desc_t ring_desc,hal_soc_handle_t hal_soc_hdl,void * st_handle)959*5113495bSYour Name hal_reo_unblock_cache_status_be(hal_ring_desc_t ring_desc,
960*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
961*5113495bSYour Name void *st_handle)
962*5113495bSYour Name {
963*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
964*5113495bSYour Name struct hal_reo_unblk_cache_status *st =
965*5113495bSYour Name (struct hal_reo_unblk_cache_status *)st_handle;
966*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
967*5113495bSYour Name uint64_t val;
968*5113495bSYour Name
969*5113495bSYour Name /*
970*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
971*5113495bSYour Name * from the field after TLV header
972*5113495bSYour Name */
973*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
974*5113495bSYour Name
975*5113495bSYour Name /* header */
976*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
977*5113495bSYour Name &st->header, hal_soc);
978*5113495bSYour Name
979*5113495bSYour Name /* error bit */
980*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
981*5113495bSYour Name ERROR_DETECTED)];
982*5113495bSYour Name st->error = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS,
983*5113495bSYour Name ERROR_DETECTED,
984*5113495bSYour Name val);
985*5113495bSYour Name
986*5113495bSYour Name /* unblock type */
987*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
988*5113495bSYour Name UNBLOCK_TYPE)];
989*5113495bSYour Name st->unblock_type = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS,
990*5113495bSYour Name UNBLOCK_TYPE,
991*5113495bSYour Name val);
992*5113495bSYour Name
993*5113495bSYour Name if (!st->error && (st->unblock_type == UNBLOCK_RES_INDEX))
994*5113495bSYour Name qdf_clear_bit(hal_soc->index,
995*5113495bSYour Name (unsigned long *)&hal_soc->reo_res_bitmap);
996*5113495bSYour Name }
997*5113495bSYour Name
hal_reo_flush_timeout_list_status_be(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)998*5113495bSYour Name void hal_reo_flush_timeout_list_status_be(hal_ring_desc_t ring_desc,
999*5113495bSYour Name void *st_handle,
1000*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1001*5113495bSYour Name {
1002*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1003*5113495bSYour Name struct hal_reo_flush_timeout_list_status *st =
1004*5113495bSYour Name (struct hal_reo_flush_timeout_list_status *)st_handle;
1005*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
1006*5113495bSYour Name uint64_t val;
1007*5113495bSYour Name
1008*5113495bSYour Name /*
1009*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1010*5113495bSYour Name * from the field after TLV header
1011*5113495bSYour Name */
1012*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
1013*5113495bSYour Name
1014*5113495bSYour Name /* header */
1015*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
1016*5113495bSYour Name &(st->header), hal_soc);
1017*5113495bSYour Name
1018*5113495bSYour Name /* error bit */
1019*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1020*5113495bSYour Name ERROR_DETECTED)];
1021*5113495bSYour Name st->error = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
1022*5113495bSYour Name ERROR_DETECTED,
1023*5113495bSYour Name val);
1024*5113495bSYour Name
1025*5113495bSYour Name /* list empty */
1026*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1027*5113495bSYour Name TIMOUT_LIST_EMPTY)];
1028*5113495bSYour Name st->list_empty = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
1029*5113495bSYour Name TIMOUT_LIST_EMPTY,
1030*5113495bSYour Name val);
1031*5113495bSYour Name
1032*5113495bSYour Name /* release descriptor count */
1033*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1034*5113495bSYour Name RELEASE_DESC_COUNT)];
1035*5113495bSYour Name st->rel_desc_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
1036*5113495bSYour Name RELEASE_DESC_COUNT,
1037*5113495bSYour Name val);
1038*5113495bSYour Name
1039*5113495bSYour Name /* forward buf count */
1040*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1041*5113495bSYour Name FORWARD_BUF_COUNT)];
1042*5113495bSYour Name st->fwd_buf_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS,
1043*5113495bSYour Name FORWARD_BUF_COUNT,
1044*5113495bSYour Name val);
1045*5113495bSYour Name }
1046*5113495bSYour Name
hal_reo_desc_thres_reached_status_be(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1047*5113495bSYour Name void hal_reo_desc_thres_reached_status_be(hal_ring_desc_t ring_desc,
1048*5113495bSYour Name void *st_handle,
1049*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1050*5113495bSYour Name {
1051*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1052*5113495bSYour Name struct hal_reo_desc_thres_reached_status *st =
1053*5113495bSYour Name (struct hal_reo_desc_thres_reached_status *)st_handle;
1054*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
1055*5113495bSYour Name uint64_t val;
1056*5113495bSYour Name
1057*5113495bSYour Name /*
1058*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1059*5113495bSYour Name * from the field after TLV header
1060*5113495bSYour Name */
1061*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
1062*5113495bSYour Name
1063*5113495bSYour Name /* header */
1064*5113495bSYour Name hal_reo_status_get_header(ring_desc,
1065*5113495bSYour Name HAL_REO_DESC_THRES_STATUS_TLV,
1066*5113495bSYour Name &(st->header), hal_soc);
1067*5113495bSYour Name
1068*5113495bSYour Name /* threshold index */
1069*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(
1070*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1071*5113495bSYour Name THRESHOLD_INDEX)];
1072*5113495bSYour Name st->thres_index = HAL_GET_FIELD(
1073*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1074*5113495bSYour Name THRESHOLD_INDEX,
1075*5113495bSYour Name val);
1076*5113495bSYour Name
1077*5113495bSYour Name /* link desc counters */
1078*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(
1079*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1080*5113495bSYour Name LINK_DESCRIPTOR_COUNTER0)];
1081*5113495bSYour Name st->link_desc_counter0 = HAL_GET_FIELD(
1082*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1083*5113495bSYour Name LINK_DESCRIPTOR_COUNTER0,
1084*5113495bSYour Name val);
1085*5113495bSYour Name
1086*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(
1087*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1088*5113495bSYour Name LINK_DESCRIPTOR_COUNTER1)];
1089*5113495bSYour Name st->link_desc_counter1 = HAL_GET_FIELD(
1090*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1091*5113495bSYour Name LINK_DESCRIPTOR_COUNTER1,
1092*5113495bSYour Name val);
1093*5113495bSYour Name
1094*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(
1095*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1096*5113495bSYour Name LINK_DESCRIPTOR_COUNTER2)];
1097*5113495bSYour Name st->link_desc_counter2 = HAL_GET_FIELD(
1098*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1099*5113495bSYour Name LINK_DESCRIPTOR_COUNTER2,
1100*5113495bSYour Name val);
1101*5113495bSYour Name
1102*5113495bSYour Name val = reo_desc[HAL_OFFSET_QW(
1103*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1104*5113495bSYour Name LINK_DESCRIPTOR_COUNTER_SUM)];
1105*5113495bSYour Name st->link_desc_counter_sum = HAL_GET_FIELD(
1106*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1107*5113495bSYour Name LINK_DESCRIPTOR_COUNTER_SUM,
1108*5113495bSYour Name val);
1109*5113495bSYour Name }
1110*5113495bSYour Name
1111*5113495bSYour Name void
hal_reo_rx_update_queue_status_be(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1112*5113495bSYour Name hal_reo_rx_update_queue_status_be(hal_ring_desc_t ring_desc,
1113*5113495bSYour Name void *st_handle,
1114*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1115*5113495bSYour Name {
1116*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1117*5113495bSYour Name struct hal_reo_update_rx_queue_status *st =
1118*5113495bSYour Name (struct hal_reo_update_rx_queue_status *)st_handle;
1119*5113495bSYour Name uint64_t *reo_desc = (uint64_t *)ring_desc;
1120*5113495bSYour Name
1121*5113495bSYour Name /*
1122*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1123*5113495bSYour Name * from the field after TLV header
1124*5113495bSYour Name */
1125*5113495bSYour Name reo_desc += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
1126*5113495bSYour Name
1127*5113495bSYour Name /* header */
1128*5113495bSYour Name hal_reo_status_get_header(ring_desc,
1129*5113495bSYour Name HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
1130*5113495bSYour Name &(st->header), hal_soc);
1131*5113495bSYour Name }
1132*5113495bSYour Name
hal_get_tlv_hdr_size_be(void)1133*5113495bSYour Name uint8_t hal_get_tlv_hdr_size_be(void)
1134*5113495bSYour Name {
1135*5113495bSYour Name return sizeof(struct tlv_32_hdr);
1136*5113495bSYour Name }
1137