xref: /wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/be/hal_be_rx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _HAL_BE_RX_H_
21 #define _HAL_BE_RX_H_
22 
23 #include "hal_be_hw_headers.h"
24 #include "hal_be_rx_tlv.h"
25 #include "hal_rx.h"
26 #include <wbm_release_ring_rx.h>
27 
28 #define HAL_RX_DA_IDX_CHIP_ID_OFFSET    14
29 #define HAL_RX_DA_IDX_CHIP_ID_MASK      0x3
30 
31 #define HAL_RX_DA_IDX_PEER_ID_MASK    0x3fff
32 #define HAL_RX_DA_IDX_ML_PEER_MASK    0x2000
33 
34 /*
35  * macro to set the cookie into the rxdma ring entry
36  */
37 #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
38 		((*(((unsigned int *)buff_addr_info) + \
39 		(BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
40 		~BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK); \
41 		((*(((unsigned int *)buff_addr_info) + \
42 		(BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
43 		(cookie << BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB) & \
44 		BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK)
45 
46 /*
47  * macro to set the manager into the rxdma ring entry
48  */
49 #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
50 		((*(((unsigned int *)buff_addr_info) + \
51 		(BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
52 		~BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK); \
53 		((*(((unsigned int *)buff_addr_info) + \
54 		(BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
55 		(manager << BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB) & \
56 		BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK)
57 
58 #define HAL_RX_ERROR_STATUS_GET(reo_desc)			\
59 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc,		\
60 		REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET)),\
61 		REO_DESTINATION_RING_REO_PUSH_REASON_MASK,	\
62 		REO_DESTINATION_RING_REO_PUSH_REASON_LSB))
63 
64 #define HAL_RX_BUF_COOKIE_GET(buff_addr_info)			\
65 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info,		\
66 		BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET)),	\
67 		BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK,	\
68 		BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB))
69 
70 #define HAL_RX_BUF_RBM_GET(buff_addr_info)			\
71 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info,		\
72 		BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET)),\
73 		BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK,	\
74 		BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB))
75 
76 /* TODO: Convert the following structure fields accesseses to offsets */
77 
78 #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc)	\
79 	(HAL_RX_BUF_COOKIE_GET(&		\
80 	(((struct reo_destination_ring *)	\
81 		reo_desc)->buf_or_link_desc_addr_info)))
82 
83 #define HAL_RX_MSDU_DESC_IP_CHKSUM_FAIL_GET(msdu_desc_info_ptr)	\
84 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((msdu_desc_info_ptr),	\
85 		RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET)),	\
86 		RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK,	\
87 		RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB))
88 
89 #define HAL_RX_REO_IP_CHKSUM_FAIL_GET(ring_desc)	\
90 	(HAL_RX_MSDU_DESC_IP_CHKSUM_FAIL_GET(&		\
91 	((struct reo_destination_ring *)ring_desc)->rx_msdu_desc_info_details))
92 
93 #define HAL_RX_MSDU_DESC_TCP_UDP_CHKSUM_FAIL_GET(msdu_desc_info_ptr)	\
94 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((msdu_desc_info_ptr),		\
95 		RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET)),	\
96 		RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK,	\
97 		RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB))
98 
99 #define HAL_RX_REO_TCP_UDP_CHKSUM_FAIL_GET(ring_desc)	\
100 	(HAL_RX_MSDU_DESC_TCP_UDP_CHKSUM_FAIL_GET(&		\
101 	((struct reo_destination_ring *)ring_desc)->rx_msdu_desc_info_details))
102 
103 #define HAL_RX_MSDU_DESC_AMPDU_FLAG_GET(mpdu_info_ptr)		\
104 	(_HAL_MS((*_OFFSET_TO_WORD_PTR((mpdu_info_ptr),		\
105 		RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET)),		\
106 		RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK,		\
107 		RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB))
108 
109 #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr)	\
110 	((mpdu_info_ptr					\
111 	[RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET >> 2] & \
112 	RX_MPDU_DESC_INFO_PEER_META_DATA_MASK) >> \
113 	RX_MPDU_DESC_INFO_PEER_META_DATA_LSB)
114 
115 #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \
116 	((mpdu_info_ptr[RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET >> 2] & \
117 	RX_MPDU_DESC_INFO_MSDU_COUNT_MASK) >> \
118 	RX_MPDU_DESC_INFO_MSDU_COUNT_LSB)
119 
120 #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \
121 	(mpdu_info_ptr[RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET >> 2] & \
122 	RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK)
123 
124 #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \
125 	(mpdu_info_ptr[RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET >> 2] & \
126 	RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK)
127 
128 #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \
129 	(mpdu_info_ptr[RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET >> 2] & \
130 	RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK)
131 
132 #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \
133 	(mpdu_info_ptr[RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET >> 2] & \
134 	RX_MPDU_DESC_INFO_RAW_MPDU_MASK)
135 
136 #define HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info_ptr) \
137 	((mpdu_info_ptr[RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET >> 2] & \
138 	RX_MPDU_DESC_INFO_BAR_FRAME_MASK) >> \
139 	RX_MPDU_DESC_INFO_BAR_FRAME_LSB)
140 
141 #define HAL_RX_MPDU_TID_GET(mpdu_info_ptr) \
142 	((mpdu_info_ptr[RX_MPDU_DESC_INFO_TID_OFFSET >> 2] & \
143 	RX_MPDU_DESC_INFO_TID_MASK) >> \
144 	RX_MPDU_DESC_INFO_TID_LSB)
145 
146 #define HAL_RX_MPDU_MPDU_QOS_CONTROL_VALID_GET(mpdu_info_ptr) \
147 	((mpdu_info_ptr[RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET >> 2] &\
148 	RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK) >> \
149 	RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB)
150 
151 /*
152  * NOTE: None of the following _GET macros need a right
153  * shift by the corresponding _LSB. This is because, they are
154  * finally taken and "OR'ed" into a single word again.
155  */
156 #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val)		\
157 	((*(((uint32_t *)msdu_info_ptr) +				\
158 		(RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET >> 2))) |= \
159 		((val) << RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB) & \
160 		RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK)
161 
162 #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr)	\
163 	((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,			\
164 		RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET)) & \
165 		RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK)
166 
167 #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr)	\
168 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,	\
169 	RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET)),	\
170 	RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK,		\
171 	RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB))
172 
173 #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr)		\
174 	((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,			\
175 		RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET)) &	\
176 		RX_MSDU_DESC_INFO_SA_IS_VALID_MASK)
177 
178 #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr)		\
179 	((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,			\
180 		RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET)) &	\
181 		RX_MSDU_DESC_INFO_DA_IS_VALID_MASK)
182 
183 #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr)		\
184 	((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,			\
185 		RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET)) &	\
186 		RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK)
187 
188 #define HAL_RX_MSDU_INTRA_BSS_FLAG_GET(msdu_info_ptr)		\
189 	((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,			\
190 		RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET)) &	\
191 		RX_MSDU_DESC_INFO_INTRA_BSS_MASK)
192 
193 #define HAL_RX_MSDU_DEST_CHIP_ID_GET(msdu_info_ptr) \
194 	((*_OFFSET_TO_WORD_PTR(msdu_info_ptr,		\
195 		RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET)) & \
196 		RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK)
197 
198 #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info)	\
199 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info,	\
200 	RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET)),		\
201 	RX_MPDU_INFO_ENCRYPT_TYPE_MASK,		\
202 	RX_MPDU_INFO_ENCRYPT_TYPE_LSB))
203 
204 #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val)		\
205 	HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO,		\
206 			_field, _val)
207 
208 #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val)		\
209 	HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO,		\
210 			_field, _val)
211 
212 #define HAL_RX_MSDU_REO_DST_IND_SET(_msdu_ext_desc_info_ptr, _field, _val)  \
213 	HAL_RX_FLD_SET(_msdu_ext_desc_info_ptr, RX_MSDU_EXT_DESC_INFO,	    \
214 			_field, _val)
215 
216 #define HAL_RX_REO_MSDU_REO_DST_IND_GET(reo_desc)	\
217 	(HAL_RX_MSDU_REO_DST_IND_GET(&		\
218 	(((struct reo_destination_ring *)	\
219 	   reo_desc)->rx_msdu_desc_info_details)))
220 
221 #define HAL_RX_DEST_CHIP_ID_GET(msdu_metadata) \
222 	(((msdu_metadata)->da_idx >> HAL_RX_DA_IDX_CHIP_ID_OFFSET) &	\
223 	 HAL_RX_DA_IDX_CHIP_ID_MASK)
224 
225 #define HAL_RX_PEER_ID_GET(msdu_metadata) \
226 	(((msdu_metadata)->da_idx) & HAL_RX_DA_IDX_PEER_ID_MASK)
227 
228 #define HAL_RX_TLV_DEST_CHIP_ID_GET(_rx_pkt_tlv)	\
229 	HAL_RX_MSDU_END(_rx_pkt_tlv).dest_chip_id
230 
231 #ifdef INTRA_BSS_FWD_OFFLOAD
232 #define HAL_RX_TLV_DEST_CHIP_PMAC_ID_GET(_rx_pkt_tlv)	\
233 	HAL_RX_MSDU_END(_rx_pkt_tlv).dest_chip_pmac_id
234 #endif
235 
236 /**
237  * enum hal_be_rx_wbm_error_source: Indicates which module initiated the
238  * release of this buffer or descriptor
239  *
240  * @HAL_BE_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
241  * @HAL_BE_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
242  * @HAL_BE_RX_WBM_ERR_SRC_FW_RX: FW released this buffer or descriptor from the
243  *				RX path
244  * @HAL_BE_RX_WBM_ERR_SRC_SW_RX: SW released this buffer or descriptor from the
245  *				RX path
246  * @HAL_BE_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
247  * @HAL_BE_RX_WBM_ERR_SRC_FW_TX: FW released this buffer or descriptor from the
248  *				RX path
249  * @HAL_BE_RX_WBM_ERR_SRC_SW_TX: SW released this buffer or descriptor from the
250  *				RX path
251  */
252 enum hal_be_rx_wbm_error_source {
253 	HAL_BE_RX_WBM_ERR_SRC_RXDMA = 0,
254 	HAL_BE_RX_WBM_ERR_SRC_REO,
255 	HAL_BE_RX_WBM_ERR_SRC_FW_RX,
256 	HAL_BE_RX_WBM_ERR_SRC_SW_RX,
257 	HAL_BE_RX_WBM_ERR_SRC_TQM,
258 	HAL_BE_RX_WBM_ERR_SRC_FW_TX,
259 	HAL_BE_RX_WBM_ERR_SRC_SW_TX,
260 };
261 
262 /**
263  * enum hal_be_wbm_release_dir - Direction of the buffer which was released to
264  *			wbm.
265  * @HAL_BE_WBM_RELEASE_DIR_RX: Buffer released to WBM due to error
266  * @HAL_BE_WBM_RELEASE_DIR_TX: Buffer released to WBM from TX path
267  */
268 enum hal_be_wbm_release_dir {
269 	HAL_BE_WBM_RELEASE_DIR_RX,
270 	HAL_BE_WBM_RELEASE_DIR_TX,
271 };
272 
hal_rx_get_mpdu_flags(uint32_t * mpdu_info)273 static inline uint32_t hal_rx_get_mpdu_flags(uint32_t *mpdu_info)
274 {
275 	uint32_t mpdu_flags = 0;
276 
277 	if (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info))
278 		mpdu_flags |= HAL_MPDU_F_FRAGMENT;
279 
280 	if (HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info))
281 		mpdu_flags |= HAL_MPDU_F_RETRY_BIT;
282 
283 	if (HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info))
284 		mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG;
285 
286 	if (HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info))
287 		mpdu_flags |= HAL_MPDU_F_RAW_AMPDU;
288 
289 	if (HAL_RX_MPDU_MPDU_QOS_CONTROL_VALID_GET(mpdu_info))
290 		mpdu_flags |= HAL_MPDU_F_QOS_CONTROL_VALID;
291 
292 	return mpdu_flags;
293 }
294 
295 /*******************************************************************************
296  * RX REO ERROR APIS
297  ******************************************************************************/
298 
299 #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
300 		(REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \
301 		REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK) >> \
302 		REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB)
303 
304 #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
305 		(REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET >> 2))) & \
306 		REO_DESTINATION_RING_REO_ERROR_CODE_MASK) >> \
307 		REO_DESTINATION_RING_REO_ERROR_CODE_LSB)
308 
309 /*
310  * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to
311  * REO entrance ring
312  *
313  * @ soc: HAL version of the SOC pointer
314  * @ pa: Physical address of the MSDU Link Descriptor
315  * @ cookie: SW cookie to get to the virtual address
316  * @ error_enabled_reo_q: Argument to determine whether this needs to go
317  * to the error enabled REO queue
318  *
319  * Return: void
320  */
321 static inline void
hal_rx_msdu_link_desc_reinject(struct hal_soc * soc,uint64_t pa,uint32_t cookie,bool error_enabled_reo_q)322 hal_rx_msdu_link_desc_reinject(struct hal_soc *soc, uint64_t pa,
323 			       uint32_t cookie, bool error_enabled_reo_q)
324 {
325 	/* TODO */
326 }
327 
328 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
329 /* HW set dowrd-2 bit16 to 1 if HW CC is done */
330 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_OFFSET 0x8
331 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_MASK 0x10000
332 #define HAL_WBM2SW_COMPLETION_RING_RX_CC_DONE_LSB 0x10
333 /**
334  * hal_rx_wbm_get_cookie_convert_done() - Get cookie conversion done flag
335  * @hal_desc: wbm Rx ring descriptor pointer
336  *
337  * This function will get the bit value that indicate HW cookie
338  * conversion done or not
339  *
340  * Return: 1 - HW cookie conversion done, 0 - not
341  */
hal_rx_wbm_get_cookie_convert_done(void * hal_desc)342 static inline uint8_t hal_rx_wbm_get_cookie_convert_done(void *hal_desc)
343 {
344 	return HAL_RX_GET(hal_desc, HAL_WBM2SW_COMPLETION_RING_RX,
345 			  CC_DONE);
346 }
347 #endif
348 
349 /**
350  * hal_rx_wbm_get_desc_va() - Get Desc virtual address within WBM Desc
351  * @hal_desc: RX WBM2SW ring descriptor pointer
352  *
353  * Return: RX descriptor virtual address
354  */
hal_rx_wbm_get_desc_va(void * hal_desc)355 static inline uintptr_t hal_rx_wbm_get_desc_va(void *hal_desc)
356 {
357 	uint64_t va_from_desc;
358 
359 	va_from_desc = qdf_le64_to_cpu(HAL_RX_GET(hal_desc,
360 				       WBM2SW_COMPLETION_RING_RX,
361 				       BUFFER_VIRT_ADDR_31_0) |
362 				       (((uint64_t)HAL_RX_GET(hal_desc,
363 				       WBM2SW_COMPLETION_RING_RX,
364 				       BUFFER_VIRT_ADDR_63_32)) << 32));
365 	return (uintptr_t)va_from_desc;
366 }
367 
368 #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc)		\
369 	(((*(((uint32_t *)wbm_desc) +			\
370 	(WBM_RELEASE_RING_FIRST_MSDU_OFFSET >> 2))) & \
371 	WBM_RELEASE_RING_FIRST_MSDU_MASK) >>		\
372 	WBM_RELEASE_RING_FIRST_MSDU_LSB)
373 
374 #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc)		\
375 	(((*(((uint32_t *)wbm_desc) +			\
376 	(WBM_RELEASE_RING_LAST_MSDU_OFFSET >> 2))) &  \
377 	WBM_RELEASE_RING_LAST_MSDU_MASK) >>		\
378 	WBM_RELEASE_RING_LAST_MSDU_LSB)
379 
380 #define HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_desc)	\
381 	(HAL_RX_BUFFER_ADDR_39_32_GET(&			\
382 	(((struct wbm_release_ring_rx *) \
383 	wbm_desc)->released_buff_or_desc_addr_info)))
384 
385 #define HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_desc)	\
386 	(HAL_RX_BUFFER_ADDR_31_0_GET(&			\
387 	(((struct wbm_release_ring_rx *) \
388 	wbm_desc)->released_buff_or_desc_addr_info)))
389 
390 #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \
391 	HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring_rx *) \
392 	wbm_desc)->released_buff_or_desc_addr_info)
393 
394 #define HAL_RX_WBM_COMP_BUF_ADDR_31_0_GET(wbm_desc) \
395 	HAL_RX_GET(wbm_desc, WBM2SW_COMPLETION_RING_RX, BUFFER_PHYS_ADDR_31_0)
396 
397 #define HAL_RX_WBM_COMP_BUF_ADDR_39_32_GET(wbm_desc) \
398 	HAL_RX_GET(wbm_desc, WBM2SW_COMPLETION_RING_RX, BUFFER_PHYS_ADDR_39_32)
399 
400 #define HAL_RX_WBM_COMP_BUF_COOKIE_GET(wbm_desc) \
401 	HAL_RX_GET(wbm_desc, WBM2SW_COMPLETION_RING_RX, SW_BUFFER_COOKIE)
402 /**
403  * hal_rx_msdu_flags_get_be() - Get msdu flags from ring desc
404  * @msdu_desc_info_hdl: msdu desc info handle
405  *
406  * Return: msdu flags
407  */
408 static inline
hal_rx_msdu_flags_get_be(rx_msdu_desc_info_t msdu_desc_info_hdl)409 uint32_t hal_rx_msdu_flags_get_be(rx_msdu_desc_info_t msdu_desc_info_hdl)
410 {
411 	struct rx_msdu_desc_info *msdu_desc_info =
412 		(struct rx_msdu_desc_info *)msdu_desc_info_hdl;
413 	uint32_t flags = 0;
414 
415 	if (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_desc_info))
416 		flags |= HAL_MSDU_F_FIRST_MSDU_IN_MPDU;
417 
418 	if (HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_desc_info))
419 		flags |= HAL_MSDU_F_LAST_MSDU_IN_MPDU;
420 
421 	if (HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_desc_info))
422 		flags |= HAL_MSDU_F_MSDU_CONTINUATION;
423 
424 	if (HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_desc_info))
425 		flags |= HAL_MSDU_F_SA_IS_VALID;
426 
427 	if (HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_desc_info))
428 		flags |= HAL_MSDU_F_DA_IS_VALID;
429 
430 	if (HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_desc_info))
431 		flags |= HAL_MSDU_F_DA_IS_MCBC;
432 
433 	if (HAL_RX_MSDU_INTRA_BSS_FLAG_GET(msdu_desc_info))
434 		flags |= HAL_MSDU_F_INTRA_BSS;
435 
436 	return flags;
437 }
438 
439 static inline
hal_rx_mpdu_desc_info_get_be(void * desc_addr,void * mpdu_desc_info_hdl)440 void hal_rx_mpdu_desc_info_get_be(void *desc_addr,
441 				  void *mpdu_desc_info_hdl)
442 {
443 	struct reo_destination_ring *reo_dst_ring;
444 	struct hal_rx_mpdu_desc_info *mpdu_desc_info =
445 		(struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl;
446 	uint32_t *mpdu_info;
447 
448 	reo_dst_ring = (struct reo_destination_ring *)desc_addr;
449 
450 	mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details;
451 
452 	mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
453 	mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags(mpdu_info);
454 	mpdu_desc_info->peer_meta_data =
455 		HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info);
456 	mpdu_desc_info->bar_frame = HAL_RX_MPDU_BAR_FRAME_GET(mpdu_info);
457 	mpdu_desc_info->tid = HAL_RX_MPDU_TID_GET(mpdu_info);
458 }
459 
460 /*
461  *hal_rx_msdu_desc_info_get_be: Gets the flags related to MSDU descriptor.
462  *@desc_addr: REO ring descriptor addr
463  *@msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor
464  *
465  * Specifically flags needed are: first_msdu_in_mpdu,
466  * last_msdu_in_mpdu, msdu_continuation, sa_is_valid,
467  * sa_idx_timeout, da_is_valid, da_idx_timeout, da_is_MCBC
468  *
469 
470  *Return: void
471  */
472 static inline void
hal_rx_msdu_desc_info_get_be(void * desc_addr,struct hal_rx_msdu_desc_info * msdu_desc_info)473 hal_rx_msdu_desc_info_get_be(void *desc_addr,
474 			     struct hal_rx_msdu_desc_info *msdu_desc_info)
475 {
476 	struct reo_destination_ring *reo_dst_ring;
477 	uint32_t *msdu_info;
478 
479 	reo_dst_ring = (struct reo_destination_ring *)desc_addr;
480 
481 	msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details;
482 	msdu_desc_info->msdu_flags =
483 		hal_rx_msdu_flags_get_be((struct rx_msdu_desc_info *)msdu_info);
484 	msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
485 }
486 
487 /**
488  * hal_rx_get_reo_desc_va() - Get Desc virtual address within REO Desc
489  * @reo_desc: REO2SW ring descriptor pointer
490  *
491  * Return: RX descriptor virtual address
492  */
hal_rx_get_reo_desc_va(void * reo_desc)493 static inline uintptr_t hal_rx_get_reo_desc_va(void *reo_desc)
494 {
495 	uint64_t va_from_desc;
496 
497 	va_from_desc = qdf_le64_to_cpu(HAL_RX_GET(reo_desc,
498 				       REO_DESTINATION_RING,
499 				       BUFFER_VIRT_ADDR_31_0) |
500 				       (((uint64_t)HAL_RX_GET(reo_desc,
501 				       REO_DESTINATION_RING,
502 				       BUFFER_VIRT_ADDR_63_32)) << 32));
503 	return (uintptr_t)va_from_desc;
504 }
505 
506 /**
507  * hal_rx_sw_exception_get_be() - Get sw_exception bit value from REO Desc
508  * @reo_desc: REO2SW ring descriptor pointer
509  *
510  * sw_exception bit might not exist in reo destination ring descriptor
511  * for some chipset, so just restrict this function for BE only.
512  *
513  * Return: sw_exception bit value
514  */
hal_rx_sw_exception_get_be(void * reo_desc)515 static inline uint8_t hal_rx_sw_exception_get_be(void *reo_desc)
516 {
517 	return HAL_RX_GET(reo_desc, REO_DESTINATION_RING, SW_EXCEPTION);
518 }
519 
520 #ifdef INTRA_BSS_FWD_OFFLOAD
521 /**
522  * hal_rx_tlv_get_dest_chip_pmac_id() - Get destination chip and PMAC ID
523  * @buf: Rx TLV buffer
524  * @d_chip_id: chip id being filled in
525  * @d_chip_pmac_id: chip pmac id being filled in
526  *
527  * Return: void
528  */
529 static inline void
hal_rx_tlv_get_dest_chip_pmac_id(uint8_t * buf,uint8_t * d_chip_id,uint8_t * d_chip_pmac_id)530 hal_rx_tlv_get_dest_chip_pmac_id(uint8_t *buf,
531 				 uint8_t *d_chip_id, uint8_t *d_chip_pmac_id)
532 {
533 	struct rx_pkt_tlvs *rx_pkt_tlvs = (struct rx_pkt_tlvs *)buf;
534 
535 	*d_chip_id = HAL_RX_TLV_DEST_CHIP_ID_GET(rx_pkt_tlvs);
536 	*d_chip_pmac_id = HAL_RX_TLV_DEST_CHIP_PMAC_ID_GET(rx_pkt_tlvs);
537 }
538 #endif /* INTRA_BSS_FWD_OFFLOAD */
539 
hal_rx_get_reo_push_rsn(void * desc_addr)540 static inline uint8_t hal_rx_get_reo_push_rsn(void *desc_addr)
541 {
542 	struct reo_destination_ring *reo_dst_ring;
543 
544 	reo_dst_ring = (struct reo_destination_ring *)desc_addr;
545 	return reo_dst_ring->reo_push_reason;
546 }
547 
548 /**
549  * hal_rx_get_mpdu_msdu_desc_info_be() - get msdu, mpdu, peer meta data info
550  *					 from HAL Desc.
551  * @desc_addr: REO ring descriptor addr
552  * @mpdu_info: pointer to MPDU info
553  * @peer_mdata: pointer to peer meta data info
554  * @msdu_info: pointer to msdu info
555  *
556  * Return: void
557  */
558 static inline void
hal_rx_get_mpdu_msdu_desc_info_be(void * desc_addr,uint32_t * mpdu_info,uint32_t * peer_mdata,uint32_t * msdu_info)559 hal_rx_get_mpdu_msdu_desc_info_be(void *desc_addr,
560 				  uint32_t *mpdu_info,
561 				  uint32_t *peer_mdata,
562 				  uint32_t *msdu_info)
563 {
564 	struct reo_destination_ring *reo_dst_ring;
565 
566 	reo_dst_ring = (struct reo_destination_ring *)desc_addr;
567 	*mpdu_info = *(uint32_t *)(&reo_dst_ring->rx_mpdu_desc_info_details);
568 	*peer_mdata = *((uint32_t *)
569 			&reo_dst_ring->rx_mpdu_desc_info_details + 1);
570 	*msdu_info = *(uint32_t *)(&reo_dst_ring->rx_msdu_desc_info_details);
571 }
572 
573 /**
574  * hal_rx_wbm_err_mpdu_msdu_info_get_be() - Copies wbm, msdu, mpdu info
575  *                                          from HAL desc
576  * @desc_addr: WBM2SW Rx Error ring descriptor addr
577  * @wbm_err_info: Holds WBM Error info from HAL Rx descriptor
578  * @mpdu_info: Holds MPDU descriptor info from HAL Rx descriptor
579  * @msdu_info: Holds MSDU descriptor info from HAL Rx descriptor
580  * @peer_meta_data: Holds Peer Meta data from HAL Rx descriptor
581  *
582  * This function copies the WBM error information, MSDU desc info,
583  * MPDU Desc info and peer meta data from HAL RX Desc.
584  *
585  * Return: void
586  */
587 static inline void
hal_rx_wbm_err_mpdu_msdu_info_get_be(void * desc_addr,uint32_t * wbm_err_info,uint32_t * mpdu_info,uint32_t * msdu_info,uint32_t * peer_meta_data)588 hal_rx_wbm_err_mpdu_msdu_info_get_be(void *desc_addr,
589 				     uint32_t *wbm_err_info,
590 				     uint32_t *mpdu_info,
591 				     uint32_t *msdu_info,
592 				     uint32_t *peer_meta_data)
593 {
594 	struct wbm2sw_completion_ring_rx *wbm_rx_err_ring;
595 
596 	wbm_rx_err_ring = (struct wbm2sw_completion_ring_rx *)desc_addr;
597 	*msdu_info = *(uint32_t *)&wbm_rx_err_ring->rx_msdu_desc_info_details;
598 	*mpdu_info = *(uint32_t *)&wbm_rx_err_ring->rx_mpdu_desc_info_details;
599 	*peer_meta_data =
600 		*((uint32_t *)&wbm_rx_err_ring->rx_mpdu_desc_info_details + 1);
601 	*wbm_err_info = *((uint32_t *)wbm_rx_err_ring + 2);
602 }
603 #endif /* _HAL_BE_RX_H_ */
604