xref: /wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/hal_rx_hw_defines.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021,2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _HAL_RX_HW_DEFINES_H_
21 #define _HAL_RX_HW_DEFINES_H_
22 
23 /* Unified 32-bit desc fields */
24 #define HAL_RX_USER_TLV32_TYPE_OFFSET		0x00000000
25 #define HAL_RX_USER_TLV32_TYPE_LSB		1
26 #define HAL_RX_USER_TLV32_TYPE_MASK		0x000003FE
27 
28 #define HAL_RX_USER_TLV32_LEN_OFFSET		0x00000000
29 #define HAL_RX_USER_TLV32_LEN_LSB		10
30 #define HAL_RX_USER_TLV32_LEN_MASK		0x003FFC00
31 
32 #define HAL_RX_USER_TLV32_USERID_OFFSET		0x00000000
33 #define HAL_RX_USER_TLV32_USERID_LSB		26
34 #define HAL_RX_USER_TLV32_USERID_MASK		0xFC000000
35 
36 /* rx mpdu desc info */
37 #define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET		0x0
38 #define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_LSB		0
39 #define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_MASK		0x000000ff
40 
41 /* reo entrance ring */
42 #define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET	0x1c
43 #define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_LSB		28
44 #define HAL_REO_ENTRANCE_RING_LOOPING_COUNT_MASK	0xf0000000
45 
46 #define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET		0x18
47 #define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB		0
48 #define HAL_REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK		0x00000003
49 
50 #define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET		0x18
51 #define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB		2
52 #define HAL_REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK		0x0000007c
53 
54 #define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET	0x8
55 #define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB	0
56 #define HAL_SW2WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK	0x00000007
57 
58 #define HAL_SW2WBM_RELEASE_RING_BM_ACTION_OFFSET		0x8
59 #define HAL_SW2WBM_RELEASE_RING_BM_ACTION_LSB			3
60 #define HAL_SW2WBM_RELEASE_RING_BM_ACTION_MASK			0x00000038
61 
62 #define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET	0x8
63 #define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB		6
64 #define HAL_SW2WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK	0x000001c0
65 
66 /* REO CMD entry offsets */
67 #define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET	0x0
68 #define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB		0
69 #define HAL_UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK		0x0000ffff
70 
71 #define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET		0x00000000
72 #define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB			0
73 #define HAL_UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK		0x0000000f
74 
75 #define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET	0x00000000
76 #define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB		4
77 #define HAL_UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK		0x000000f0
78 
79 #define HAL_WBM_INTERNAL_ERROR_OFFSET		0x8
80 #define HAL_WBM_INTERNAL_ERROR_LSB		31
81 #define HAL_WBM_INTERNAL_ERROR_MASK		0x80000000
82 
83 #define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_OFFSET	0x8
84 #define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_LSB	6
85 #define WBM_ERR_RING_BUFFER_OR_DESC_TYPE_MASK	0x000001c0
86 
87 /* RX Flow search entry MACROS */
88 #define HAL_RX_FLOW_SEARCH_ENTRY_VALID_OFFSET			0x00000024
89 #define HAL_RX_FLOW_SEARCH_ENTRY_VALID_LSB			8
90 #define HAL_RX_FLOW_SEARCH_ENTRY_VALID_MASK			0x00000100
91 
92 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET		0x00000000
93 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB		0
94 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK		0xffffffff
95 
96 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET		0x00000004
97 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB		0
98 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK		0xffffffff
99 
100 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET		0x00000008
101 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB		0
102 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK		0xffffffff
103 
104 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET		0x0000000c
105 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB		0
106 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK		0xffffffff
107 
108 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET		0x00000010
109 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB		0
110 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK		0xffffffff
111 
112 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET		0x00000014
113 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB		0
114 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK		0xffffffff
115 
116 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET		0x00000018
117 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB		0
118 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK		0xffffffff
119 
120 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET		0x0000001c
121 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB		0
122 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK		0xffffffff
123 
124 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET		0x00000020
125 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB			16
126 #define HAL_RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK			0xffff0000
127 
128 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET		0x00000020
129 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB			0
130 #define HAL_RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK			0x0000ffff
131 
132 #define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET		0x00000024
133 #define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB		0
134 #define HAL_RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK		0x000000ff
135 
136 #endif /* _HAL_RX_HW_DEFINES_H_ */
137