1 /*
2 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include "qdf_types.h"
21 #include "qdf_util.h"
22 #include "qdf_types.h"
23 #include "qdf_lock.h"
24 #include "qdf_mem.h"
25 #include "qdf_nbuf.h"
26 #include "hal_hw_headers.h"
27 #include "hal_internal.h"
28 #include "hal_api.h"
29 #include "target_type.h"
30 #include "wcss_version.h"
31 #include "qdf_module.h"
32 #include "hal_flow.h"
33 #include "rx_flow_search_entry.h"
34 #include "hal_rx_flow_info.h"
35 #include "hal_be_api.h"
36 #include "reo_destination_ring_with_pn.h"
37 #include "rx_reo_queue_1k.h"
38
39 #include <hal_be_rx.h>
40
41 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
42 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET
43 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
44 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK
45 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
46 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB
47 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
48 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
49 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
50 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
51 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
52 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
53 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
54 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
55 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
56 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
57 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
58 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
59 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
60 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
61 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
62 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
63 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
64 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
65 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
66 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
67 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
68 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
69 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
70 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET
71 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
72 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
73 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
74 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
75 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
76 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
77 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
78 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
79 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
80 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
81 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
82 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
83 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
84 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
85 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
86 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
88 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
92 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
93 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
94 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
96 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
97 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
98 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
100 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
101 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
102 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
104 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
105 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
106 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
108 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
109 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
110 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
112 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
114 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
115 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
116 WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
117
118 #include "hal_kiwi_tx.h"
119 #include "hal_kiwi_rx.h"
120
121 #include "hal_be_rx_tlv.h"
122
123 #include <hal_generic_api.h>
124 #include "hal_be_api_mon.h"
125 #include <hal_be_generic_api.h>
126
127 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
128
129 /* For Berryllium sw2rxdma ring size increased to 20 bits */
130 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
131
132 #ifdef QCA_GET_TSF_VIA_REG
133 #define PCIE_PCIE_MHI_TIME_LOW 0xA28
134 #define PCIE_PCIE_MHI_TIME_HIGH 0xA2C
135
136 #define PMM_REG_BASE 0xB500FC
137
138 #define FW_QTIME_CYCLES_PER_10_USEC 192
139 #endif
140
141 struct wbm2sw_completion_ring_tx gwbm2sw_tx_comp_symbol __attribute__((used));
142 struct wbm2sw_completion_ring_rx gwbm2sw_rx_comp_symbol __attribute__((used));
143
hal_get_link_desc_size_kiwi(void)144 static uint32_t hal_get_link_desc_size_kiwi(void)
145 {
146 return LINK_DESC_SIZE;
147 }
148
149 /**
150 * hal_rx_dump_msdu_end_tlv_kiwi() - dump RX msdu_end TLV in structured
151 * human readable format.
152 * @msduend: pointer the msdu_end TLV in pkt.
153 * @dbg_level: log level.
154 *
155 * Return: void
156 */
157 #ifdef QCA_WIFI_KIWI_V2
hal_rx_dump_msdu_end_tlv_kiwi(void * msduend,uint8_t dbg_level)158 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend,
159 uint8_t dbg_level)
160 {
161 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
162
163 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
164 "rx_msdu_end tlv (1/5)- "
165 "rxpcu_mpdu_filter_in_category :%x "
166 "sw_frame_group_id :%x "
167 "reserved_0 :%x "
168 "phy_ppdu_id :%x "
169 "ip_hdr_chksum :%x "
170 "reported_mpdu_length :%x "
171 "reserved_1a :%x "
172 "reserved_2a :%x "
173 "cce_super_rule :%x "
174 "cce_classify_not_done_truncate :%x "
175 "cce_classify_not_done_cce_dis :%x "
176 "cumulative_l3_checksum :%x "
177 "rule_indication_31_0 :%x "
178 "ipv6_options_crc :%x "
179 "da_offset :%x "
180 "sa_offset :%x "
181 "da_offset_valid :%x "
182 "sa_offset_valid :%x "
183 "reserved_5a :%x "
184 "l3_type :%x",
185 msdu_end->rxpcu_mpdu_filter_in_category,
186 msdu_end->sw_frame_group_id,
187 msdu_end->reserved_0,
188 msdu_end->phy_ppdu_id,
189 msdu_end->ip_hdr_chksum,
190 msdu_end->reported_mpdu_length,
191 msdu_end->reserved_1a,
192 msdu_end->reserved_2a,
193 msdu_end->cce_super_rule,
194 msdu_end->cce_classify_not_done_truncate,
195 msdu_end->cce_classify_not_done_cce_dis,
196 msdu_end->cumulative_l3_checksum,
197 msdu_end->rule_indication_31_0,
198 msdu_end->ipv6_options_crc,
199 msdu_end->da_offset,
200 msdu_end->sa_offset,
201 msdu_end->da_offset_valid,
202 msdu_end->sa_offset_valid,
203 msdu_end->reserved_5a,
204 msdu_end->l3_type);
205
206 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
207 "rx_msdu_end tlv (2/5)- "
208 "rule_indication_63_32 :%x "
209 "tcp_seq_number :%x "
210 "tcp_ack_number :%x "
211 "tcp_flag :%x "
212 "lro_eligible :%x "
213 "reserved_9a :%x "
214 "window_size :%x "
215 "sa_sw_peer_id :%x "
216 "sa_idx_timeout :%x "
217 "da_idx_timeout :%x "
218 "to_ds :%x "
219 "tid :%x "
220 "sa_is_valid :%x "
221 "da_is_valid :%x "
222 "da_is_mcbc :%x "
223 "l3_header_padding :%x "
224 "first_msdu :%x "
225 "last_msdu :%x "
226 "fr_ds :%x "
227 "ip_chksum_fail_copy :%x "
228 "sa_idx :%x "
229 "da_idx_or_sw_peer_id :%x",
230 msdu_end->rule_indication_63_32,
231 msdu_end->tcp_seq_number,
232 msdu_end->tcp_ack_number,
233 msdu_end->tcp_flag,
234 msdu_end->lro_eligible,
235 msdu_end->reserved_9a,
236 msdu_end->window_size,
237 msdu_end->sa_sw_peer_id,
238 msdu_end->sa_idx_timeout,
239 msdu_end->da_idx_timeout,
240 msdu_end->to_ds,
241 msdu_end->tid,
242 msdu_end->sa_is_valid,
243 msdu_end->da_is_valid,
244 msdu_end->da_is_mcbc,
245 msdu_end->l3_header_padding,
246 msdu_end->first_msdu,
247 msdu_end->last_msdu,
248 msdu_end->fr_ds,
249 msdu_end->ip_chksum_fail_copy,
250 msdu_end->sa_idx,
251 msdu_end->da_idx_or_sw_peer_id);
252
253 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
254 "rx_msdu_end tlv (3/5)- "
255 "msdu_drop :%x "
256 "reo_destination_indication :%x "
257 "flow_idx :%x "
258 "use_ppe :%x "
259 "vlan_ctag_stripped :%x "
260 "vlan_stag_stripped :%x "
261 "fragment_flag :%x "
262 "fse_metadata :%x "
263 "cce_metadata :%x "
264 "tcp_udp_chksum :%x "
265 "aggregation_count :%x "
266 "flow_aggregation_continuation :%x "
267 "fisa_timeout :%x "
268 "tcp_udp_chksum_fail_copy :%x "
269 "msdu_limit_error :%x "
270 "flow_idx_timeout :%x "
271 "flow_idx_invalid :%x "
272 "cce_match :%x "
273 "amsdu_parser_error :%x "
274 "cumulative_ip_length :%x "
275 "key_id_octet :%x "
276 "reserved_16a :%x "
277 "reserved_17a :%x "
278 "service_code :%x "
279 "priority_valid :%x "
280 "intra_bss :%x "
281 "dest_chip_id :%x "
282 "multicast_echo :%x "
283 "wds_learning_event :%x "
284 "wds_roaming_event :%x "
285 "wds_keep_alive_event :%x "
286 "reserved_17b :%x",
287 msdu_end->msdu_drop,
288 msdu_end->reo_destination_indication,
289 msdu_end->flow_idx,
290 msdu_end->use_ppe,
291 msdu_end->vlan_ctag_stripped,
292 msdu_end->vlan_stag_stripped,
293 msdu_end->fragment_flag,
294 msdu_end->fse_metadata,
295 msdu_end->cce_metadata,
296 msdu_end->tcp_udp_chksum,
297 msdu_end->aggregation_count,
298 msdu_end->flow_aggregation_continuation,
299 msdu_end->fisa_timeout,
300 msdu_end->tcp_udp_chksum_fail_copy,
301 msdu_end->msdu_limit_error,
302 msdu_end->flow_idx_timeout,
303 msdu_end->flow_idx_invalid,
304 msdu_end->cce_match,
305 msdu_end->amsdu_parser_error,
306 msdu_end->cumulative_ip_length,
307 msdu_end->key_id_octet,
308 msdu_end->reserved_16a,
309 msdu_end->reserved_17a,
310 msdu_end->service_code,
311 msdu_end->priority_valid,
312 msdu_end->intra_bss,
313 msdu_end->dest_chip_id,
314 msdu_end->multicast_echo,
315 msdu_end->wds_learning_event,
316 msdu_end->wds_roaming_event,
317 msdu_end->wds_keep_alive_event,
318 msdu_end->reserved_17b);
319
320 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
321 "rx_msdu_end tlv (4/5)- "
322 "msdu_length :%x "
323 "stbc :%x "
324 "ipsec_esp :%x "
325 "l3_offset :%x "
326 "ipsec_ah :%x "
327 "l4_offset :%x "
328 "msdu_number :%x "
329 "decap_format :%x "
330 "ipv4_proto :%x "
331 "ipv6_proto :%x "
332 "tcp_proto :%x "
333 "udp_proto :%x "
334 "ip_frag :%x "
335 "tcp_only_ack :%x "
336 "da_is_bcast_mcast :%x "
337 "toeplitz_hash_sel :%x "
338 "ip_fixed_header_valid :%x "
339 "ip_extn_header_valid :%x "
340 "tcp_udp_header_valid :%x "
341 "mesh_control_present :%x "
342 "ldpc :%x "
343 "ip4_protocol_ip6_next_header :%x "
344 "vlan_ctag_ci :%x "
345 "vlan_stag_ci :%x "
346 "peer_meta_data :%x "
347 "user_rssi :%x "
348 "pkt_type :%x "
349 "sgi :%x "
350 "rate_mcs :%x "
351 "receive_bandwidth :%x "
352 "reception_type :%x "
353 "mimo_ss_bitmap :%x "
354 "msdu_done_copy :%x "
355 "flow_id_toeplitz :%x",
356 msdu_end->msdu_length,
357 msdu_end->stbc,
358 msdu_end->ipsec_esp,
359 msdu_end->l3_offset,
360 msdu_end->ipsec_ah,
361 msdu_end->l4_offset,
362 msdu_end->msdu_number,
363 msdu_end->decap_format,
364 msdu_end->ipv4_proto,
365 msdu_end->ipv6_proto,
366 msdu_end->tcp_proto,
367 msdu_end->udp_proto,
368 msdu_end->ip_frag,
369 msdu_end->tcp_only_ack,
370 msdu_end->da_is_bcast_mcast,
371 msdu_end->toeplitz_hash_sel,
372 msdu_end->ip_fixed_header_valid,
373 msdu_end->ip_extn_header_valid,
374 msdu_end->tcp_udp_header_valid,
375 msdu_end->mesh_control_present,
376 msdu_end->ldpc,
377 msdu_end->ip4_protocol_ip6_next_header,
378 msdu_end->vlan_ctag_ci,
379 msdu_end->vlan_stag_ci,
380 msdu_end->peer_meta_data,
381 msdu_end->user_rssi,
382 msdu_end->pkt_type,
383 msdu_end->sgi,
384 msdu_end->rate_mcs,
385 msdu_end->receive_bandwidth,
386 msdu_end->reception_type,
387 msdu_end->mimo_ss_bitmap,
388 msdu_end->msdu_done_copy,
389 msdu_end->flow_id_toeplitz);
390
391 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
392 "rx_msdu_end tlv (5/5)- "
393 "ppdu_start_timestamp_63_32 :%x "
394 "sw_phy_meta_data :%x "
395 "ppdu_start_timestamp_31_0 :%x "
396 "toeplitz_hash_2_or_4 :%x "
397 "reserved_28a :%x "
398 "sa_15_0 :%x "
399 "sa_47_16 :%x "
400 "first_mpdu :%x "
401 "reserved_30a :%x "
402 "mcast_bcast :%x "
403 "ast_index_not_found :%x "
404 "ast_index_timeout :%x "
405 "power_mgmt :%x "
406 "non_qos :%x "
407 "null_data :%x "
408 "mgmt_type :%x "
409 "ctrl_type :%x "
410 "more_data :%x "
411 "eosp :%x "
412 "a_msdu_error :%x "
413 "reserved_30b :%x "
414 "order :%x "
415 "wifi_parser_error :%x "
416 "overflow_err :%x "
417 "msdu_length_err :%x "
418 "tcp_udp_chksum_fail :%x "
419 "ip_chksum_fail :%x "
420 "sa_idx_invalid :%x "
421 "da_idx_invalid :%x "
422 "amsdu_addr_mismatch :%x "
423 "rx_in_tx_decrypt_byp :%x "
424 "encrypt_required :%x "
425 "directed :%x "
426 "buffer_fragment :%x "
427 "mpdu_length_err :%x "
428 "tkip_mic_err :%x "
429 "decrypt_err :%x "
430 "unencrypted_frame_err :%x "
431 "fcs_err :%x "
432 "reserved_31a :%x "
433 "decrypt_status_code :%x "
434 "rx_bitmap_not_updated :%x "
435 "reserved_31b :%x "
436 "msdu_done :%x",
437 msdu_end->ppdu_start_timestamp_63_32,
438 msdu_end->sw_phy_meta_data,
439 msdu_end->ppdu_start_timestamp_31_0,
440 msdu_end->toeplitz_hash_2_or_4,
441 msdu_end->reserved_28a,
442 msdu_end->sa_15_0,
443 msdu_end->sa_47_16,
444 msdu_end->first_mpdu,
445 msdu_end->reserved_30a,
446 msdu_end->mcast_bcast,
447 msdu_end->ast_index_not_found,
448 msdu_end->ast_index_timeout,
449 msdu_end->power_mgmt,
450 msdu_end->non_qos,
451 msdu_end->null_data,
452 msdu_end->mgmt_type,
453 msdu_end->ctrl_type,
454 msdu_end->more_data,
455 msdu_end->eosp,
456 msdu_end->a_msdu_error,
457 msdu_end->reserved_30b,
458 msdu_end->order,
459 msdu_end->wifi_parser_error,
460 msdu_end->overflow_err,
461 msdu_end->msdu_length_err,
462 msdu_end->tcp_udp_chksum_fail,
463 msdu_end->ip_chksum_fail,
464 msdu_end->sa_idx_invalid,
465 msdu_end->da_idx_invalid,
466 msdu_end->amsdu_addr_mismatch,
467 msdu_end->rx_in_tx_decrypt_byp,
468 msdu_end->encrypt_required,
469 msdu_end->directed,
470 msdu_end->buffer_fragment,
471 msdu_end->mpdu_length_err,
472 msdu_end->tkip_mic_err,
473 msdu_end->decrypt_err,
474 msdu_end->unencrypted_frame_err,
475 msdu_end->fcs_err,
476 msdu_end->reserved_31a,
477 msdu_end->decrypt_status_code,
478 msdu_end->rx_bitmap_not_updated,
479 msdu_end->reserved_31b,
480 msdu_end->msdu_done);
481 }
482 #else
hal_rx_dump_msdu_end_tlv_kiwi(void * msduend,uint8_t dbg_level)483 static void hal_rx_dump_msdu_end_tlv_kiwi(void *msduend,
484 uint8_t dbg_level)
485 {
486 struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend;
487
488 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
489 "rx_msdu_end tlv (1/7)- "
490 "rxpcu_mpdu_filter_in_category :%x"
491 "sw_frame_group_id :%x"
492 "reserved_0 :%x"
493 "phy_ppdu_id :%x"
494 "ip_hdr_chksum:%x"
495 "reported_mpdu_length :%x"
496 "reserved_1a :%x"
497 "key_id_octet :%x"
498 "cce_super_rule :%x"
499 "cce_classify_not_done_truncate :%x"
500 "cce_classify_not_done_cce_dis:%x"
501 "cumulative_l3_checksum :%x"
502 "rule_indication_31_0 :%x"
503 "rule_indication_63_32:%x"
504 "da_offset :%x"
505 "sa_offset :%x"
506 "da_offset_valid :%x"
507 "sa_offset_valid :%x"
508 "reserved_5a :%x"
509 "l3_type :%x",
510 msdu_end->rxpcu_mpdu_filter_in_category,
511 msdu_end->sw_frame_group_id,
512 msdu_end->reserved_0,
513 msdu_end->phy_ppdu_id,
514 msdu_end->ip_hdr_chksum,
515 msdu_end->reported_mpdu_length,
516 msdu_end->reserved_1a,
517 msdu_end->key_id_octet,
518 msdu_end->cce_super_rule,
519 msdu_end->cce_classify_not_done_truncate,
520 msdu_end->cce_classify_not_done_cce_dis,
521 msdu_end->cumulative_l3_checksum,
522 msdu_end->rule_indication_31_0,
523 msdu_end->rule_indication_63_32,
524 msdu_end->da_offset,
525 msdu_end->sa_offset,
526 msdu_end->da_offset_valid,
527 msdu_end->sa_offset_valid,
528 msdu_end->reserved_5a,
529 msdu_end->l3_type);
530
531 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
532 "rx_msdu_end tlv (2/7)- "
533 "ipv6_options_crc :%x"
534 "tcp_seq_number :%x"
535 "tcp_ack_number :%x"
536 "tcp_flag :%x"
537 "lro_eligible :%x"
538 "reserved_9a :%x"
539 "window_size :%x"
540 "tcp_udp_chksum :%x"
541 "sa_idx_timeout :%x"
542 "da_idx_timeout :%x"
543 "msdu_limit_error :%x"
544 "flow_idx_timeout :%x"
545 "flow_idx_invalid :%x"
546 "wifi_parser_error :%x"
547 "amsdu_parser_error :%x"
548 "sa_is_valid :%x"
549 "da_is_valid :%x"
550 "da_is_mcbc :%x"
551 "l3_header_padding :%x"
552 "first_msdu :%x"
553 "last_msdu :%x",
554 msdu_end->ipv6_options_crc,
555 msdu_end->tcp_seq_number,
556 msdu_end->tcp_ack_number,
557 msdu_end->tcp_flag,
558 msdu_end->lro_eligible,
559 msdu_end->reserved_9a,
560 msdu_end->window_size,
561 msdu_end->tcp_udp_chksum,
562 msdu_end->sa_idx_timeout,
563 msdu_end->da_idx_timeout,
564 msdu_end->msdu_limit_error,
565 msdu_end->flow_idx_timeout,
566 msdu_end->flow_idx_invalid,
567 msdu_end->wifi_parser_error,
568 msdu_end->amsdu_parser_error,
569 msdu_end->sa_is_valid,
570 msdu_end->da_is_valid,
571 msdu_end->da_is_mcbc,
572 msdu_end->l3_header_padding,
573 msdu_end->first_msdu,
574 msdu_end->last_msdu);
575
576 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
577 "rx_msdu_end tlv (3/7)"
578 "tcp_udp_chksum_fail_copy :%x"
579 "ip_chksum_fail_copy :%x"
580 "sa_idx :%x"
581 "da_idx_or_sw_peer_id :%x"
582 "msdu_drop :%x"
583 "reo_destination_indication :%x"
584 "flow_idx :%x"
585 "reserved_12a :%x"
586 "fse_metadata :%x"
587 "cce_metadata :%x"
588 "sa_sw_peer_id:%x"
589 "aggregation_count :%x"
590 "flow_aggregation_continuation:%x"
591 "fisa_timeout :%x"
592 "reserved_15a :%x"
593 "cumulative_l4_checksum :%x"
594 "cumulative_ip_length :%x"
595 "service_code :%x"
596 "priority_valid :%x",
597 msdu_end->tcp_udp_chksum_fail_copy,
598 msdu_end->ip_chksum_fail_copy,
599 msdu_end->sa_idx,
600 msdu_end->da_idx_or_sw_peer_id,
601 msdu_end->msdu_drop,
602 msdu_end->reo_destination_indication,
603 msdu_end->flow_idx,
604 msdu_end->reserved_12a,
605 msdu_end->fse_metadata,
606 msdu_end->cce_metadata,
607 msdu_end->sa_sw_peer_id,
608 msdu_end->aggregation_count,
609 msdu_end->flow_aggregation_continuation,
610 msdu_end->fisa_timeout,
611 msdu_end->reserved_15a,
612 msdu_end->cumulative_l4_checksum,
613 msdu_end->cumulative_ip_length,
614 msdu_end->service_code,
615 msdu_end->priority_valid);
616
617 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
618 "rx_msdu_end tlv (4/7)"
619 "reserved_17a :%x"
620 "msdu_length :%x"
621 "ipsec_esp :%x"
622 "l3_offset :%x"
623 "ipsec_ah :%x"
624 "l4_offset :%x"
625 "msdu_number :%x"
626 "decap_format :%x"
627 "ipv4_proto :%x"
628 "ipv6_proto :%x"
629 "tcp_proto :%x"
630 "udp_proto :%x"
631 "ip_frag :%x"
632 "tcp_only_ack :%x"
633 "da_is_bcast_mcast :%x"
634 "toeplitz_hash_sel :%x"
635 "ip_fixed_header_valid:%x"
636 "ip_extn_header_valid :%x"
637 "tcp_udp_header_valid :%x",
638 msdu_end->reserved_17a,
639 msdu_end->msdu_length,
640 msdu_end->ipsec_esp,
641 msdu_end->l3_offset,
642 msdu_end->ipsec_ah,
643 msdu_end->l4_offset,
644 msdu_end->msdu_number,
645 msdu_end->decap_format,
646 msdu_end->ipv4_proto,
647 msdu_end->ipv6_proto,
648 msdu_end->tcp_proto,
649 msdu_end->udp_proto,
650 msdu_end->ip_frag,
651 msdu_end->tcp_only_ack,
652 msdu_end->da_is_bcast_mcast,
653 msdu_end->toeplitz_hash_sel,
654 msdu_end->ip_fixed_header_valid,
655 msdu_end->ip_extn_header_valid,
656 msdu_end->tcp_udp_header_valid);
657
658 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
659 "rx_msdu_end tlv (5/7)"
660 "mesh_control_present :%x"
661 "ldpc :%x"
662 "ip4_protocol_ip6_next_header :%x"
663 "toeplitz_hash_2_or_4 :%x"
664 "flow_id_toeplitz :%x"
665 "user_rssi :%x"
666 "pkt_type :%x"
667 "stbc :%x"
668 "sgi :%x"
669 "rate_mcs :%x"
670 "receive_bandwidth :%x"
671 "reception_type :%x"
672 "mimo_ss_bitmap :%x"
673 "ppdu_start_timestamp_31_0 :%x"
674 "ppdu_start_timestamp_63_32 :%x"
675 "sw_phy_meta_data :%x"
676 "vlan_ctag_ci :%x"
677 "vlan_stag_ci :%x"
678 "first_mpdu :%x"
679 "reserved_30a :%x"
680 "mcast_bcast :%x",
681 msdu_end->mesh_control_present,
682 msdu_end->ldpc,
683 msdu_end->ip4_protocol_ip6_next_header,
684 msdu_end->toeplitz_hash_2_or_4,
685 msdu_end->flow_id_toeplitz,
686 msdu_end->user_rssi,
687 msdu_end->pkt_type,
688 msdu_end->stbc,
689 msdu_end->sgi,
690 msdu_end->rate_mcs,
691 msdu_end->receive_bandwidth,
692 msdu_end->reception_type,
693 msdu_end->mimo_ss_bitmap,
694 msdu_end->ppdu_start_timestamp_31_0,
695 msdu_end->ppdu_start_timestamp_63_32,
696 msdu_end->sw_phy_meta_data,
697 msdu_end->vlan_ctag_ci,
698 msdu_end->vlan_stag_ci,
699 msdu_end->first_mpdu,
700 msdu_end->reserved_30a,
701 msdu_end->mcast_bcast);
702
703 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
704 "rx_msdu_end tlv (6/7)"
705 "ast_index_not_found :%x"
706 "ast_index_timeout :%x"
707 "power_mgmt :%x"
708 "non_qos :%x"
709 "null_data :%x"
710 "mgmt_type :%x"
711 "ctrl_type :%x"
712 "more_data :%x"
713 "eosp :%x"
714 "a_msdu_error :%x"
715 "fragment_flag:%x"
716 "order:%x"
717 "cce_match :%x"
718 "overflow_err :%x"
719 "msdu_length_err :%x"
720 "tcp_udp_chksum_fail :%x"
721 "ip_chksum_fail :%x"
722 "sa_idx_invalid :%x"
723 "da_idx_invalid :%x"
724 "reserved_30b :%x",
725 msdu_end->ast_index_not_found,
726 msdu_end->ast_index_timeout,
727 msdu_end->power_mgmt,
728 msdu_end->non_qos,
729 msdu_end->null_data,
730 msdu_end->mgmt_type,
731 msdu_end->ctrl_type,
732 msdu_end->more_data,
733 msdu_end->eosp,
734 msdu_end->a_msdu_error,
735 msdu_end->fragment_flag,
736 msdu_end->order,
737 msdu_end->cce_match,
738 msdu_end->overflow_err,
739 msdu_end->msdu_length_err,
740 msdu_end->tcp_udp_chksum_fail,
741 msdu_end->ip_chksum_fail,
742 msdu_end->sa_idx_invalid,
743 msdu_end->da_idx_invalid,
744 msdu_end->reserved_30b);
745
746 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
747 "rx_msdu_end tlv (7/7)"
748 "rx_in_tx_decrypt_byp :%x"
749 "encrypt_required :%x"
750 "directed :%x"
751 "buffer_fragment :%x"
752 "mpdu_length_err :%x"
753 "tkip_mic_err :%x"
754 "decrypt_err :%x"
755 "unencrypted_frame_err:%x"
756 "fcs_err :%x"
757 "reserved_31a :%x"
758 "decrypt_status_code :%x"
759 "rx_bitmap_not_updated:%x"
760 "reserved_31b :%x"
761 "msdu_done :%x",
762 msdu_end->rx_in_tx_decrypt_byp,
763 msdu_end->encrypt_required,
764 msdu_end->directed,
765 msdu_end->buffer_fragment,
766 msdu_end->mpdu_length_err,
767 msdu_end->tkip_mic_err,
768 msdu_end->decrypt_err,
769 msdu_end->unencrypted_frame_err,
770 msdu_end->fcs_err,
771 msdu_end->reserved_31a,
772 msdu_end->decrypt_status_code,
773 msdu_end->rx_bitmap_not_updated,
774 msdu_end->reserved_31b,
775 msdu_end->msdu_done);
776 }
777 #endif
778
779 #ifdef NO_RX_PKT_HDR_TLV
hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)780 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs,
781 uint8_t dbg_level)
782 {
783 }
784
785 static inline
hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc * hal_soc)786 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc)
787 {
788 }
789
hal_rx_desc_get_80211_hdr_be(void * hw_desc_addr)790 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr)
791 {
792 uint8_t *rx_pkt_hdr;
793 struct rx_mon_pkt_tlvs *rx_desc =
794 (struct rx_mon_pkt_tlvs *)hw_desc_addr;
795
796 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
797
798 return rx_pkt_hdr;
799 }
800 #else
hal_rx_desc_get_80211_hdr_be(void * hw_desc_addr)801 static uint8_t *hal_rx_desc_get_80211_hdr_be(void *hw_desc_addr)
802 {
803 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
804 uint8_t *rx_pkt_hdr;
805
806 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
807
808 return rx_pkt_hdr;
809 }
810
811 /**
812 * hal_rx_dump_pkt_hdr_tlv_kiwi() - dump RX pkt header TLV in hex format
813 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
814 * @dbg_level: log level.
815 *
816 * Return: void
817 */
hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)818 static inline void hal_rx_dump_pkt_hdr_tlv_kiwi(struct rx_pkt_tlvs *pkt_tlvs,
819 uint8_t dbg_level)
820 {
821 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
822
823 hal_verbose_debug("\n---------------\n"
824 "rx_pkt_hdr_tlv\n"
825 "---------------\n"
826 "phy_ppdu_id 0x%x ",
827 pkt_hdr_tlv->phy_ppdu_id);
828
829 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
830 sizeof(pkt_hdr_tlv->rx_pkt_hdr));
831 }
832
833 /**
834 * hal_register_rx_pkt_hdr_tlv_api_kiwi: register all rx_pkt_hdr_tlv related api
835 * @hal_soc: HAL soc handler
836 *
837 * Return: none
838 */
839 static inline
hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc * hal_soc)840 void hal_register_rx_pkt_hdr_tlv_api_kiwi(struct hal_soc *hal_soc)
841 {
842 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
843 hal_rx_pkt_tlv_offset_get_generic;
844 }
845 #endif
846
847 /**
848 * hal_rx_dump_mpdu_start_tlv_kiwi(): dump RX mpdu_start TLV in structured
849 * human readable format.
850 * @mpdustart: pointer the rx_attention TLV in pkt.
851 * @dbg_level: log level.
852 *
853 * Return: void
854 */
hal_rx_dump_mpdu_start_tlv_kiwi(void * mpdustart,uint8_t dbg_level)855 static inline void hal_rx_dump_mpdu_start_tlv_kiwi(void *mpdustart,
856 uint8_t dbg_level)
857 {
858 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
859 struct rx_mpdu_info *mpdu_info =
860 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
861
862 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
863 "rx_mpdu_start tlv (1/5) - "
864 "rx_reo_queue_desc_addr_31_0 :%x"
865 "rx_reo_queue_desc_addr_39_32 :%x"
866 "receive_queue_number:%x "
867 "pre_delim_err_warning:%x "
868 "first_delim_err:%x "
869 "reserved_2a:%x "
870 "pn_31_0:%x "
871 "pn_63_32:%x "
872 "pn_95_64:%x "
873 "pn_127_96:%x "
874 "epd_en:%x "
875 "all_frames_shall_be_encrypted :%x"
876 "encrypt_type:%x "
877 "wep_key_width_for_variable_key :%x"
878 "bssid_hit:%x "
879 "bssid_number:%x "
880 "tid:%x "
881 "reserved_7a:%x "
882 "peer_meta_data:%x ",
883 mpdu_info->rx_reo_queue_desc_addr_31_0,
884 mpdu_info->rx_reo_queue_desc_addr_39_32,
885 mpdu_info->receive_queue_number,
886 mpdu_info->pre_delim_err_warning,
887 mpdu_info->first_delim_err,
888 mpdu_info->reserved_2a,
889 mpdu_info->pn_31_0,
890 mpdu_info->pn_63_32,
891 mpdu_info->pn_95_64,
892 mpdu_info->pn_127_96,
893 mpdu_info->epd_en,
894 mpdu_info->all_frames_shall_be_encrypted,
895 mpdu_info->encrypt_type,
896 mpdu_info->wep_key_width_for_variable_key,
897 mpdu_info->bssid_hit,
898 mpdu_info->bssid_number,
899 mpdu_info->tid,
900 mpdu_info->reserved_7a,
901 mpdu_info->peer_meta_data);
902
903 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
904 "rx_mpdu_start tlv (2/5) - "
905 "rxpcu_mpdu_filter_in_category :%x"
906 "sw_frame_group_id:%x "
907 "ndp_frame:%x "
908 "phy_err:%x "
909 "phy_err_during_mpdu_header :%x"
910 "protocol_version_err:%x "
911 "ast_based_lookup_valid:%x "
912 "reserved_9a:%x "
913 "phy_ppdu_id:%x "
914 "ast_index:%x "
915 "sw_peer_id:%x "
916 "mpdu_frame_control_valid:%x "
917 "mpdu_duration_valid:%x "
918 "mac_addr_ad1_valid:%x "
919 "mac_addr_ad2_valid:%x "
920 "mac_addr_ad3_valid:%x "
921 "mac_addr_ad4_valid:%x "
922 "mpdu_sequence_control_valid :%x"
923 "mpdu_qos_control_valid:%x "
924 "mpdu_ht_control_valid:%x "
925 "frame_encryption_info_valid :%x",
926 mpdu_info->rxpcu_mpdu_filter_in_category,
927 mpdu_info->sw_frame_group_id,
928 mpdu_info->ndp_frame,
929 mpdu_info->phy_err,
930 mpdu_info->phy_err_during_mpdu_header,
931 mpdu_info->protocol_version_err,
932 mpdu_info->ast_based_lookup_valid,
933 mpdu_info->reserved_9a,
934 mpdu_info->phy_ppdu_id,
935 mpdu_info->ast_index,
936 mpdu_info->sw_peer_id,
937 mpdu_info->mpdu_frame_control_valid,
938 mpdu_info->mpdu_duration_valid,
939 mpdu_info->mac_addr_ad1_valid,
940 mpdu_info->mac_addr_ad2_valid,
941 mpdu_info->mac_addr_ad3_valid,
942 mpdu_info->mac_addr_ad4_valid,
943 mpdu_info->mpdu_sequence_control_valid,
944 mpdu_info->mpdu_qos_control_valid,
945 mpdu_info->mpdu_ht_control_valid,
946 mpdu_info->frame_encryption_info_valid);
947
948 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
949 "rx_mpdu_start tlv (3/5) - "
950 "mpdu_fragment_number:%x "
951 "more_fragment_flag:%x "
952 "reserved_11a:%x "
953 "fr_ds:%x "
954 "to_ds:%x "
955 "encrypted:%x "
956 "mpdu_retry:%x "
957 "mpdu_sequence_number:%x "
958 "key_id_octet:%x "
959 "new_peer_entry:%x "
960 "decrypt_needed:%x "
961 "decap_type:%x "
962 "rx_insert_vlan_c_tag_padding :%x"
963 "rx_insert_vlan_s_tag_padding :%x"
964 "strip_vlan_c_tag_decap:%x "
965 "strip_vlan_s_tag_decap:%x "
966 "pre_delim_count:%x "
967 "ampdu_flag:%x "
968 "bar_frame:%x "
969 "raw_mpdu:%x "
970 "reserved_12:%x "
971 "mpdu_length:%x ",
972 mpdu_info->mpdu_fragment_number,
973 mpdu_info->more_fragment_flag,
974 mpdu_info->reserved_11a,
975 mpdu_info->fr_ds,
976 mpdu_info->to_ds,
977 mpdu_info->encrypted,
978 mpdu_info->mpdu_retry,
979 mpdu_info->mpdu_sequence_number,
980 mpdu_info->key_id_octet,
981 mpdu_info->new_peer_entry,
982 mpdu_info->decrypt_needed,
983 mpdu_info->decap_type,
984 mpdu_info->rx_insert_vlan_c_tag_padding,
985 mpdu_info->rx_insert_vlan_s_tag_padding,
986 mpdu_info->strip_vlan_c_tag_decap,
987 mpdu_info->strip_vlan_s_tag_decap,
988 mpdu_info->pre_delim_count,
989 mpdu_info->ampdu_flag,
990 mpdu_info->bar_frame,
991 mpdu_info->raw_mpdu,
992 mpdu_info->reserved_12,
993 mpdu_info->mpdu_length);
994
995 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
996 "rx_mpdu_start tlv (4/5) - "
997 "mpdu_length:%x "
998 "first_mpdu:%x "
999 "mcast_bcast:%x "
1000 "ast_index_not_found:%x "
1001 "ast_index_timeout:%x "
1002 "power_mgmt:%x "
1003 "non_qos:%x "
1004 "null_data:%x "
1005 "mgmt_type:%x "
1006 "ctrl_type:%x "
1007 "more_data:%x "
1008 "eosp:%x "
1009 "fragment_flag:%x "
1010 "order:%x "
1011 "u_apsd_trigger:%x "
1012 "encrypt_required:%x "
1013 "directed:%x "
1014 "amsdu_present:%x "
1015 "reserved_13:%x "
1016 "mpdu_frame_control_field:%x "
1017 "mpdu_duration_field:%x ",
1018 mpdu_info->mpdu_length,
1019 mpdu_info->first_mpdu,
1020 mpdu_info->mcast_bcast,
1021 mpdu_info->ast_index_not_found,
1022 mpdu_info->ast_index_timeout,
1023 mpdu_info->power_mgmt,
1024 mpdu_info->non_qos,
1025 mpdu_info->null_data,
1026 mpdu_info->mgmt_type,
1027 mpdu_info->ctrl_type,
1028 mpdu_info->more_data,
1029 mpdu_info->eosp,
1030 mpdu_info->fragment_flag,
1031 mpdu_info->order,
1032 mpdu_info->u_apsd_trigger,
1033 mpdu_info->encrypt_required,
1034 mpdu_info->directed,
1035 mpdu_info->amsdu_present,
1036 mpdu_info->reserved_13,
1037 mpdu_info->mpdu_frame_control_field,
1038 mpdu_info->mpdu_duration_field);
1039
1040 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_HAL,
1041 "rx_mpdu_start tlv (5/5) - "
1042 "mac_addr_ad1_31_0:%x "
1043 "mac_addr_ad1_47_32:%x "
1044 "mac_addr_ad2_15_0:%x "
1045 "mac_addr_ad2_47_16:%x "
1046 "mac_addr_ad3_31_0:%x "
1047 "mac_addr_ad3_47_32:%x "
1048 "mpdu_sequence_control_field :%x"
1049 "mac_addr_ad4_31_0:%x "
1050 "mac_addr_ad4_47_32:%x "
1051 "mpdu_qos_control_field:%x "
1052 "mpdu_ht_control_field:%x "
1053 "vdev_id:%x "
1054 "service_code:%x "
1055 "priority_valid:%x "
1056 "reserved_23a:%x ",
1057 mpdu_info->mac_addr_ad1_31_0,
1058 mpdu_info->mac_addr_ad1_47_32,
1059 mpdu_info->mac_addr_ad2_15_0,
1060 mpdu_info->mac_addr_ad2_47_16,
1061 mpdu_info->mac_addr_ad3_31_0,
1062 mpdu_info->mac_addr_ad3_47_32,
1063 mpdu_info->mpdu_sequence_control_field,
1064 mpdu_info->mac_addr_ad4_31_0,
1065 mpdu_info->mac_addr_ad4_47_32,
1066 mpdu_info->mpdu_qos_control_field,
1067 mpdu_info->mpdu_ht_control_field,
1068 mpdu_info->vdev_id,
1069 mpdu_info->service_code,
1070 mpdu_info->priority_valid,
1071 mpdu_info->reserved_23a);
1072 }
1073
1074 /**
1075 * hal_rx_dump_pkt_tlvs_kiwi(): API to print RX Pkt TLVS for kiwi
1076 * @hal_soc_hdl: hal_soc handle
1077 * @buf: pointer the pkt buffer
1078 * @dbg_level: log level
1079 *
1080 * Return: void
1081 */
hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1082 static void hal_rx_dump_pkt_tlvs_kiwi(hal_soc_handle_t hal_soc_hdl,
1083 uint8_t *buf, uint8_t dbg_level)
1084 {
1085 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1086 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1087 struct rx_mpdu_start *mpdu_start =
1088 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1089
1090 hal_rx_dump_msdu_end_tlv_kiwi(msdu_end, dbg_level);
1091 hal_rx_dump_mpdu_start_tlv_kiwi(mpdu_start, dbg_level);
1092 hal_rx_dump_pkt_hdr_tlv_kiwi(pkt_tlvs, dbg_level);
1093 }
1094
1095 /**
1096 * hal_rx_get_mpdu_flags_from_tlv() - Populate the local mpdu_flags elements
1097 * from the rx tlvs
1098 * @mpdu_info: buf address to rx_mpdu_info
1099 *
1100 * Return: mpdu_flags.
1101 */
1102 static inline uint32_t
hal_rx_get_mpdu_flags_from_tlv(struct rx_mpdu_info * mpdu_info)1103 hal_rx_get_mpdu_flags_from_tlv(struct rx_mpdu_info *mpdu_info)
1104 {
1105 uint32_t mpdu_flags = 0;
1106
1107 if (mpdu_info->fragment_flag)
1108 mpdu_flags |= HAL_MPDU_F_FRAGMENT;
1109
1110 if (mpdu_info->mpdu_retry)
1111 mpdu_flags |= HAL_MPDU_F_RETRY_BIT;
1112
1113 if (mpdu_info->ampdu_flag)
1114 mpdu_flags |= HAL_MPDU_F_AMPDU_FLAG;
1115
1116 if (mpdu_info->raw_mpdu)
1117 mpdu_flags |= HAL_MPDU_F_RAW_AMPDU;
1118
1119 if (mpdu_info->mpdu_qos_control_valid)
1120 mpdu_flags |= HAL_MPDU_F_QOS_CONTROL_VALID;
1121
1122 return mpdu_flags;
1123 }
1124
1125 /**
1126 * hal_rx_tlv_populate_mpdu_desc_info_kiwi() - Populate the local mpdu_desc_info
1127 * elements from the rx tlvs
1128 * @buf: start address of rx tlvs [Validated by caller]
1129 * @mpdu_desc_info_hdl: Buffer to populate the mpdu_dsc_info
1130 * [To be validated by caller]
1131 *
1132 * Return: None
1133 */
1134 static void
hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t * buf,void * mpdu_desc_info_hdl)1135 hal_rx_tlv_populate_mpdu_desc_info_kiwi(uint8_t *buf,
1136 void *mpdu_desc_info_hdl)
1137 {
1138 struct hal_rx_mpdu_desc_info *mpdu_desc_info =
1139 (struct hal_rx_mpdu_desc_info *)mpdu_desc_info_hdl;
1140 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1141 struct rx_mpdu_start *mpdu_start =
1142 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1143 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1144
1145 mpdu_desc_info->mpdu_seq = mpdu_info->mpdu_sequence_number;
1146 mpdu_desc_info->mpdu_flags = hal_rx_get_mpdu_flags_from_tlv(mpdu_info);
1147 mpdu_desc_info->peer_meta_data = mpdu_info->peer_meta_data;
1148 mpdu_desc_info->bar_frame = mpdu_info->bar_frame;
1149 }
1150
1151 /**
1152 * hal_reo_status_get_header_kiwi() - Process reo desc info
1153 * @ring_desc: Pointer to reo descriptor
1154 * @b: tlv type info
1155 * @h1: Pointer to hal_reo_status_header where info to be stored
1156 *
1157 * Return: none.
1158 *
1159 */
hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc,int b,void * h1)1160 static void hal_reo_status_get_header_kiwi(hal_ring_desc_t ring_desc, int b,
1161 void *h1)
1162 {
1163 uint64_t *d = (uint64_t *)ring_desc;
1164 uint64_t val1 = 0;
1165 struct hal_reo_status_header *h =
1166 (struct hal_reo_status_header *)h1;
1167
1168 /* Offsets of descriptor fields defined in HW headers start
1169 * from the field after TLV header
1170 */
1171 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
1172
1173 switch (b) {
1174 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1175 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
1176 STATUS_HEADER_REO_STATUS_NUMBER)];
1177 break;
1178 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1179 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
1180 STATUS_HEADER_REO_STATUS_NUMBER)];
1181 break;
1182 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1183 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
1184 STATUS_HEADER_REO_STATUS_NUMBER)];
1185 break;
1186 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1187 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
1188 STATUS_HEADER_REO_STATUS_NUMBER)];
1189 break;
1190 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1191 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1192 STATUS_HEADER_REO_STATUS_NUMBER)];
1193 break;
1194 case HAL_REO_DESC_THRES_STATUS_TLV:
1195 val1 =
1196 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1197 STATUS_HEADER_REO_STATUS_NUMBER)];
1198 break;
1199 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1200 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
1201 STATUS_HEADER_REO_STATUS_NUMBER)];
1202 break;
1203 default:
1204 qdf_nofl_err("ERROR: Unknown tlv\n");
1205 break;
1206 }
1207 h->cmd_num =
1208 HAL_GET_FIELD(
1209 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
1210 val1);
1211 h->exec_time =
1212 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
1213 CMD_EXECUTION_TIME, val1);
1214 h->status =
1215 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
1216 REO_CMD_EXECUTION_STATUS, val1);
1217 switch (b) {
1218 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1219 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
1220 STATUS_HEADER_TIMESTAMP)];
1221 break;
1222 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1223 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
1224 STATUS_HEADER_TIMESTAMP)];
1225 break;
1226 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1227 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
1228 STATUS_HEADER_TIMESTAMP)];
1229 break;
1230 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1231 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
1232 STATUS_HEADER_TIMESTAMP)];
1233 break;
1234 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1235 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
1236 STATUS_HEADER_TIMESTAMP)];
1237 break;
1238 case HAL_REO_DESC_THRES_STATUS_TLV:
1239 val1 =
1240 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
1241 STATUS_HEADER_TIMESTAMP)];
1242 break;
1243 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1244 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
1245 STATUS_HEADER_TIMESTAMP)];
1246 break;
1247 default:
1248 qdf_nofl_err("ERROR: Unknown tlv\n");
1249 break;
1250 }
1251 h->tstamp =
1252 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
1253 }
1254
1255 static
hal_rx_msdu0_buffer_addr_lsb_kiwi(void * link_desc_va)1256 void *hal_rx_msdu0_buffer_addr_lsb_kiwi(void *link_desc_va)
1257 {
1258 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
1259 }
1260
1261 static
hal_rx_msdu_desc_info_ptr_get_kiwi(void * msdu0)1262 void *hal_rx_msdu_desc_info_ptr_get_kiwi(void *msdu0)
1263 {
1264 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
1265 }
1266
1267 static
hal_ent_mpdu_desc_info_kiwi(void * ent_ring_desc)1268 void *hal_ent_mpdu_desc_info_kiwi(void *ent_ring_desc)
1269 {
1270 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
1271 }
1272
1273 static
hal_dst_mpdu_desc_info_kiwi(void * dst_ring_desc)1274 void *hal_dst_mpdu_desc_info_kiwi(void *dst_ring_desc)
1275 {
1276 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
1277 }
1278
1279 /**
1280 * hal_rx_get_tlv_kiwi() - API to get the tlv
1281 * @rx_tlv: TLV data extracted from the rx packet
1282 *
1283 * Return: uint8_t
1284 */
hal_rx_get_tlv_kiwi(void * rx_tlv)1285 static uint8_t hal_rx_get_tlv_kiwi(void *rx_tlv)
1286 {
1287 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
1288 }
1289
1290 /**
1291 * hal_rx_phy_legacy_get_rssi_kiwi() - API to get RSSI from TLV
1292 * WIFIPHYRX_RSSI_LEGACY_E
1293 * @buf: pointer to the start of WIFIPHYRX_RSSI_LEGACY_E TLV
1294 *
1295 * Return: value of RSSI
1296 */
hal_rx_phy_legacy_get_rssi_kiwi(uint8_t * buf)1297 static int8_t hal_rx_phy_legacy_get_rssi_kiwi(uint8_t *buf)
1298 {
1299 return HAL_RX_GET_64(buf, PHYRX_RSSI_LEGACY, RSSI_COMB_PPDU);
1300 }
1301
1302 /**
1303 * hal_rx_proc_phyrx_other_receive_info_tlv_kiwi()
1304 * - process other receive info TLV
1305 * @rx_tlv_hdr: pointer to TLV header
1306 * @ppdu_info_handle: pointer to ppdu_info
1307 *
1308 * Return: None
1309 */
1310 static
hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void * rx_tlv_hdr,void * ppdu_info_handle)1311 void hal_rx_proc_phyrx_other_receive_info_tlv_kiwi(void *rx_tlv_hdr,
1312 void *ppdu_info_handle)
1313 {
1314 uint32_t tlv_tag, tlv_len;
1315 uint32_t temp_len, other_tlv_len, other_tlv_tag;
1316 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
1317 void *other_tlv_hdr = NULL;
1318 void *other_tlv = NULL;
1319
1320 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
1321 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
1322 temp_len = 0;
1323
1324 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
1325
1326 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
1327 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
1328 temp_len += other_tlv_len;
1329 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
1330
1331 switch (other_tlv_tag) {
1332 default:
1333 hal_err_rl("unhandled TLV type: %d, TLV len:%d",
1334 other_tlv_tag, other_tlv_len);
1335 break;
1336 }
1337 }
1338
1339 /**
1340 * hal_reo_config_kiwi(): Set reo config parameters
1341 * @soc: hal soc handle
1342 * @reg_val: value to be set
1343 * @reo_params: reo parameters
1344 *
1345 * Return: void
1346 */
1347 static
hal_reo_config_kiwi(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)1348 void hal_reo_config_kiwi(struct hal_soc *soc,
1349 uint32_t reg_val,
1350 struct hal_reo_params *reo_params)
1351 {
1352 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
1353 }
1354
1355 /**
1356 * hal_rx_msdu_desc_info_get_ptr_kiwi() - Get msdu desc info ptr
1357 * @msdu_details_ptr: Pointer to msdu_details_ptr
1358 *
1359 * Return: Pointer to rx_msdu_desc_info structure.
1360 *
1361 */
hal_rx_msdu_desc_info_get_ptr_kiwi(void * msdu_details_ptr)1362 static void *hal_rx_msdu_desc_info_get_ptr_kiwi(void *msdu_details_ptr)
1363 {
1364 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
1365 }
1366
1367 /**
1368 * hal_rx_link_desc_msdu0_ptr_kiwi() - Get pointer to rx_msdu details
1369 * @link_desc: Pointer to link desc
1370 *
1371 * Return: Pointer to rx_msdu_details structure
1372 *
1373 */
hal_rx_link_desc_msdu0_ptr_kiwi(void * link_desc)1374 static void *hal_rx_link_desc_msdu0_ptr_kiwi(void *link_desc)
1375 {
1376 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
1377 }
1378
1379 /**
1380 * hal_get_window_address_kiwi(): Function to get hp/tp address
1381 * @hal_soc: Pointer to hal_soc
1382 * @addr: address offset of register
1383 *
1384 * Return: modified address offset of register
1385 */
hal_get_window_address_kiwi(struct hal_soc * hal_soc,qdf_iomem_t addr)1386 static inline qdf_iomem_t hal_get_window_address_kiwi(struct hal_soc *hal_soc,
1387 qdf_iomem_t addr)
1388 {
1389 return addr;
1390 }
1391
1392 /**
1393 * hal_reo_set_err_dst_remap_kiwi(): Function to set REO error destination
1394 * ring remap register
1395 * @hal_soc: Pointer to hal_soc
1396 *
1397 * Return: none.
1398 */
1399 static void
hal_reo_set_err_dst_remap_kiwi(void * hal_soc)1400 hal_reo_set_err_dst_remap_kiwi(void *hal_soc)
1401 {
1402 /*
1403 * Set REO error 2k jump (error code 5) / OOR (error code 7)
1404 * frame routed to REO2SW0 ring.
1405 */
1406 uint32_t dst_remap_ix0 =
1407 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 0) |
1408 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 1) |
1409 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 2) |
1410 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 3) |
1411 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 4) |
1412 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 5) |
1413 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 6) |
1414 HAL_REO_ERR_REMAP_IX0(REO_REMAP_TCL, 7);
1415
1416 uint32_t dst_remap_ix1 =
1417 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 14) |
1418 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 13) |
1419 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 12) |
1420 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 11) |
1421 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 10) |
1422 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 9) |
1423 HAL_REO_ERR_REMAP_IX1(REO_REMAP_TCL, 8);
1424
1425 HAL_REG_WRITE(hal_soc,
1426 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
1427 REO_REG_REG_BASE),
1428 dst_remap_ix0);
1429
1430 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 0x%x",
1431 HAL_REG_READ(
1432 hal_soc,
1433 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(
1434 REO_REG_REG_BASE)));
1435
1436 HAL_REG_WRITE(hal_soc,
1437 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
1438 REO_REG_REG_BASE),
1439 dst_remap_ix1);
1440
1441 hal_info("HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 0x%x",
1442 HAL_REG_READ(
1443 hal_soc,
1444 HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(
1445 REO_REG_REG_BASE)));
1446 }
1447
1448 /**
1449 * hal_reo_enable_pn_in_dest_kiwi() - Set the REO register to enable previous PN
1450 * for OOR and 2K-jump frames
1451 * @hal_soc: HAL SoC handle
1452 *
1453 * Return: 1, since the register is set.
1454 */
hal_reo_enable_pn_in_dest_kiwi(void * hal_soc)1455 static uint8_t hal_reo_enable_pn_in_dest_kiwi(void *hal_soc)
1456 {
1457 HAL_REG_WRITE(hal_soc, HWIO_REO_R0_PN_IN_DEST_ADDR(REO_REG_REG_BASE),
1458 1);
1459 return 1;
1460 }
1461
1462 /**
1463 * hal_rx_flow_setup_fse_kiwi() - Setup a flow search entry in HW FST
1464 * @rx_fst: Pointer to the Rx Flow Search Table
1465 * @table_offset: offset into the table where the flow is to be setup
1466 * @rx_flow: Flow Parameters
1467 *
1468 * Flow table entry fields are updated in host byte order, little endian order.
1469 *
1470 * Return: Success/Failure
1471 */
1472 static void *
hal_rx_flow_setup_fse_kiwi(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1473 hal_rx_flow_setup_fse_kiwi(uint8_t *rx_fst, uint32_t table_offset,
1474 uint8_t *rx_flow)
1475 {
1476 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1477 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1478 uint8_t *fse;
1479 bool fse_valid;
1480
1481 if (table_offset >= fst->max_entries) {
1482 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1483 "HAL FSE table offset %u exceeds max entries %u",
1484 table_offset, fst->max_entries);
1485 return NULL;
1486 }
1487
1488 fse = (uint8_t *)fst->base_vaddr +
1489 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1490
1491 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1492
1493 if (fse_valid) {
1494 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1495 "HAL FSE %pK already valid", fse);
1496 return NULL;
1497 }
1498
1499 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
1500 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1501 (flow->tuple_info.src_ip_127_96));
1502
1503 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
1504 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1505 (flow->tuple_info.src_ip_95_64));
1506
1507 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
1508 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1509 (flow->tuple_info.src_ip_63_32));
1510
1511 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
1512 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1513 (flow->tuple_info.src_ip_31_0));
1514
1515 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
1516 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1517 (flow->tuple_info.dest_ip_127_96));
1518
1519 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
1520 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1521 (flow->tuple_info.dest_ip_95_64));
1522
1523 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
1524 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1525 (flow->tuple_info.dest_ip_63_32));
1526
1527 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
1528 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1529 (flow->tuple_info.dest_ip_31_0));
1530
1531 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
1532 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
1533 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1534 (flow->tuple_info.dest_port));
1535
1536 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
1537 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
1538 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1539 (flow->tuple_info.src_port));
1540
1541 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
1542 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
1543 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1544 flow->tuple_info.l4_protocol);
1545
1546 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
1547 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
1548 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1549 flow->reo_destination_handler);
1550
1551 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1552 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
1553 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1554
1555 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
1556 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
1557 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1558 (flow->fse_metadata));
1559
1560 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
1561 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
1562 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1563 REO_DESTINATION_INDICATION,
1564 flow->reo_destination_indication);
1565
1566 /* Reset all the other fields in FSE */
1567 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
1568 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
1569 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
1570 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
1571 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
1572
1573 return fse;
1574 }
1575
1576 /**
1577 * hal_rx_flow_setup_cmem_fse_kiwi() - Setup a flow search entry in HW CMEM FST
1578 * @hal_soc: hal_soc reference
1579 * @cmem_ba: CMEM base address
1580 * @table_offset: offset into the table where the flow is to be setup
1581 * @rx_flow: Flow Parameters
1582 *
1583 * Return: Success/Failure
1584 */
1585 static uint32_t
hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc * hal_soc,uint32_t cmem_ba,uint32_t table_offset,uint8_t * rx_flow)1586 hal_rx_flow_setup_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t cmem_ba,
1587 uint32_t table_offset, uint8_t *rx_flow)
1588 {
1589 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1590 uint32_t fse_offset;
1591 uint32_t value;
1592
1593 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE);
1594
1595 /* Reset the Valid bit */
1596 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1597 VALID), 0);
1598
1599 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1600 (flow->tuple_info.src_ip_127_96));
1601 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1602 SRC_IP_127_96), value);
1603
1604 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1605 (flow->tuple_info.src_ip_95_64));
1606 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1607 SRC_IP_95_64), value);
1608
1609 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1610 (flow->tuple_info.src_ip_63_32));
1611 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1612 SRC_IP_63_32), value);
1613
1614 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1615 (flow->tuple_info.src_ip_31_0));
1616 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1617 SRC_IP_31_0), value);
1618
1619 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1620 (flow->tuple_info.dest_ip_127_96));
1621 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1622 DEST_IP_127_96), value);
1623
1624 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1625 (flow->tuple_info.dest_ip_95_64));
1626 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1627 DEST_IP_95_64), value);
1628
1629 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1630 (flow->tuple_info.dest_ip_63_32));
1631 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1632 DEST_IP_63_32), value);
1633
1634 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1635 (flow->tuple_info.dest_ip_31_0));
1636 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1637 DEST_IP_31_0), value);
1638
1639 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1640 (flow->tuple_info.dest_port));
1641 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1642 (flow->tuple_info.src_port));
1643 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1644 SRC_PORT), value);
1645
1646 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1647 (flow->fse_metadata));
1648 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1649 METADATA), value);
1650
1651 /* Reset all the other fields in FSE */
1652 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1653 MSDU_COUNT), 0);
1654 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1655 MSDU_BYTE_COUNT), 0);
1656 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1657 TIMESTAMP), 0);
1658
1659 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1660 flow->tuple_info.l4_protocol);
1661 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1662 flow->reo_destination_handler);
1663 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1664 REO_DESTINATION_INDICATION,
1665 flow->reo_destination_indication);
1666 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1667 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY,
1668 L4_PROTOCOL), value);
1669
1670 return fse_offset;
1671 }
1672
1673 /**
1674 * hal_rx_flow_get_cmem_fse_ts_kiwi() - Get timestamp field from CMEM FSE
1675 * @hal_soc: hal_soc reference
1676 * @fse_offset: CMEM FSE offset
1677 *
1678 * Return: Timestamp
1679 */
hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc * hal_soc,uint32_t fse_offset)1680 static uint32_t hal_rx_flow_get_cmem_fse_ts_kiwi(struct hal_soc *hal_soc,
1681 uint32_t fse_offset)
1682 {
1683 return HAL_CMEM_READ(hal_soc, fse_offset +
1684 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY, TIMESTAMP));
1685 }
1686
1687 /**
1688 * hal_rx_flow_get_cmem_fse_kiwi() - Get FSE from CMEM
1689 * @hal_soc: hal_soc reference
1690 * @fse_offset: CMEM FSE offset
1691 * @fse: reference where FSE will be copied
1692 * @len: length of FSE
1693 *
1694 * Return: If read is successful or not
1695 */
1696 static void
hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc * hal_soc,uint32_t fse_offset,uint32_t * fse,qdf_size_t len)1697 hal_rx_flow_get_cmem_fse_kiwi(struct hal_soc *hal_soc, uint32_t fse_offset,
1698 uint32_t *fse, qdf_size_t len)
1699 {
1700 int i;
1701
1702 if (len != HAL_RX_FST_ENTRY_SIZE)
1703 return;
1704
1705 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++)
1706 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4);
1707 }
1708
1709 static
hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t * ring_map,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1710 void hal_compute_reo_remap_ix2_ix3_kiwi(uint32_t *ring_map,
1711 uint32_t num_rings, uint32_t *remap1,
1712 uint32_t *remap2)
1713 {
1714
1715 switch (num_rings) {
1716 /* should we have all the different possible ring configs */
1717 default:
1718 case 3:
1719 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) |
1720 HAL_REO_REMAP_IX2(ring_map[1], 17) |
1721 HAL_REO_REMAP_IX2(ring_map[2], 18) |
1722 HAL_REO_REMAP_IX2(ring_map[0], 19) |
1723 HAL_REO_REMAP_IX2(ring_map[1], 20) |
1724 HAL_REO_REMAP_IX2(ring_map[2], 21) |
1725 HAL_REO_REMAP_IX2(ring_map[0], 22) |
1726 HAL_REO_REMAP_IX2(ring_map[1], 23);
1727
1728 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) |
1729 HAL_REO_REMAP_IX3(ring_map[0], 25) |
1730 HAL_REO_REMAP_IX3(ring_map[1], 26) |
1731 HAL_REO_REMAP_IX3(ring_map[2], 27) |
1732 HAL_REO_REMAP_IX3(ring_map[0], 28) |
1733 HAL_REO_REMAP_IX3(ring_map[1], 29) |
1734 HAL_REO_REMAP_IX3(ring_map[2], 30) |
1735 HAL_REO_REMAP_IX3(ring_map[0], 31);
1736 break;
1737 case 4:
1738 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) |
1739 HAL_REO_REMAP_IX2(ring_map[1], 17) |
1740 HAL_REO_REMAP_IX2(ring_map[2], 18) |
1741 HAL_REO_REMAP_IX2(ring_map[3], 19) |
1742 HAL_REO_REMAP_IX2(ring_map[0], 20) |
1743 HAL_REO_REMAP_IX2(ring_map[1], 21) |
1744 HAL_REO_REMAP_IX2(ring_map[2], 22) |
1745 HAL_REO_REMAP_IX2(ring_map[3], 23);
1746
1747 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) |
1748 HAL_REO_REMAP_IX3(ring_map[1], 25) |
1749 HAL_REO_REMAP_IX3(ring_map[2], 26) |
1750 HAL_REO_REMAP_IX3(ring_map[3], 27) |
1751 HAL_REO_REMAP_IX3(ring_map[0], 28) |
1752 HAL_REO_REMAP_IX3(ring_map[1], 29) |
1753 HAL_REO_REMAP_IX3(ring_map[2], 30) |
1754 HAL_REO_REMAP_IX3(ring_map[3], 31);
1755 break;
1756 case 6:
1757 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) |
1758 HAL_REO_REMAP_IX2(ring_map[1], 17) |
1759 HAL_REO_REMAP_IX2(ring_map[2], 18) |
1760 HAL_REO_REMAP_IX2(ring_map[3], 19) |
1761 HAL_REO_REMAP_IX2(ring_map[4], 20) |
1762 HAL_REO_REMAP_IX2(ring_map[5], 21) |
1763 HAL_REO_REMAP_IX2(ring_map[0], 22) |
1764 HAL_REO_REMAP_IX2(ring_map[1], 23);
1765
1766 *remap2 = HAL_REO_REMAP_IX3(ring_map[2], 24) |
1767 HAL_REO_REMAP_IX3(ring_map[3], 25) |
1768 HAL_REO_REMAP_IX3(ring_map[4], 26) |
1769 HAL_REO_REMAP_IX3(ring_map[5], 27) |
1770 HAL_REO_REMAP_IX3(ring_map[0], 28) |
1771 HAL_REO_REMAP_IX3(ring_map[1], 29) |
1772 HAL_REO_REMAP_IX3(ring_map[2], 30) |
1773 HAL_REO_REMAP_IX3(ring_map[3], 31);
1774 break;
1775 case 8:
1776 *remap1 = HAL_REO_REMAP_IX2(ring_map[0], 16) |
1777 HAL_REO_REMAP_IX2(ring_map[1], 17) |
1778 HAL_REO_REMAP_IX2(ring_map[2], 18) |
1779 HAL_REO_REMAP_IX2(ring_map[3], 19) |
1780 HAL_REO_REMAP_IX2(ring_map[4], 20) |
1781 HAL_REO_REMAP_IX2(ring_map[5], 21) |
1782 HAL_REO_REMAP_IX2(ring_map[6], 22) |
1783 HAL_REO_REMAP_IX2(ring_map[7], 23);
1784
1785 *remap2 = HAL_REO_REMAP_IX3(ring_map[0], 24) |
1786 HAL_REO_REMAP_IX3(ring_map[1], 25) |
1787 HAL_REO_REMAP_IX3(ring_map[2], 26) |
1788 HAL_REO_REMAP_IX3(ring_map[3], 27) |
1789 HAL_REO_REMAP_IX3(ring_map[4], 28) |
1790 HAL_REO_REMAP_IX3(ring_map[5], 29) |
1791 HAL_REO_REMAP_IX3(ring_map[6], 30) |
1792 HAL_REO_REMAP_IX3(ring_map[7], 31);
1793 break;
1794 }
1795 }
1796
1797 /* NUM TCL Bank registers in KIWI */
1798 #define HAL_NUM_TCL_BANKS_KIWI 8
1799
1800 /**
1801 * hal_tx_get_num_tcl_banks_kiwi() - Get number of banks in target
1802 *
1803 * Returns: number of bank
1804 */
hal_tx_get_num_tcl_banks_kiwi(void)1805 static uint8_t hal_tx_get_num_tcl_banks_kiwi(void)
1806 {
1807 return HAL_NUM_TCL_BANKS_KIWI;
1808 }
1809
1810 /**
1811 * hal_rx_reo_prev_pn_get_kiwi() - Get the previous PN from the REO ring desc.
1812 * @ring_desc: REO ring descriptor [To be validated by caller ]
1813 * @prev_pn: Buffer where the previous PN is to be populated.
1814 * [To be validated by caller]
1815 *
1816 * Return: None
1817 */
hal_rx_reo_prev_pn_get_kiwi(void * ring_desc,uint64_t * prev_pn)1818 static void hal_rx_reo_prev_pn_get_kiwi(void *ring_desc,
1819 uint64_t *prev_pn)
1820 {
1821 struct reo_destination_ring_with_pn *reo_desc =
1822 (struct reo_destination_ring_with_pn *)ring_desc;
1823
1824 *prev_pn = reo_desc->prev_pn_23_0;
1825 *prev_pn |= ((uint64_t)reo_desc->prev_pn_55_24 << 24);
1826 }
1827
1828 /**
1829 * hal_cmem_write_kiwi() - function for CMEM buffer writing
1830 * @hal_soc_hdl: HAL SOC handle
1831 * @offset: CMEM address
1832 * @value: value to write
1833 *
1834 * Return: None.
1835 */
hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl,uint32_t offset,uint32_t value)1836 static inline void hal_cmem_write_kiwi(hal_soc_handle_t hal_soc_hdl,
1837 uint32_t offset,
1838 uint32_t value)
1839 {
1840 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
1841
1842 hal_write32_mb(hal, offset, value);
1843 }
1844
1845 /**
1846 * hal_get_idle_link_bm_id_kiwi() - Get idle link BM id from chid_id
1847 * @chip_id: mlo chip_id
1848 *
1849 * Returns: RBM ID
1850 */
hal_get_idle_link_bm_id_kiwi(uint8_t chip_id)1851 static uint8_t hal_get_idle_link_bm_id_kiwi(uint8_t chip_id)
1852 {
1853 return WBM_IDLE_DESC_LIST;
1854 }
1855
1856 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1857 /**
1858 * hal_get_first_wow_wakeup_packet_kiwi(): Function to get if the buffer
1859 * is the first one that wakes up host from WoW.
1860 *
1861 * @buf: network buffer
1862 *
1863 * Dummy function for KIWI
1864 *
1865 * Returns: 1 to indicate it is first packet received that wakes up host from
1866 * WoW. Otherwise 0
1867 */
hal_get_first_wow_wakeup_packet_kiwi(uint8_t * buf)1868 static inline uint8_t hal_get_first_wow_wakeup_packet_kiwi(uint8_t *buf)
1869 {
1870 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1871
1872 return HAL_RX_TLV_FIRST_WAKEUP_PKT_GET(pkt_tlvs);
1873 }
1874 #endif
1875
hal_get_rx_max_ba_window_kiwi(int tid)1876 static uint16_t hal_get_rx_max_ba_window_kiwi(int tid)
1877 {
1878 return HAL_RX_BA_WINDOW_1024;
1879 }
1880
1881 /**
1882 * hal_get_reo_qdesc_size_kiwi()- Get the reo queue descriptor size
1883 * from the give Block-Ack window size
1884 * @ba_window_size: Block-Ack window size
1885 * @tid: TID
1886 *
1887 * Return: reo queue descriptor size
1888 */
hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size,int tid)1889 static uint32_t hal_get_reo_qdesc_size_kiwi(uint32_t ba_window_size, int tid)
1890 {
1891 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
1892 * NON_QOS_TID until HW issues are resolved.
1893 */
1894 if (tid != HAL_NON_QOS_TID)
1895 ba_window_size = hal_get_rx_max_ba_window_kiwi(tid);
1896
1897 /* Return descriptor size corresponding to window size of 2 since
1898 * we set ba_window_size to 2 while setting up REO descriptors as
1899 * a WAR to get 2k jump exception aggregates are received without
1900 * a BA session.
1901 */
1902 if (ba_window_size <= 1) {
1903 if (tid != HAL_NON_QOS_TID)
1904 return sizeof(struct rx_reo_queue) +
1905 sizeof(struct rx_reo_queue_ext);
1906 else
1907 return sizeof(struct rx_reo_queue);
1908 }
1909
1910 if (ba_window_size <= 105)
1911 return sizeof(struct rx_reo_queue) +
1912 sizeof(struct rx_reo_queue_ext);
1913
1914 if (ba_window_size <= 210)
1915 return sizeof(struct rx_reo_queue) +
1916 (2 * sizeof(struct rx_reo_queue_ext));
1917
1918 if (ba_window_size <= 256)
1919 return sizeof(struct rx_reo_queue) +
1920 (3 * sizeof(struct rx_reo_queue_ext));
1921
1922 return sizeof(struct rx_reo_queue) +
1923 (10 * sizeof(struct rx_reo_queue_ext)) +
1924 sizeof(struct rx_reo_queue_1k);
1925 }
1926
1927 #ifdef QCA_GET_TSF_VIA_REG
1928 static inline uint32_t
hal_tsf_read_scratch_reg(struct hal_soc * soc,enum hal_scratch_reg_enum reg_enum)1929 hal_tsf_read_scratch_reg(struct hal_soc *soc,
1930 enum hal_scratch_reg_enum reg_enum)
1931 {
1932 return hal_read32_mb(soc, PMM_REG_BASE + (reg_enum * 4));
1933 }
1934
1935 static inline
hal_tsf_get_fw_time(struct hal_soc * soc)1936 uint64_t hal_tsf_get_fw_time(struct hal_soc *soc)
1937 {
1938 uint64_t fw_time_low;
1939 uint64_t fw_time_high;
1940
1941 fw_time_low = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_LOW);
1942 fw_time_high = hal_read32_mb(soc, PCIE_PCIE_MHI_TIME_HIGH);
1943 return (fw_time_high << 32 | fw_time_low);
1944 }
1945
1946 static inline
hal_fw_qtime_to_usecs(uint64_t time)1947 uint64_t hal_fw_qtime_to_usecs(uint64_t time)
1948 {
1949 /*
1950 * Try to preserve precision by multiplying by 10 first.
1951 * If that would cause a wrap around, divide first instead.
1952 */
1953 if (time * 10 < time) {
1954 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC);
1955 return time * 10;
1956 }
1957
1958 time = time * 10;
1959 time = qdf_do_div(time, FW_QTIME_CYCLES_PER_10_USEC);
1960
1961 return time;
1962 }
1963
1964 /**
1965 * hal_get_tsf_time_kiwi() - Get tsf time from scratch register
1966 * @hal_soc_hdl: HAL soc handle
1967 * @tsf_id: TSF id
1968 * @mac_id: mac_id
1969 * @tsf: pointer to update tsf value
1970 * @tsf_sync_soc_time: pointer to update tsf sync time
1971 *
1972 * Return: None.
1973 */
1974 static void
hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl,uint32_t tsf_id,uint32_t mac_id,uint64_t * tsf,uint64_t * tsf_sync_soc_time)1975 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
1976 uint32_t mac_id, uint64_t *tsf,
1977 uint64_t *tsf_sync_soc_time)
1978 {
1979 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
1980 uint64_t global_time_low_offset, global_time_high_offset;
1981 uint64_t tsf_offset_low, tsf_offset_hi;
1982 uint64_t fw_time, global_time, sync_time;
1983 enum hal_scratch_reg_enum tsf_enum_low = 0, tsf_enum_high = 0;
1984
1985 if (hif_force_wake_request(soc->hif_handle))
1986 return;
1987
1988 hal_get_tsf_enum(tsf_id, mac_id, &tsf_enum_low, &tsf_enum_high);
1989 sync_time = qdf_get_log_timestamp();
1990 fw_time = hal_tsf_get_fw_time(soc);
1991
1992 global_time_low_offset =
1993 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_LO_US);
1994 global_time_high_offset =
1995 hal_tsf_read_scratch_reg(soc, PMM_QTIMER_GLOBAL_OFFSET_HI_US);
1996
1997 tsf_offset_low = hal_tsf_read_scratch_reg(soc, tsf_enum_low);
1998 tsf_offset_hi = hal_tsf_read_scratch_reg(soc, tsf_enum_high);
1999
2000 fw_time = hal_fw_qtime_to_usecs(fw_time);
2001 global_time = fw_time +
2002 (global_time_low_offset |
2003 (global_time_high_offset << 32));
2004
2005 *tsf = global_time + (tsf_offset_low | (tsf_offset_hi << 32));
2006 *tsf_sync_soc_time = qdf_log_timestamp_to_usecs(sync_time);
2007
2008 hif_force_wake_release(soc->hif_handle);
2009 }
2010 #else
2011 static inline void
hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl,uint32_t tsf_id,uint32_t mac_id,uint64_t * tsf,uint64_t * tsf_sync_soc_time)2012 hal_get_tsf_time_kiwi(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
2013 uint32_t mac_id, uint64_t *tsf,
2014 uint64_t *tsf_sync_soc_time)
2015 {
2016 }
2017 #endif
2018
hal_rx_reo_ent_get_src_link_id_kiwi(hal_rxdma_desc_t rx_desc,uint8_t * src_link_id)2019 static QDF_STATUS hal_rx_reo_ent_get_src_link_id_kiwi(hal_rxdma_desc_t rx_desc,
2020 uint8_t *src_link_id)
2021 {
2022 struct reo_entrance_ring *reo_ent_desc =
2023 (struct reo_entrance_ring *)rx_desc;
2024
2025 *src_link_id = reo_ent_desc->src_link_id;
2026
2027 return QDF_STATUS_SUCCESS;
2028 }
2029
2030 /**
2031 * hal_rx_en_mcast_fp_data_filter_kiwi() - Is mcast filter pass enabled
2032 *
2033 * Return: false for BE MCC
2034 */
2035 static inline
hal_rx_en_mcast_fp_data_filter_kiwi(void)2036 bool hal_rx_en_mcast_fp_data_filter_kiwi(void)
2037 {
2038 return false;
2039 }
2040
2041 #ifdef QCA_WIFI_KIWI_V2
2042 /**
2043 * hal_srng_dst_hw_init_misc_1_kiwi() - Function to initialize MISC_1 register
2044 * of destination ring HW
2045 * @srng: SRNG ring pointer
2046 *
2047 * Return: None
2048 */
2049 static inline
hal_srng_dst_hw_init_misc_1_kiwi(struct hal_srng * srng)2050 void hal_srng_dst_hw_init_misc_1_kiwi(struct hal_srng *srng)
2051 {
2052 uint32_t reg_val = 0;
2053
2054 /* number threshold for pointer update */
2055 if (srng->pointer_num_threshold)
2056 reg_val |= SRNG_SM(SRNG_DST_HW_FLD(MISC_1,
2057 NUM_THRESHOLD_TO_UPDATE),
2058 srng->pointer_num_threshold);
2059 /* timer threshold for pointer update */
2060 if (srng->pointer_timer_threshold)
2061 reg_val |= SRNG_SM(SRNG_DST_HW_FLD(MISC_1,
2062 TIME_THRESHOLD_TO_UPDATE),
2063 srng->pointer_timer_threshold);
2064
2065 if (reg_val)
2066 SRNG_DST_REG_WRITE(srng, MISC_1, reg_val);
2067 }
2068
2069 /**
2070 * hal_srng_hw_reg_offset_init_misc_1_kiwi() - Initialize the HW srng register
2071 * offset of MISC_1
2072 * @hal_soc: HAL Soc handle
2073 *
2074 * Return: None
2075 */
2076 static inline
hal_srng_hw_reg_offset_init_misc_1_kiwi(struct hal_soc * hal_soc)2077 void hal_srng_hw_reg_offset_init_misc_1_kiwi(struct hal_soc *hal_soc)
2078 {
2079 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2080
2081 hw_reg_offset[DST_MISC_1] = REG_OFFSET(DST, MISC_1);
2082 }
2083 #else
2084 static inline
hal_srng_dst_hw_init_misc_1_kiwi(struct hal_srng * srng)2085 void hal_srng_dst_hw_init_misc_1_kiwi(struct hal_srng *srng)
2086 {
2087 }
2088
2089 static inline
hal_srng_hw_reg_offset_init_misc_1_kiwi(struct hal_soc * hal_soc)2090 void hal_srng_hw_reg_offset_init_misc_1_kiwi(struct hal_soc *hal_soc)
2091 {
2092 }
2093 #endif
2094
2095 /**
2096 * hal_srng_dst_hw_init_kiwi() - Function to initialize SRNG
2097 * destination ring HW
2098 * @hal_soc: HAL SOC handle
2099 * @srng: SRNG ring pointer
2100 * @idle_check: Check if ring is idle
2101 * @idx: Ring index
2102 *
2103 * Return: None
2104 */
2105 static inline
hal_srng_dst_hw_init_kiwi(struct hal_soc * hal_soc,struct hal_srng * srng,bool idle_check,uint32_t idx)2106 void hal_srng_dst_hw_init_kiwi(struct hal_soc *hal_soc,
2107 struct hal_srng *srng,
2108 bool idle_check,
2109 uint32_t idx)
2110 {
2111 hal_srng_dst_hw_init_misc_1_kiwi(srng);
2112
2113 hal_srng_dst_hw_init_generic(hal_soc, srng, idle_check, idx);
2114 }
2115
hal_hw_txrx_ops_attach_kiwi(struct hal_soc * hal_soc)2116 static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc)
2117 {
2118 /* init and setup */
2119 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_kiwi;
2120 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
2121 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
2122 hal_soc->ops->hal_get_window_address = hal_get_window_address_kiwi;
2123 hal_soc->ops->hal_reo_set_err_dst_remap =
2124 hal_reo_set_err_dst_remap_kiwi;
2125 hal_soc->ops->hal_reo_enable_pn_in_dest =
2126 hal_reo_enable_pn_in_dest_kiwi;
2127 /* Overwrite the default BE ops */
2128 hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_kiwi;
2129 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_kiwi;
2130
2131 /* tx */
2132 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_kiwi;
2133 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_kiwi;
2134 hal_soc->ops->hal_tx_comp_get_status =
2135 hal_tx_comp_get_status_generic_be;
2136 hal_soc->ops->hal_tx_init_cmd_credit_ring =
2137 hal_tx_init_cmd_credit_ring_kiwi;
2138 hal_soc->ops->hal_tx_config_rbm_mapping_be =
2139 hal_tx_config_rbm_mapping_be_kiwi;
2140
2141 /* rx */
2142 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
2143 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
2144 hal_rx_mon_hw_desc_get_mpdu_status_be;
2145 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_kiwi;
2146 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
2147 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
2148 hal_rx_proc_phyrx_other_receive_info_tlv_kiwi;
2149
2150 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_kiwi;
2151 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
2152 hal_rx_dump_mpdu_start_tlv_kiwi;
2153 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_kiwi;
2154 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_be;
2155
2156 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_kiwi;
2157 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
2158 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
2159 hal_rx_tlv_reception_type_get_be;
2160 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
2161 hal_rx_msdu_end_da_idx_get_be;
2162 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
2163 hal_rx_msdu_desc_info_get_ptr_kiwi;
2164 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
2165 hal_rx_link_desc_msdu0_ptr_kiwi;
2166 hal_soc->ops->hal_reo_status_get_header =
2167 hal_reo_status_get_header_kiwi;
2168 hal_soc->ops->hal_rx_status_get_tlv_info =
2169 hal_rx_status_get_tlv_info_wrapper_be;
2170 hal_soc->ops->hal_rx_wbm_err_info_get =
2171 hal_rx_wbm_err_info_get_generic_be;
2172 hal_soc->ops->hal_rx_priv_info_set_in_tlv =
2173 hal_rx_priv_info_set_in_tlv_be;
2174 hal_soc->ops->hal_rx_priv_info_get_from_tlv =
2175 hal_rx_priv_info_get_from_tlv_be;
2176
2177 hal_soc->ops->hal_tx_set_pcp_tid_map =
2178 hal_tx_set_pcp_tid_map_generic_be;
2179 hal_soc->ops->hal_tx_update_pcp_tid_map =
2180 hal_tx_update_pcp_tid_generic_be;
2181 hal_soc->ops->hal_tx_set_tidmap_prty =
2182 hal_tx_update_tidmap_prty_generic_be;
2183 hal_soc->ops->hal_rx_get_rx_fragment_number =
2184 hal_rx_get_rx_fragment_number_be;
2185 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
2186 hal_rx_tlv_da_is_mcbc_get_be;
2187 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
2188 hal_rx_tlv_sa_is_valid_get_be;
2189 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be,
2190 hal_soc->ops->hal_rx_desc_is_first_msdu =
2191 hal_rx_desc_is_first_msdu_be;
2192 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
2193 hal_rx_tlv_l3_hdr_padding_get_be;
2194 hal_soc->ops->hal_rx_encryption_info_valid =
2195 hal_rx_encryption_info_valid_be;
2196 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
2197 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
2198 hal_rx_tlv_first_msdu_get_be;
2199 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
2200 hal_rx_tlv_da_is_valid_get_be;
2201 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
2202 hal_rx_tlv_last_msdu_get_be;
2203 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
2204 hal_rx_get_mpdu_mac_ad4_valid_be;
2205 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
2206 hal_rx_mpdu_start_sw_peer_id_get_be;
2207 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
2208 hal_rx_mpdu_peer_meta_data_get_be;
2209 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
2210 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
2211 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
2212 hal_rx_get_mpdu_frame_control_valid_be;
2213 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
2214 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
2215 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
2216 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
2217 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
2218 hal_rx_get_mpdu_sequence_control_valid_be;
2219 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
2220 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
2221 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
2222 hal_rx_hw_desc_get_ppduid_get_be;
2223 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
2224 hal_rx_msdu0_buffer_addr_lsb_kiwi;
2225 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
2226 hal_rx_msdu_desc_info_ptr_get_kiwi;
2227 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_kiwi;
2228 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_kiwi;
2229 hal_soc->ops->hal_rx_phy_legacy_get_rssi =
2230 hal_rx_phy_legacy_get_rssi_kiwi;
2231 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
2232 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
2233 hal_soc->ops->hal_rx_get_mac_addr2_valid =
2234 hal_rx_get_mac_addr2_valid_be;
2235 hal_soc->ops->hal_rx_get_filter_category =
2236 hal_rx_get_filter_category_be;
2237 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
2238 hal_soc->ops->hal_reo_config = hal_reo_config_kiwi;
2239 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
2240 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
2241 hal_rx_msdu_flow_idx_invalid_be;
2242 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
2243 hal_rx_msdu_flow_idx_timeout_be;
2244 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
2245 hal_rx_msdu_fse_metadata_get_be;
2246 hal_soc->ops->hal_rx_msdu_cce_match_get =
2247 hal_rx_msdu_cce_match_get_be;
2248 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
2249 hal_rx_msdu_cce_metadata_get_be;
2250 hal_soc->ops->hal_rx_msdu_get_flow_params =
2251 hal_rx_msdu_get_flow_params_be;
2252 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
2253 hal_rx_tlv_get_tcp_chksum_be;
2254 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
2255 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \
2256 defined(WLAN_ENH_CFR_ENABLE)
2257 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_kiwi;
2258 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_kiwi;
2259 #else
2260 hal_soc->ops->hal_rx_get_bb_info = NULL;
2261 hal_soc->ops->hal_rx_get_rtt_info = NULL;
2262 #endif
2263 /* rx - msdu end fast path info fields */
2264 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
2265 hal_rx_msdu_packet_metadata_get_generic_be;
2266 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
2267 hal_rx_get_fisa_cumulative_l4_checksum_be;
2268 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
2269 hal_rx_get_fisa_cumulative_ip_length_be;
2270 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_be;
2271 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
2272 hal_rx_get_flow_agg_continuation_be;
2273 hal_soc->ops->hal_rx_get_fisa_flow_agg_count =
2274 hal_rx_get_flow_agg_count_be;
2275 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_be;
2276 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
2277 hal_rx_mpdu_start_tlv_tag_valid_be;
2278 hal_soc->ops->hal_rx_reo_prev_pn_get = hal_rx_reo_prev_pn_get_kiwi;
2279
2280 /* rx - TLV struct offsets */
2281 hal_register_rx_pkt_hdr_tlv_api_kiwi(hal_soc);
2282 hal_soc->ops->hal_rx_msdu_end_offset_get =
2283 hal_rx_msdu_end_offset_get_generic;
2284 hal_soc->ops->hal_rx_mpdu_start_offset_get =
2285 hal_rx_mpdu_start_offset_get_generic;
2286 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_kiwi;
2287 hal_soc->ops->hal_rx_flow_get_tuple_info =
2288 hal_rx_flow_get_tuple_info_be;
2289 hal_soc->ops->hal_rx_flow_delete_entry =
2290 hal_rx_flow_delete_entry_be;
2291 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
2292 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
2293 hal_compute_reo_remap_ix2_ix3_kiwi;
2294 hal_soc->ops->hal_rx_flow_setup_cmem_fse =
2295 hal_rx_flow_setup_cmem_fse_kiwi;
2296 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts =
2297 hal_rx_flow_get_cmem_fse_ts_kiwi;
2298 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_kiwi;
2299 hal_soc->ops->hal_cmem_write = hal_cmem_write_kiwi;
2300 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
2301 hal_rx_msdu_get_reo_destination_indication_be;
2302 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_kiwi;
2303 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
2304 hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
2305 hal_rx_msdu_is_wlan_mcast_generic_be;
2306 hal_soc->ops->hal_rx_tlv_bw_get =
2307 hal_rx_tlv_bw_get_be;
2308 hal_soc->ops->hal_rx_tlv_get_is_decrypted =
2309 hal_rx_tlv_get_is_decrypted_be;
2310 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
2311 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
2312 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
2313 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
2314 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get =
2315 hal_rx_tlv_mpdu_len_err_get_be;
2316 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get =
2317 hal_rx_tlv_mpdu_fcs_err_get_be;
2318
2319 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
2320 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
2321 hal_rx_tlv_decrypt_err_get_be;
2322 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
2323 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
2324 hal_soc->ops->hal_rx_tlv_decap_format_get =
2325 hal_rx_tlv_decap_format_get_be;
2326 hal_soc->ops->hal_rx_tlv_get_offload_info =
2327 hal_rx_tlv_get_offload_info_be;
2328 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
2329 hal_rx_attn_phy_ppdu_id_get_be;
2330 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_tlv_msdu_done_get_be;
2331 hal_soc->ops->hal_rx_tlv_msdu_len_get =
2332 hal_rx_msdu_start_msdu_len_get_be;
2333 hal_soc->ops->hal_rx_get_frame_ctrl_field =
2334 hal_rx_get_frame_ctrl_field_be;
2335 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
2336 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
2337 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
2338 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
2339 hal_rx_mpdu_info_ampdu_flag_get_be;
2340 hal_soc->ops->hal_rx_tlv_msdu_len_set =
2341 hal_rx_msdu_start_msdu_len_set_be;
2342 hal_soc->ops->hal_rx_tlv_populate_mpdu_desc_info =
2343 hal_rx_tlv_populate_mpdu_desc_info_kiwi;
2344 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_kiwi;
2345 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
2346 hal_soc->ops->hal_get_first_wow_wakeup_packet =
2347 hal_get_first_wow_wakeup_packet_kiwi;
2348 #endif
2349 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
2350
2351 hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be;
2352 hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
2353 hal_tx_vdev_mismatch_routing_set_generic_be;
2354 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
2355 hal_tx_mcast_mlo_reinject_routing_set_generic_be;
2356 hal_soc->ops->hal_get_ba_aging_timeout =
2357 hal_get_ba_aging_timeout_be_generic;
2358 hal_soc->ops->hal_setup_link_idle_list =
2359 hal_setup_link_idle_list_generic_be;
2360 hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
2361 hal_cookie_conversion_reg_cfg_generic_be;
2362 hal_soc->ops->hal_set_ba_aging_timeout =
2363 hal_set_ba_aging_timeout_be_generic;
2364 hal_soc->ops->hal_tx_populate_bank_register =
2365 hal_tx_populate_bank_register_be;
2366 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
2367 hal_tx_vdev_mcast_ctrl_set_be;
2368 hal_soc->ops->hal_get_tsf_time = hal_get_tsf_time_kiwi;
2369 hal_soc->ops->hal_rx_reo_ent_get_src_link_id =
2370 hal_rx_reo_ent_get_src_link_id_kiwi;
2371 #ifdef FEATURE_DIRECT_LINK
2372 hal_soc->ops->hal_srng_set_msi_config = hal_srng_set_msi_config;
2373 #endif
2374 hal_soc->ops->hal_rx_en_mcast_fp_data_filter =
2375 hal_rx_en_mcast_fp_data_filter_kiwi;
2376 #ifdef WLAN_PKT_CAPTURE_TX_2_0
2377 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
2378 hal_txmon_is_mon_buf_addr_tlv_generic_be;
2379 hal_soc->ops->hal_txmon_populate_packet_info =
2380 hal_txmon_populate_packet_info_generic_be;
2381 hal_soc->ops->hal_txmon_status_parse_tlv =
2382 hal_txmon_status_parse_tlv_generic_be;
2383 hal_soc->ops->hal_txmon_status_get_num_users =
2384 hal_txmon_status_get_num_users_generic_be;
2385 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
2386 };
2387
2388 struct hal_hw_srng_config hw_srng_table_kiwi[] = {
2389 /* TODO: max_rings can populated by querying HW capabilities */
2390 { /* REO_DST */
2391 .start_ring_id = HAL_SRNG_REO2SW1,
2392 .max_rings = 8,
2393 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2394 .lmac_ring = FALSE,
2395 .ring_dir = HAL_SRNG_DST_RING,
2396 .nf_irq_support = true,
2397 .reg_start = {
2398 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
2399 REO_REG_REG_BASE),
2400 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
2401 REO_REG_REG_BASE)
2402 },
2403 .reg_size = {
2404 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
2405 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
2406 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
2407 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
2408 },
2409 .max_size =
2410 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
2411 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
2412 },
2413 { /* REO_EXCEPTION */
2414 /* Designating REO2SW0 ring as exception ring. */
2415 .start_ring_id = HAL_SRNG_REO2SW0,
2416 .max_rings = 1,
2417 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2418 .lmac_ring = FALSE,
2419 .ring_dir = HAL_SRNG_DST_RING,
2420 .reg_start = {
2421 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
2422 REO_REG_REG_BASE),
2423 HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
2424 REO_REG_REG_BASE)
2425 },
2426 /* Single ring - provide ring size if multiple rings of this
2427 * type are supported
2428 */
2429 .reg_size = {},
2430 .max_size =
2431 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
2432 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
2433 },
2434 { /* REO_REINJECT */
2435 .start_ring_id = HAL_SRNG_SW2REO,
2436 .max_rings = 1,
2437 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2438 .lmac_ring = FALSE,
2439 .ring_dir = HAL_SRNG_SRC_RING,
2440 .reg_start = {
2441 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
2442 REO_REG_REG_BASE),
2443 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
2444 REO_REG_REG_BASE)
2445 },
2446 /* Single ring - provide ring size if multiple rings of this
2447 * type are supported
2448 */
2449 .reg_size = {},
2450 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
2451 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
2452 },
2453 { /* REO_CMD */
2454 .start_ring_id = HAL_SRNG_REO_CMD,
2455 .max_rings = 1,
2456 .entry_size = (sizeof(struct tlv_32_hdr) +
2457 sizeof(struct reo_get_queue_stats)) >> 2,
2458 .lmac_ring = FALSE,
2459 .ring_dir = HAL_SRNG_SRC_RING,
2460 .reg_start = {
2461 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
2462 REO_REG_REG_BASE),
2463 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
2464 REO_REG_REG_BASE),
2465 },
2466 /* Single ring - provide ring size if multiple rings of this
2467 * type are supported
2468 */
2469 .reg_size = {},
2470 .max_size =
2471 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
2472 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
2473 },
2474 { /* REO_STATUS */
2475 .start_ring_id = HAL_SRNG_REO_STATUS,
2476 .max_rings = 1,
2477 .entry_size = (sizeof(struct tlv_32_hdr) +
2478 sizeof(struct reo_get_queue_stats_status)) >> 2,
2479 .lmac_ring = FALSE,
2480 .ring_dir = HAL_SRNG_DST_RING,
2481 .reg_start = {
2482 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
2483 REO_REG_REG_BASE),
2484 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
2485 REO_REG_REG_BASE),
2486 },
2487 /* Single ring - provide ring size if multiple rings of this
2488 * type are supported
2489 */
2490 .reg_size = {},
2491 .max_size =
2492 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2493 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2494 },
2495 { /* TCL_DATA */
2496 .start_ring_id = HAL_SRNG_SW2TCL1,
2497 .max_rings = 5,
2498 .entry_size = sizeof(struct tcl_data_cmd) >> 2,
2499 .lmac_ring = FALSE,
2500 .ring_dir = HAL_SRNG_SRC_RING,
2501 .reg_start = {
2502 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
2503 MAC_TCL_REG_REG_BASE),
2504 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
2505 MAC_TCL_REG_REG_BASE),
2506 },
2507 .reg_size = {
2508 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
2509 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
2510 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
2511 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
2512 },
2513 .max_size =
2514 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
2515 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
2516 },
2517 { /* TCL_CMD */
2518 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
2519 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG
2520 .max_rings = 1,
2521 #else
2522 .max_rings = 0,
2523 #endif
2524 .entry_size = sizeof(struct tcl_gse_cmd) >> 2,
2525 .lmac_ring = FALSE,
2526 .ring_dir = HAL_SRNG_SRC_RING,
2527 .reg_start = {
2528 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
2529 MAC_TCL_REG_REG_BASE),
2530 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
2531 MAC_TCL_REG_REG_BASE),
2532 },
2533 /* Single ring - provide ring size if multiple rings of this
2534 * type are supported
2535 */
2536 .reg_size = {},
2537 .max_size =
2538 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
2539 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
2540 },
2541 { /* TCL_STATUS */
2542 .start_ring_id = HAL_SRNG_TCL_STATUS,
2543 #ifndef WLAN_DP_DISABLE_TCL_CMD_CRED_SRNG
2544 .max_rings = 1,
2545 #else
2546 .max_rings = 0,
2547 #endif
2548 /* confirm that TLV header is needed */
2549 .entry_size = sizeof(struct tcl_status_ring) >> 2,
2550 .lmac_ring = FALSE,
2551 .ring_dir = HAL_SRNG_DST_RING,
2552 .reg_start = {
2553 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
2554 MAC_TCL_REG_REG_BASE),
2555 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
2556 MAC_TCL_REG_REG_BASE),
2557 },
2558 /* Single ring - provide ring size if multiple rings of this
2559 * type are supported
2560 */
2561 .reg_size = {},
2562 .max_size =
2563 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
2564 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
2565 },
2566 { /* CE_SRC */
2567 .start_ring_id = HAL_SRNG_CE_0_SRC,
2568 .max_rings = 12,
2569 .entry_size = sizeof(struct ce_src_desc) >> 2,
2570 .lmac_ring = FALSE,
2571 .ring_dir = HAL_SRNG_SRC_RING,
2572 .reg_start = {
2573 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,
2574 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,
2575 },
2576 .reg_size = {
2577 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
2578 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
2579 SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
2580 SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
2581 },
2582 .max_size =
2583 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
2584 HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
2585 },
2586 { /* CE_DST */
2587 .start_ring_id = HAL_SRNG_CE_0_DST,
2588 .max_rings = 12,
2589 .entry_size = 8 >> 2,
2590 /*TODO: entry_size above should actually be
2591 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
2592 * of struct ce_dst_desc in HW header files
2593 */
2594 .lmac_ring = FALSE,
2595 .ring_dir = HAL_SRNG_SRC_RING,
2596 .reg_start = {
2597 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,
2598 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,
2599 },
2600 .reg_size = {
2601 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
2602 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
2603 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
2604 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
2605 },
2606 .max_size =
2607 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2608 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
2609 },
2610 { /* CE_DST_STATUS */
2611 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
2612 .max_rings = 12,
2613 .entry_size = sizeof(struct ce_stat_desc) >> 2,
2614 .lmac_ring = FALSE,
2615 .ring_dir = HAL_SRNG_DST_RING,
2616 .reg_start = {
2617 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,
2618 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,
2619 },
2620 .reg_size = {
2621 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
2622 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
2623 SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
2624 SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
2625 },
2626 .max_size =
2627 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2628 HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2629 },
2630 { /* WBM_IDLE_LINK */
2631 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
2632 .max_rings = 1,
2633 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
2634 .lmac_ring = FALSE,
2635 .ring_dir = HAL_SRNG_SRC_RING,
2636 .reg_start = {
2637 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
2638 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
2639 },
2640 /* Single ring - provide ring size if multiple rings of this
2641 * type are supported
2642 */
2643 .reg_size = {},
2644 .max_size =
2645 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
2646 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
2647 },
2648 { /* SW2WBM_RELEASE */
2649 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
2650 .max_rings = 1,
2651 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2652 .lmac_ring = FALSE,
2653 .ring_dir = HAL_SRNG_SRC_RING,
2654 .reg_start = {
2655 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
2656 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
2657 },
2658 /* Single ring - provide ring size if multiple rings of this
2659 * type are supported
2660 */
2661 .reg_size = {},
2662 .max_size =
2663 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2664 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2665 },
2666 { /* WBM2SW_RELEASE */
2667 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
2668 .max_rings = 8,
2669 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2670 .lmac_ring = FALSE,
2671 .ring_dir = HAL_SRNG_DST_RING,
2672 .nf_irq_support = true,
2673 .reg_start = {
2674 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
2675 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
2676 },
2677 .reg_size = {
2678 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) -
2679 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
2680 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) -
2681 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
2682 },
2683 .max_size =
2684 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2685 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2686 },
2687 { /* RXDMA_BUF */
2688 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
2689 #if defined(IPA_OFFLOAD) && defined(FEATURE_DIRECT_LINK)
2690 .max_rings = 4,
2691 #elif defined(IPA_OFFLOAD) || defined(FEATURE_DIRECT_LINK)
2692 .max_rings = 3,
2693 #else
2694 .max_rings = 2,
2695 #endif
2696 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2697 .lmac_ring = TRUE,
2698 .ring_dir = HAL_SRNG_SRC_RING,
2699 /* reg_start is not set because LMAC rings are not accessed
2700 * from host
2701 */
2702 .reg_start = {},
2703 .reg_size = {},
2704 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2705 },
2706 { /* RXDMA_DST */
2707 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
2708 .max_rings = 1,
2709 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2710 .lmac_ring = TRUE,
2711 .ring_dir = HAL_SRNG_DST_RING,
2712 /* reg_start is not set because LMAC rings are not accessed
2713 * from host
2714 */
2715 .reg_start = {},
2716 .reg_size = {},
2717 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2718 },
2719 { /* RXDMA_MONITOR_BUF */
2720 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
2721 .max_rings = 1,
2722 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2723 .lmac_ring = TRUE,
2724 .ring_dir = HAL_SRNG_SRC_RING,
2725 /* reg_start is not set because LMAC rings are not accessed
2726 * from host
2727 */
2728 .reg_start = {},
2729 .reg_size = {},
2730 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2731 },
2732 { /* RXDMA_MONITOR_STATUS */
2733 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
2734 .max_rings = 1,
2735 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2736 .lmac_ring = TRUE,
2737 .ring_dir = HAL_SRNG_SRC_RING,
2738 /* reg_start is not set because LMAC rings are not accessed
2739 * from host
2740 */
2741 .reg_start = {},
2742 .reg_size = {},
2743 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2744 },
2745 { /* RXDMA_MONITOR_DST */
2746 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
2747 .max_rings = 1,
2748 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2749 .lmac_ring = TRUE,
2750 .ring_dir = HAL_SRNG_DST_RING,
2751 /* reg_start is not set because LMAC rings are not accessed
2752 * from host
2753 */
2754 .reg_start = {},
2755 .reg_size = {},
2756 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2757 },
2758 { /* RXDMA_MONITOR_DESC */
2759 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2760 .max_rings = 1,
2761 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2762 .lmac_ring = TRUE,
2763 .ring_dir = HAL_SRNG_SRC_RING,
2764 /* reg_start is not set because LMAC rings are not accessed
2765 * from host
2766 */
2767 .reg_start = {},
2768 .reg_size = {},
2769 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2770 },
2771 { /* DIR_BUF_RX_DMA_SRC */
2772 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2773 /*
2774 * one ring is for spectral scan
2775 * the other is for cfr
2776 */
2777 .max_rings = 2,
2778 .entry_size = 2,
2779 .lmac_ring = TRUE,
2780 .ring_dir = HAL_SRNG_SRC_RING,
2781 /* reg_start is not set because LMAC rings are not accessed
2782 * from host
2783 */
2784 .reg_start = {},
2785 .reg_size = {},
2786 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2787 },
2788 #ifdef WLAN_FEATURE_CIF_CFR
2789 { /* WIFI_POS_SRC */
2790 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2791 .max_rings = 1,
2792 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2793 .lmac_ring = TRUE,
2794 .ring_dir = HAL_SRNG_SRC_RING,
2795 /* reg_start is not set because LMAC rings are not accessed
2796 * from host
2797 */
2798 .reg_start = {},
2799 .reg_size = {},
2800 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2801 },
2802 #endif
2803 { /* REO2PPE */ 0},
2804 { /* PPE2TCL */ 0},
2805 { /* PPE_RELEASE */ 0},
2806 #ifdef WLAN_PKT_CAPTURE_TX_2_0
2807 { /* TX_MONITOR_BUF */
2808 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
2809 .max_rings = 1,
2810 .entry_size = sizeof(struct mon_ingress_ring) >> 2,
2811 .lmac_ring = TRUE,
2812 .ring_dir = HAL_SRNG_SRC_RING,
2813 /* reg_start is not set because LMAC rings are not accessed
2814 * from host
2815 */
2816 .reg_start = {},
2817 .reg_size = {},
2818 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2819 },
2820 { /* TX_MONITOR_DST */
2821 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
2822 .max_rings = 2,
2823 .entry_size = sizeof(struct mon_destination_ring) >> 2,
2824 .lmac_ring = TRUE,
2825 .ring_dir = HAL_SRNG_DST_RING,
2826 /* reg_start is not set because LMAC rings are not accessed
2827 * from host
2828 */
2829 .reg_start = {},
2830 .reg_size = {},
2831 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2832 },
2833 #else
2834 {0},
2835 {0},
2836 #endif
2837 { /* SW2RXDMA_NEW */ 0},
2838 { /* SW2RXDMA_LINK_RELEASE */ 0},
2839 };
2840
2841 /**
2842 * hal_srng_hw_reg_offset_init_kiwi() - Initialize the HW srng reg offset
2843 * applicable only for KIWI
2844 * @hal_soc: HAL Soc handle
2845 *
2846 * Return: None
2847 */
hal_srng_hw_reg_offset_init_kiwi(struct hal_soc * hal_soc)2848 static inline void hal_srng_hw_reg_offset_init_kiwi(struct hal_soc *hal_soc)
2849 {
2850 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2851
2852 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
2853 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
2854 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
2855 hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
2856 REG_OFFSET(DST, PRODUCER_INT2_SETUP);
2857 hal_srng_hw_reg_offset_init_misc_1_kiwi(hal_soc);
2858 }
2859
hal_kiwi_attach(struct hal_soc * hal_soc)2860 void hal_kiwi_attach(struct hal_soc *hal_soc)
2861 {
2862 hal_soc->hw_srng_table = hw_srng_table_kiwi;
2863
2864 hal_srng_hw_reg_offset_init_generic(hal_soc);
2865 hal_srng_hw_reg_offset_init_kiwi(hal_soc);
2866 hal_hw_txrx_default_ops_attach_be(hal_soc);
2867 hal_hw_txrx_ops_attach_kiwi(hal_soc);
2868 }
2869