xref: /wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/kiwi/hal_kiwi_rx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _HAL_KIWI_RX_H_
21 #define _HAL_KIWI_RX_H_
22 #include "qdf_util.h"
23 #include "qdf_types.h"
24 #include "qdf_lock.h"
25 #include "qdf_mem.h"
26 #include "qdf_nbuf.h"
27 #include "tcl_data_cmd.h"
28 //#include "mac_tcl_reg_seq_hwioreg.h"
29 #include "phyrx_rssi_legacy.h"
30 #include "rx_msdu_start.h"
31 #include "tlv_tag_def.h"
32 #include "hal_hw_headers.h"
33 #include "hal_internal.h"
34 #include "cdp_txrx_mon_struct.h"
35 #include "qdf_trace.h"
36 #include "hal_rx.h"
37 #include "hal_tx.h"
38 #include "dp_types.h"
39 #include "hal_api_mon.h"
40 #include "phyrx_other_receive_info_ru_details.h"
41 
42 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va)	\
43 	(uint8_t *)(link_desc_va) +			\
44 	RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
45 
46 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0)			\
47 	(uint8_t *)(msdu0) +				\
48 	RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
49 
50 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc)		\
51 	(uint8_t *)(ent_ring_desc) +			\
52 	RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
53 
54 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc)		\
55 	(uint8_t *)(dst_ring_desc) +			\
56 	REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
57 
58 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
59 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
60 
61 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start)	\
62 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
63 
64 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start)	\
65 	HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_PEER_ID)
66 
67 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params)		\
68 	do { \
69 		reg_val &= \
70 			~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
71 			HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
72 		reg_val |= \
73 			HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
74 			       AGING_LIST_ENABLE, 1) |\
75 			HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
76 			       AGING_FLUSH_ENABLE, 1);\
77 		HAL_REG_WRITE((soc), \
78 			      HWIO_REO_R0_GENERAL_ENABLE_ADDR(	\
79 			      REO_REG_REG_BASE), \
80 			      (reg_val));		\
81 		reg_val = \
82 			HAL_REG_READ((soc), \
83 				     HWIO_REO_R0_MISC_CTL_ADDR(	\
84 				     REO_REG_REG_BASE)); \
85 		reg_val &= \
86 			~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
87 		reg_val |= \
88 			HAL_SM(HWIO_REO_R0_MISC_CTL,	\
89 			       FRAGMENT_DEST_RING, \
90 			       (reo_params)->frag_dst_ring); \
91 		reg_val &= \
92 			(~HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK |\
93 				(REO_REMAP_TCL << HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT)); \
94 		HAL_REG_WRITE((soc), \
95 			      HWIO_REO_R0_MISC_CTL_ADDR( \
96 			      REO_REG_REG_BASE), \
97 			      (reg_val)); \
98 	} while (0)
99 
100 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
101 	((struct rx_msdu_desc_info *) \
102 	_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
103 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
104 
105 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc)   \
106 	((struct rx_msdu_details *) \
107 	 _OFFSET_TO_BYTE_PTR((link_desc),\
108 	RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
109 
110 #if defined(QCA_WIFI_KIWI) && defined(WLAN_CFR_ENABLE) && \
111 	defined(WLAN_ENH_CFR_ENABLE)
112 
113 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006
114 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1
115 #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2
116 
117 #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \
118 	((HAL_RX_GET_64((rx_tlv), \
119 		     PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \
120 		     RTT_CFR_STATUS) & \
121 	  PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \
122 	 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB)
123 
124 static inline
hal_rx_get_bb_info_kiwi(void * rx_tlv,void * ppdu_info_hdl)125 void hal_rx_get_bb_info_kiwi(void *rx_tlv,
126 			     void *ppdu_info_hdl)
127 {
128 	struct hal_rx_ppdu_info *ppdu_info  = ppdu_info_hdl;
129 
130 	ppdu_info->cfr_info.bb_captured_channel =
131 	  HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
132 
133 	ppdu_info->cfr_info.bb_captured_timeout =
134 	  HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
135 
136 	ppdu_info->cfr_info.bb_captured_reason =
137 	  HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
138 }
139 
140 static inline
hal_rx_get_rtt_info_kiwi(void * rx_tlv,void * ppdu_info_hdl)141 void hal_rx_get_rtt_info_kiwi(void *rx_tlv,
142 			      void *ppdu_info_hdl)
143 {
144 	struct hal_rx_ppdu_info *ppdu_info  = ppdu_info_hdl;
145 
146 	ppdu_info->cfr_info.rx_location_info_valid =
147 	HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
148 		      RX_LOCATION_INFO_VALID);
149 
150 	ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
151 	HAL_RX_GET_64(rx_tlv,
152 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
153 		      RTT_CHE_BUFFER_POINTER_LOW32);
154 
155 	ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
156 	HAL_RX_GET_64(rx_tlv,
157 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
158 		      RTT_CHE_BUFFER_POINTER_HIGH8);
159 
160 	ppdu_info->cfr_info.chan_capture_status =
161 	HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
162 
163 	ppdu_info->cfr_info.rx_start_ts =
164 	HAL_RX_GET_64(rx_tlv,
165 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
166 		      RX_START_TS);
167 
168 	ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
169 	HAL_RX_GET_64(rx_tlv,
170 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
171 		      RTT_CFO_MEASUREMENT);
172 
173 	ppdu_info->cfr_info.agc_gain_info0 =
174 	HAL_RX_GET_64(rx_tlv,
175 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
176 		      GAIN_CHAIN0);
177 
178 	ppdu_info->cfr_info.agc_gain_info0 |=
179 	(((uint32_t)HAL_RX_GET_64(rx_tlv,
180 		    PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
181 		    GAIN_CHAIN1)) << 16);
182 
183 	ppdu_info->cfr_info.agc_gain_info1 =
184 	HAL_RX_GET_64(rx_tlv,
185 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
186 		      GAIN_CHAIN2);
187 
188 	ppdu_info->cfr_info.agc_gain_info1 |=
189 	(((uint32_t)HAL_RX_GET_64(rx_tlv,
190 		    PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
191 		    GAIN_CHAIN3)) << 16);
192 
193 	ppdu_info->cfr_info.agc_gain_info2 = 0;
194 
195 	ppdu_info->cfr_info.agc_gain_info3 = 0;
196 
197 	ppdu_info->cfr_info.mcs_rate =
198 	HAL_RX_GET_64(rx_tlv,
199 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
200 		      RTT_MCS_RATE);
201 
202 	ppdu_info->cfr_info.gi_type =
203 	HAL_RX_GET_64(rx_tlv,
204 		      PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
205 		      RTT_GI_TYPE);
206 }
207 #endif
208 #endif
209