xref: /wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/li/hal_li_generic_api.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #ifndef _HAL_LI_GENERIC_API_H_
21 #define _HAL_LI_GENERIC_API_H_
22 
23 #include "hal_tx.h"
24 #include "hal_li_tx.h"
25 #include "hal_li_rx.h"
26 
27 #define HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc)	\
28 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc,	\
29 		WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET)),	\
30 		WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK, \
31 		WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB))
32 
33 #define HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc)		\
34 	(_HAL_MS((*_OFFSET_TO_WORD_PTR(wbm_desc,	\
35 		WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET)),	\
36 		WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK, \
37 		WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB))
38 
39 #define HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc)	\
40 	(((*(((uint32_t *)wbm_desc) +			\
41 	(WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET >> 2))) & \
42 	WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK) >>	\
43 	WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB)
44 
45 #define HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc)	\
46 	(((*(((uint32_t *)wbm_desc) +			\
47 	(WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET >> 2))) & \
48 	WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK) >>	\
49 	WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB)
50 
51 /**
52  * hal_rx_wbm_err_info_get_generic_li() - Retrieves WBM error code and
53  *	reason and save it to hal_wbm_err_desc_info structure passed
54  *	by caller
55  * @wbm_desc: wbm ring descriptor
56  * @wbm_er_info1: hal_wbm_err_desc_info structure, output parameter.
57  *
58  * Return: void
59  */
60 static inline
hal_rx_wbm_err_info_get_generic_li(void * wbm_desc,void * wbm_er_info1)61 void hal_rx_wbm_err_info_get_generic_li(void *wbm_desc,
62 					void *wbm_er_info1)
63 {
64 	struct hal_wbm_err_desc_info *wbm_er_info =
65 		(struct hal_wbm_err_desc_info *)wbm_er_info1;
66 
67 	wbm_er_info->wbm_err_src = HAL_WBM2SW_RELEASE_SRC_GET(wbm_desc);
68 	wbm_er_info->reo_psh_rsn = HAL_RX_WBM_REO_PUSH_REASON_GET(wbm_desc);
69 	wbm_er_info->reo_err_code = HAL_RX_WBM_REO_ERROR_CODE_GET(wbm_desc);
70 	wbm_er_info->rxdma_psh_rsn = HAL_RX_WBM_RXDMA_PUSH_REASON_GET(wbm_desc);
71 	wbm_er_info->rxdma_err_code = HAL_RX_WBM_RXDMA_ERROR_CODE_GET(wbm_desc);
72 }
73 
74 #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY)
75 static inline void
hal_tx_comp_get_buffer_timestamp_li(void * desc,struct hal_tx_completion_status * ts)76 hal_tx_comp_get_buffer_timestamp_li(void *desc,
77 				    struct hal_tx_completion_status *ts)
78 {
79 	ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
80 					       BUFFER_TIMESTAMP);
81 }
82 #else /* !(WLAN_FEATURE_TSF_AUTO_REPORT || WLAN_CONFIG_TX_DELAY) */
83 static inline void
hal_tx_comp_get_buffer_timestamp_li(void * desc,struct hal_tx_completion_status * ts)84 hal_tx_comp_get_buffer_timestamp_li(void *desc,
85 				    struct hal_tx_completion_status *ts)
86 {
87 }
88 #endif /* WLAN_FEATURE_TSF_AUTO_REPORT || WLAN_CONFIG_TX_DELAY */
89 
90 #ifdef QCA_UNDECODED_METADATA_SUPPORT
91 static inline void
hal_rx_get_phyrx_abort(struct hal_soc * hal,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)92 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
93 		       struct hal_rx_ppdu_info *ppdu_info){
94 	switch (hal->target_type) {
95 	case TARGET_TYPE_QCN9000:
96 	case TARGET_TYPE_QCN9160:
97 		ppdu_info->rx_status.phyrx_abort =
98 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2,
99 				   PHYRX_ABORT_REQUEST_INFO_VALID);
100 		ppdu_info->rx_status.phyrx_abort_reason =
101 			HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11,
102 				   PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON);
103 		break;
104 	default:
105 		break;
106 	}
107 }
108 
109 static inline void
hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * ht_sig_info)110 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
111 		       uint8_t *ht_sig_info)
112 {
113 	ppdu_info->rx_status.ht_length =
114 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH);
115 	ppdu_info->rx_status.smoothing =
116 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING);
117 	ppdu_info->rx_status.not_sounding =
118 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING);
119 	ppdu_info->rx_status.aggregation =
120 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION);
121 	ppdu_info->rx_status.ht_stbc =
122 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC);
123 	ppdu_info->rx_status.ht_crc =
124 		HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC);
125 }
126 
127 static inline void
hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * l_sig_a_info)128 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
129 			uint8_t *l_sig_a_info)
130 {
131 	ppdu_info->rx_status.l_sig_length =
132 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH);
133 	ppdu_info->rx_status.l_sig_a_parity =
134 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY);
135 	ppdu_info->rx_status.l_sig_a_pkt_type =
136 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE);
137 	ppdu_info->rx_status.l_sig_a_implicit_sounding =
138 		HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0,
139 			   CAPTURED_IMPLICIT_SOUNDING);
140 }
141 
142 static inline void
hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * vht_sig_a_info)143 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
144 			  uint8_t *vht_sig_a_info)
145 {
146 	ppdu_info->rx_status.vht_no_txop_ps =
147 		HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
148 			   TXOP_PS_NOT_ALLOWED);
149 	ppdu_info->rx_status.vht_crc =
150 		HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC);
151 }
152 
153 static inline void
hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_su_info)154 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
155 				uint8_t *he_sig_a_su_info) {
156 	ppdu_info->rx_status.he_crc =
157 		HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC);
158 }
159 
160 static inline void
hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_mu_dl_info)161 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
162 				   uint8_t *he_sig_a_mu_dl_info) {
163 	ppdu_info->rx_status.he_crc =
164 		HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC);
165 }
166 #else
167 static inline void
hal_rx_get_phyrx_abort(struct hal_soc * hal,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)168 hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv,
169 		       struct hal_rx_ppdu_info *ppdu_info)
170 {
171 }
172 
173 static inline void
hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * ht_sig_info)174 hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info,
175 		       uint8_t *ht_sig_info)
176 {
177 }
178 
179 static inline void
hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * l_sig_a_info)180 hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
181 			uint8_t *l_sig_a_info)
182 {
183 }
184 
185 static inline void
hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * vht_sig_a_info)186 hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info,
187 			  uint8_t *vht_sig_a_info)
188 {
189 }
190 
191 static inline void
hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_su_info)192 hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info,
193 				uint8_t *he_sig_a_su_info)
194 {
195 }
196 
197 static inline void
hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info * ppdu_info,uint8_t * he_sig_a_mu_dl_info)198 hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info,
199 				   uint8_t *he_sig_a_mu_dl_info)
200 {
201 }
202 #endif /* QCA_UNDECODED_METADATA_SUPPORT */
203 
204 /**
205  * hal_tx_comp_get_status_generic_li() - Get tx completion status
206  * @desc: tx descriptor
207  * @ts1: completion ring Tx status
208  * @hal: hal_soc object
209  *
210  * This function will parse the WBM completion descriptor and populate in
211  * HAL structure
212  *
213  * Return: none
214  */
215 static inline void
hal_tx_comp_get_status_generic_li(void * desc,void * ts1,struct hal_soc * hal)216 hal_tx_comp_get_status_generic_li(void *desc, void *ts1,
217 				  struct hal_soc *hal)
218 {
219 	uint8_t rate_stats_valid = 0;
220 	uint32_t rate_stats = 0;
221 	struct hal_tx_completion_status *ts =
222 		(struct hal_tx_completion_status *)ts1;
223 
224 	ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
225 			TQM_STATUS_NUMBER);
226 	ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
227 			ACK_FRAME_RSSI);
228 	ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
229 	ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
230 	ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
231 			MSDU_PART_OF_AMSDU);
232 
233 	ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID);
234 	ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID);
235 	ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
236 			TRANSMIT_COUNT);
237 
238 	rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS);
239 
240 	rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0,
241 			TX_RATE_STATS_INFO_VALID, rate_stats);
242 
243 	ts->valid = rate_stats_valid;
244 
245 	if (rate_stats_valid) {
246 		ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW,
247 				rate_stats);
248 		ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0,
249 				TRANSMIT_PKT_TYPE, rate_stats);
250 		ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0,
251 				TRANSMIT_STBC, rate_stats);
252 		ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC,
253 				rate_stats);
254 		ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI,
255 				rate_stats);
256 		ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS,
257 				rate_stats);
258 		ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION,
259 				rate_stats);
260 		ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU,
261 				rate_stats);
262 	}
263 
264 	ts->release_src = hal_tx_comp_get_buffer_source(
265 					hal_soc_to_hal_soc_handle(hal),
266 					desc);
267 	ts->status = hal_tx_comp_get_release_reason(
268 					desc,
269 					hal_soc_to_hal_soc_handle(hal));
270 
271 	ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6,
272 			TX_RATE_STATS_INFO_TX_RATE_STATS);
273 
274 	hal_tx_comp_get_buffer_timestamp_li(desc, ts);
275 }
276 
277 /**
278  * hal_tx_desc_set_buf_addr_generic_li() - Fill Buffer Address
279  *                                         information in Tx Descriptor
280  * @desc: Handle to Tx Descriptor
281  * @paddr: Physical Address
282  * @rbm_id: Return Buffer Manager ID
283  * @desc_id: Descriptor ID
284  * @type: 0 - Address points to a MSDU buffer
285  *        1 - Address points to MSDU extension descriptor
286  *
287  * Return: void
288  */
289 static inline void
hal_tx_desc_set_buf_addr_generic_li(void * desc,dma_addr_t paddr,uint8_t rbm_id,uint32_t desc_id,uint8_t type)290 hal_tx_desc_set_buf_addr_generic_li(void *desc, dma_addr_t paddr,
291 				    uint8_t rbm_id, uint32_t desc_id,
292 				    uint8_t type)
293 {
294 	/* Set buffer_addr_info.buffer_addr_31_0 */
295 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
296 		    BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
297 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
298 
299 	/* Set buffer_addr_info.buffer_addr_39_32 */
300 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
301 			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
302 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
303 		       (((uint64_t)paddr) >> 32));
304 
305 	/* Set buffer_addr_info.return_buffer_manager = rbm id */
306 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
307 			 BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
308 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
309 		       RETURN_BUFFER_MANAGER, rbm_id);
310 
311 	/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
312 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
313 		    BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
314 		HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
315 			  desc_id);
316 
317 	/* Set  Buffer or Ext Descriptor Type */
318 	HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
319 		    BUF_OR_EXT_DESC_TYPE) |=
320 		HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
321 }
322 
323 #if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
324 /**
325  * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
326  * @tlv_tag: Tag of the TLVs
327  * @rx_tlv: the pointer to the TLVs
328  * @ppdu_info: pointer to ppdu_info
329  *
330  * Return: true if the tlv is handled, false if not
331  */
332 static inline bool
hal_rx_handle_other_tlvs(uint32_t tlv_tag,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)333 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
334 			 struct hal_rx_ppdu_info *ppdu_info)
335 {
336 	uint32_t value;
337 
338 	switch (tlv_tag) {
339 	case WIFIPHYRX_HE_SIG_A_MU_UL_E:
340 	{
341 		uint8_t *he_sig_a_mu_ul_info =
342 			(uint8_t *)rx_tlv +
343 			HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0,
344 					  HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS);
345 		ppdu_info->rx_status.he_flags = 1;
346 
347 		value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
348 				   FORMAT_INDICATION);
349 		if (value == 0) {
350 			ppdu_info->rx_status.he_data1 =
351 				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
352 		} else {
353 			ppdu_info->rx_status.he_data1 =
354 				QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
355 		}
356 
357 		/* data1 */
358 		ppdu_info->rx_status.he_data1 |=
359 			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
360 			QDF_MON_STATUS_HE_DL_UL_KNOWN |
361 			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN;
362 
363 		/* data2 */
364 		ppdu_info->rx_status.he_data2 |=
365 			QDF_MON_STATUS_TXOP_KNOWN;
366 
367 		/*data3*/
368 		value = HAL_RX_GET(he_sig_a_mu_ul_info,
369 				   HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID);
370 		ppdu_info->rx_status.he_data3 = value;
371 		/* 1 for UL and 0 for DL */
372 		value = 1;
373 		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
374 		ppdu_info->rx_status.he_data3 |= value;
375 
376 		/*data4*/
377 		value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0,
378 				   SPATIAL_REUSE);
379 		ppdu_info->rx_status.he_data4 = value;
380 
381 		/*data5*/
382 		value = HAL_RX_GET(he_sig_a_mu_ul_info,
383 				   HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW);
384 		ppdu_info->rx_status.he_data5 = value;
385 		ppdu_info->rx_status.bw = value;
386 
387 		/*data6*/
388 		value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1,
389 				   TXOP_DURATION);
390 		value = value << QDF_MON_STATUS_TXOP_SHIFT;
391 		ppdu_info->rx_status.he_data6 |= value;
392 		return true;
393 	}
394 	default:
395 		return false;
396 	}
397 }
398 #else
399 static inline bool
hal_rx_handle_other_tlvs(uint32_t tlv_tag,void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)400 hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv,
401 			 struct hal_rx_ppdu_info *ppdu_info)
402 {
403 	return false;
404 }
405 #endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */
406 
407 #if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \
408 defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET)
409 
410 static inline void
hal_rx_handle_mu_ul_info(void * rx_tlv,struct mon_rx_user_status * mon_rx_user_status)411 hal_rx_handle_mu_ul_info(void *rx_tlv,
412 			 struct mon_rx_user_status *mon_rx_user_status)
413 {
414 	mon_rx_user_status->mu_ul_user_v0_word0 =
415 		HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11,
416 			   SW_RESPONSE_REFERENCE_PTR);
417 
418 	mon_rx_user_status->mu_ul_user_v0_word1 =
419 		HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22,
420 			   SW_RESPONSE_REFERENCE_PTR_EXT);
421 }
422 
423 static inline void
hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct mon_rx_user_status * mon_rx_user_status)424 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
425 			   struct mon_rx_user_status *mon_rx_user_status)
426 {
427 	uint32_t mpdu_ok_byte_count;
428 	uint32_t mpdu_err_byte_count;
429 
430 	mpdu_ok_byte_count = HAL_RX_GET(rx_tlv,
431 					RX_PPDU_END_USER_STATS_17,
432 					MPDU_OK_BYTE_COUNT);
433 	mpdu_err_byte_count = HAL_RX_GET(rx_tlv,
434 					 RX_PPDU_END_USER_STATS_19,
435 					 MPDU_ERR_BYTE_COUNT);
436 
437 	mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count;
438 	mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count;
439 }
440 #else
441 static inline void
hal_rx_handle_mu_ul_info(void * rx_tlv,struct mon_rx_user_status * mon_rx_user_status)442 hal_rx_handle_mu_ul_info(void *rx_tlv,
443 			 struct mon_rx_user_status *mon_rx_user_status)
444 {
445 }
446 
447 static inline void
hal_rx_populate_byte_count(void * rx_tlv,void * ppduinfo,struct mon_rx_user_status * mon_rx_user_status)448 hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo,
449 			   struct mon_rx_user_status *mon_rx_user_status)
450 {
451 	struct hal_rx_ppdu_info *ppdu_info =
452 			(struct hal_rx_ppdu_info *)ppduinfo;
453 
454 	/* HKV1: doesn't support mpdu byte count */
455 	mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len;
456 	mon_rx_user_status->mpdu_err_byte_count = 0;
457 }
458 #endif
459 
460 static inline void
hal_rx_populate_mu_user_info(void * rx_tlv,void * ppduinfo,uint32_t user_id,struct mon_rx_user_status * mon_rx_user_status)461 hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id,
462 			     struct mon_rx_user_status *mon_rx_user_status)
463 {
464 	struct mon_rx_info *mon_rx_info;
465 	struct mon_rx_user_info *mon_rx_user_info;
466 	struct hal_rx_ppdu_info *ppdu_info =
467 			(struct hal_rx_ppdu_info *)ppduinfo;
468 
469 	mon_rx_info = &ppdu_info->rx_info;
470 	mon_rx_user_info = &ppdu_info->rx_user_info[user_id];
471 	mon_rx_user_info->qos_control_info_valid =
472 		mon_rx_info->qos_control_info_valid;
473 	mon_rx_user_info->qos_control =  mon_rx_info->qos_control;
474 
475 	mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index;
476 	mon_rx_user_status->tid = ppdu_info->rx_status.tid;
477 	mon_rx_user_status->tcp_msdu_count =
478 		ppdu_info->rx_status.tcp_msdu_count;
479 	mon_rx_user_status->udp_msdu_count =
480 		ppdu_info->rx_status.udp_msdu_count;
481 	mon_rx_user_status->other_msdu_count =
482 		ppdu_info->rx_status.other_msdu_count;
483 	mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control;
484 	mon_rx_user_status->frame_control_info_valid =
485 		ppdu_info->rx_status.frame_control_info_valid;
486 	mon_rx_user_status->data_sequence_control_info_valid =
487 		ppdu_info->rx_status.data_sequence_control_info_valid;
488 	mon_rx_user_status->first_data_seq_ctrl =
489 		ppdu_info->rx_status.first_data_seq_ctrl;
490 	mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type;
491 	mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags;
492 	mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags;
493 	mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags;
494 	mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags;
495 	mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags;
496 
497 	mon_rx_user_status->mpdu_cnt_fcs_ok =
498 		ppdu_info->com_info.mpdu_cnt_fcs_ok;
499 	mon_rx_user_status->mpdu_cnt_fcs_err =
500 		ppdu_info->com_info.mpdu_cnt_fcs_err;
501 	qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap,
502 		     &ppdu_info->com_info.mpdu_fcs_ok_bitmap,
503 		     HAL_RX_NUM_WORDS_PER_PPDU_BITMAP *
504 		     sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0]));
505 
506 	hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status);
507 }
508 
509 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \
510 					ppdu_info, rssi_info_tlv) \
511 	{						\
512 	ppdu_info->rx_status.rssi_chain[chain][0] = \
513 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
514 				   RSSI_PRI20_CHAIN##chain); \
515 	ppdu_info->rx_status.rssi_chain[chain][1] = \
516 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
517 				   RSSI_EXT20_CHAIN##chain); \
518 	ppdu_info->rx_status.rssi_chain[chain][2] = \
519 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
520 				   RSSI_EXT40_LOW20_CHAIN##chain); \
521 	ppdu_info->rx_status.rssi_chain[chain][3] = \
522 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\
523 				   RSSI_EXT40_HIGH20_CHAIN##chain); \
524 	ppdu_info->rx_status.rssi_chain[chain][4] = \
525 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
526 				   RSSI_EXT80_LOW20_CHAIN##chain); \
527 	ppdu_info->rx_status.rssi_chain[chain][5] = \
528 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
529 				   RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \
530 	ppdu_info->rx_status.rssi_chain[chain][6] = \
531 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
532 				   RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \
533 	ppdu_info->rx_status.rssi_chain[chain][7] = \
534 			HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\
535 				   RSSI_EXT80_HIGH20_CHAIN##chain); \
536 	}						\
537 
538 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \
539 	{HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \
540 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \
541 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \
542 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \
543 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \
544 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \
545 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \
546 	HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \
547 
548 static inline uint32_t
hal_rx_update_rssi_chain(struct hal_rx_ppdu_info * ppdu_info,uint8_t * rssi_info_tlv)549 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info,
550 			 uint8_t *rssi_info_tlv)
551 {
552 	HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv)
553 	return 0;
554 }
555 
556 #ifdef WLAN_TX_PKT_CAPTURE_ENH
557 static inline void
hal_get_qos_control(void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)558 hal_get_qos_control(void *rx_tlv,
559 		    struct hal_rx_ppdu_info *ppdu_info)
560 {
561 	ppdu_info->rx_info.qos_control_info_valid =
562 		HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
563 			   QOS_CONTROL_INFO_VALID);
564 
565 	if (ppdu_info->rx_info.qos_control_info_valid)
566 		ppdu_info->rx_info.qos_control =
567 			HAL_RX_GET(rx_tlv,
568 				   RX_PPDU_END_USER_STATS_5,
569 				   QOS_CONTROL_FIELD);
570 }
571 
572 static inline void
hal_get_mac_addr1(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)573 hal_get_mac_addr1(uint8_t *rx_mpdu_start,
574 		  struct hal_rx_ppdu_info *ppdu_info)
575 {
576 	if ((ppdu_info->sw_frame_group_id
577 	     == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) ||
578 	    (ppdu_info->sw_frame_group_id ==
579 	     HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) {
580 		ppdu_info->rx_info.mac_addr1_valid =
581 				HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start);
582 
583 		*(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] =
584 			HAL_RX_GET(rx_mpdu_start,
585 				   RX_MPDU_INFO_15,
586 				   MAC_ADDR_AD1_31_0);
587 		if (ppdu_info->sw_frame_group_id ==
588 		    HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) {
589 			*(uint16_t *)&ppdu_info->rx_info.mac_addr1[4] =
590 				HAL_RX_GET(rx_mpdu_start,
591 					   RX_MPDU_INFO_16,
592 					   MAC_ADDR_AD1_47_32);
593 		}
594 	}
595 }
596 #else
597 static inline void
hal_get_qos_control(void * rx_tlv,struct hal_rx_ppdu_info * ppdu_info)598 hal_get_qos_control(void *rx_tlv,
599 		    struct hal_rx_ppdu_info *ppdu_info)
600 {
601 }
602 
603 static inline void
hal_get_mac_addr1(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)604 hal_get_mac_addr1(uint8_t *rx_mpdu_start,
605 		  struct hal_rx_ppdu_info *ppdu_info)
606 {
607 }
608 #endif
609 
610 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS
611 static inline void
hal_update_frame_type_cnt(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)612 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
613 			  struct hal_rx_ppdu_info *ppdu_info)
614 {
615 	uint16_t frame_ctrl;
616 	uint8_t fc_type;
617 
618 	if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) {
619 		frame_ctrl = HAL_RX_GET(rx_mpdu_start,
620 					RX_MPDU_INFO_14,
621 					MPDU_FRAME_CONTROL_FIELD);
622 		fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl);
623 		if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT)
624 			ppdu_info->frm_type_info.rx_mgmt_cnt++;
625 		else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL)
626 			ppdu_info->frm_type_info.rx_ctrl_cnt++;
627 		else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA)
628 			ppdu_info->frm_type_info.rx_data_cnt++;
629 	}
630 }
631 #else
632 static inline void
hal_update_frame_type_cnt(uint8_t * rx_mpdu_start,struct hal_rx_ppdu_info * ppdu_info)633 hal_update_frame_type_cnt(uint8_t *rx_mpdu_start,
634 			  struct hal_rx_ppdu_info *ppdu_info)
635 {
636 }
637 #endif
638 
639 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS
640 static inline void
hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info * ppdu_info,uint32_t user_id)641 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info,
642 			       uint32_t user_id)
643 {
644 	uint16_t fc = ppdu_info->nac_info.frame_control;
645 
646 	if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) {
647 		if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) ==
648 		    QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN)
649 			ppdu_info->ctrl_frm_info[user_id].ndpa = 1;
650 		if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) ==
651 		    QDF_IEEE80211_FC0_SUBTYPE_BAR)
652 			ppdu_info->ctrl_frm_info[user_id].bar = 1;
653 	}
654 }
655 #else
656 static inline void
hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info * ppdu_info,uint32_t user_id)657 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info,
658 			       uint32_t user_id)
659 {
660 }
661 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */
662 
663 /**
664  * hal_rx_status_get_tlv_info_generic_li() - process receive info TLV
665  * @rx_tlv_hdr: pointer to TLV header
666  * @ppduinfo: pointer to ppdu_info
667  * @hal_soc_hdl: hal_soc handle
668  * @nbuf: pointer the pkt buffer.
669  *
670  * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
671  */
672 static inline uint32_t
hal_rx_status_get_tlv_info_generic_li(void * rx_tlv_hdr,void * ppduinfo,hal_soc_handle_t hal_soc_hdl,qdf_nbuf_t nbuf)673 hal_rx_status_get_tlv_info_generic_li(void *rx_tlv_hdr, void *ppduinfo,
674 				      hal_soc_handle_t hal_soc_hdl,
675 				      qdf_nbuf_t nbuf)
676 {
677 	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
678 	uint32_t tlv_tag, user_id, tlv_len, value;
679 	uint8_t group_id = 0;
680 	uint8_t he_dcm = 0;
681 	uint8_t he_stbc = 0;
682 	uint16_t he_gi = 0;
683 	uint16_t he_ltf = 0;
684 	void *rx_tlv;
685 	bool unhandled = false;
686 	struct mon_rx_user_status *mon_rx_user_status;
687 	struct hal_rx_ppdu_info *ppdu_info =
688 			(struct hal_rx_ppdu_info *)ppduinfo;
689 
690 	tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
691 	user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
692 	tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
693 
694 	rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
695 
696 	switch (tlv_tag) {
697 	case WIFIRX_PPDU_START_E:
698 	{
699 		if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id ==
700 		    HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID)))
701 			hal_err("Matching ppdu_id(%u) detected",
702 				 ppdu_info->com_info.last_ppdu_id);
703 
704 		/* Reset ppdu_info before processing the ppdu */
705 		qdf_mem_zero(ppdu_info,
706 			     sizeof(struct hal_rx_ppdu_info));
707 
708 		ppdu_info->com_info.last_ppdu_id =
709 			ppdu_info->com_info.ppdu_id =
710 				HAL_RX_GET(rx_tlv, RX_PPDU_START_0,
711 					PHY_PPDU_ID);
712 
713 		/* channel number is set in PHY meta data */
714 		ppdu_info->rx_status.chan_num =
715 			(HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
716 				SW_PHY_META_DATA) & 0x0000FFFF);
717 		ppdu_info->rx_status.chan_freq =
718 			(HAL_RX_GET(rx_tlv, RX_PPDU_START_1,
719 				SW_PHY_META_DATA) & 0xFFFF0000) >> 16;
720 		if (ppdu_info->rx_status.chan_num) {
721 			ppdu_info->rx_status.chan_freq =
722 				hal_rx_radiotap_num_to_freq(
723 				ppdu_info->rx_status.chan_num,
724 				 ppdu_info->rx_status.chan_freq);
725 		}
726 		ppdu_info->com_info.ppdu_timestamp =
727 			HAL_RX_GET(rx_tlv, RX_PPDU_START_2,
728 				PPDU_START_TIMESTAMP);
729 		ppdu_info->rx_status.ppdu_timestamp =
730 			ppdu_info->com_info.ppdu_timestamp;
731 		ppdu_info->rx_state = HAL_RX_MON_PPDU_START;
732 
733 		break;
734 	}
735 
736 	case WIFIRX_PPDU_START_USER_INFO_E:
737 		break;
738 
739 	case WIFIRX_PPDU_END_E:
740 		dp_nofl_debug("[%s][%d] ppdu_end_e len=%d",
741 			      __func__, __LINE__, tlv_len);
742 		/* This is followed by sub-TLVs of PPDU_END */
743 		ppdu_info->rx_state = HAL_RX_MON_PPDU_END;
744 		break;
745 
746 	case WIFIPHYRX_PKT_END_E:
747 		hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info);
748 		break;
749 
750 	case WIFIRXPCU_PPDU_END_INFO_E:
751 		ppdu_info->rx_status.rx_antenna =
752 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA);
753 		ppdu_info->rx_status.tsft =
754 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1,
755 				WB_TIMESTAMP_UPPER_32);
756 		ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) |
757 			HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0,
758 				WB_TIMESTAMP_LOWER_32);
759 		ppdu_info->rx_status.duration =
760 			HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8,
761 				RX_PPDU_DURATION);
762 		hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info);
763 		hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info);
764 		break;
765 
766 	/*
767 	 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received.
768 	 * for MU, based on num users we see this tlv that many times.
769 	 */
770 	case WIFIRX_PPDU_END_USER_STATS_E:
771 	{
772 		unsigned long tid = 0;
773 		uint16_t seq = 0;
774 
775 		ppdu_info->rx_status.ast_index =
776 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4,
777 						AST_INDEX);
778 
779 		tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12,
780 				RECEIVED_QOS_DATA_TID_BITMAP);
781 		ppdu_info->rx_status.tid = qdf_find_first_bit(&tid,
782 							      sizeof(tid) * 8);
783 
784 		if (ppdu_info->rx_status.tid == (sizeof(tid) * 8))
785 			ppdu_info->rx_status.tid = HAL_TID_INVALID;
786 
787 		ppdu_info->rx_status.tcp_msdu_count =
788 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
789 					TCP_MSDU_COUNT) +
790 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
791 					TCP_ACK_MSDU_COUNT);
792 		ppdu_info->rx_status.udp_msdu_count =
793 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9,
794 						UDP_MSDU_COUNT);
795 		ppdu_info->rx_status.other_msdu_count =
796 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10,
797 					OTHER_MSDU_COUNT);
798 
799 		if (ppdu_info->sw_frame_group_id
800 		    != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
801 			ppdu_info->rx_status.frame_control_info_valid =
802 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
803 					   FRAME_CONTROL_INFO_VALID);
804 
805 			if (ppdu_info->rx_status.frame_control_info_valid)
806 				ppdu_info->rx_status.frame_control =
807 					HAL_RX_GET(rx_tlv,
808 						   RX_PPDU_END_USER_STATS_4,
809 						   FRAME_CONTROL_FIELD);
810 
811 			hal_get_qos_control(rx_tlv, ppdu_info);
812 		}
813 
814 		ppdu_info->rx_status.data_sequence_control_info_valid =
815 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
816 				   DATA_SEQUENCE_CONTROL_INFO_VALID);
817 
818 		seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5,
819 				 FIRST_DATA_SEQ_CTRL);
820 		if (ppdu_info->rx_status.data_sequence_control_info_valid)
821 			ppdu_info->rx_status.first_data_seq_ctrl = seq;
822 
823 		ppdu_info->rx_status.preamble_type =
824 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
825 						HT_CONTROL_FIELD_PKT_TYPE);
826 		switch (ppdu_info->rx_status.preamble_type) {
827 		case HAL_RX_PKT_TYPE_11N:
828 			ppdu_info->rx_status.ht_flags = 1;
829 			ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT;
830 			break;
831 		case HAL_RX_PKT_TYPE_11AC:
832 			ppdu_info->rx_status.vht_flags = 1;
833 			break;
834 		case HAL_RX_PKT_TYPE_11AX:
835 			ppdu_info->rx_status.he_flags = 1;
836 			break;
837 		default:
838 			break;
839 		}
840 
841 		ppdu_info->com_info.mpdu_cnt_fcs_ok =
842 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3,
843 					MPDU_CNT_FCS_OK);
844 		ppdu_info->com_info.mpdu_cnt_fcs_err =
845 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2,
846 					MPDU_CNT_FCS_ERR);
847 		if ((ppdu_info->com_info.mpdu_cnt_fcs_ok |
848 			ppdu_info->com_info.mpdu_cnt_fcs_err) > 1)
849 			ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG;
850 		else
851 			ppdu_info->rx_status.rs_flags &=
852 				(~IEEE80211_AMPDU_FLAG);
853 
854 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] =
855 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7,
856 					   FCS_OK_BITMAP_31_0);
857 
858 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] =
859 				HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8,
860 					   FCS_OK_BITMAP_63_32);
861 
862 		if (user_id < HAL_MAX_UL_MU_USERS) {
863 			mon_rx_user_status =
864 				&ppdu_info->rx_user_status[user_id];
865 
866 			hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status);
867 
868 			ppdu_info->com_info.num_users++;
869 
870 			hal_rx_populate_mu_user_info(rx_tlv, ppdu_info,
871 						     user_id,
872 						     mon_rx_user_status);
873 		}
874 		break;
875 	}
876 
877 	case WIFIRX_PPDU_END_USER_STATS_EXT_E:
878 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] =
879 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1,
880 				   FCS_OK_BITMAP_95_64);
881 
882 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] =
883 			 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2,
884 				    FCS_OK_BITMAP_127_96);
885 
886 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] =
887 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3,
888 				   FCS_OK_BITMAP_159_128);
889 
890 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] =
891 			 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4,
892 				    FCS_OK_BITMAP_191_160);
893 
894 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] =
895 			HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5,
896 				   FCS_OK_BITMAP_223_192);
897 
898 		ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] =
899 			 HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6,
900 				    FCS_OK_BITMAP_255_224);
901 		break;
902 
903 	case WIFIRX_PPDU_END_STATUS_DONE_E:
904 		return HAL_TLV_STATUS_PPDU_DONE;
905 
906 	case WIFIDUMMY_E:
907 		return HAL_TLV_STATUS_BUF_DONE;
908 
909 	case WIFIPHYRX_HT_SIG_E:
910 	{
911 		uint8_t *ht_sig_info = (uint8_t *)rx_tlv +
912 				HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0,
913 				HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS);
914 		value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1,
915 				FEC_CODING);
916 		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
917 			1 : 0;
918 		ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info,
919 				HT_SIG_INFO_0, MCS);
920 		ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs;
921 		ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info,
922 				HT_SIG_INFO_0, CBW);
923 		ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info,
924 				HT_SIG_INFO_1, SHORT_GI);
925 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
926 		ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >>
927 				HT_SIG_SU_NSS_SHIFT) + 1;
928 		ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1);
929 		hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info);
930 		break;
931 	}
932 
933 	case WIFIPHYRX_L_SIG_B_E:
934 	{
935 		uint8_t *l_sig_b_info = (uint8_t *)rx_tlv +
936 				HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0,
937 				L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS);
938 
939 		value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE);
940 		ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info);
941 		switch (value) {
942 		case 1:
943 			ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS;
944 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
945 			break;
946 		case 2:
947 			ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS;
948 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
949 			break;
950 		case 3:
951 			ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS;
952 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
953 			break;
954 		case 4:
955 			ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS;
956 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
957 			break;
958 		case 5:
959 			ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS;
960 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
961 			break;
962 		case 6:
963 			ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS;
964 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
965 			break;
966 		case 7:
967 			ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS;
968 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
969 			break;
970 		default:
971 			break;
972 		}
973 		ppdu_info->rx_status.cck_flag = 1;
974 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
975 	break;
976 	}
977 
978 	case WIFIPHYRX_L_SIG_A_E:
979 	{
980 		uint8_t *l_sig_a_info = (uint8_t *)rx_tlv +
981 				HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0,
982 				L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS);
983 
984 		value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE);
985 		ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info);
986 		switch (value) {
987 		case 8:
988 			ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS;
989 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0;
990 			break;
991 		case 9:
992 			ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS;
993 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1;
994 			break;
995 		case 10:
996 			ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS;
997 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2;
998 			break;
999 		case 11:
1000 			ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS;
1001 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3;
1002 			break;
1003 		case 12:
1004 			ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS;
1005 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4;
1006 			break;
1007 		case 13:
1008 			ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS;
1009 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5;
1010 			break;
1011 		case 14:
1012 			ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS;
1013 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6;
1014 			break;
1015 		case 15:
1016 			ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS;
1017 			ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7;
1018 			break;
1019 		default:
1020 			break;
1021 		}
1022 		ppdu_info->rx_status.ofdm_flag = 1;
1023 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
1024 		hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info);
1025 	break;
1026 	}
1027 
1028 	case WIFIPHYRX_VHT_SIG_A_E:
1029 	{
1030 		uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv +
1031 				HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0,
1032 				VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS);
1033 
1034 		value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1,
1035 				SU_MU_CODING);
1036 		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
1037 			1 : 0;
1038 		group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0,
1039 				      GROUP_ID);
1040 		ppdu_info->rx_status.vht_flag_values5 = group_id;
1041 		ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info,
1042 				VHT_SIG_A_INFO_1, MCS);
1043 		ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info,
1044 				VHT_SIG_A_INFO_1, GI_SETTING);
1045 
1046 		switch (hal->target_type) {
1047 		case TARGET_TYPE_QCA8074:
1048 		case TARGET_TYPE_QCA8074V2:
1049 		case TARGET_TYPE_QCA6018:
1050 		case TARGET_TYPE_QCA5018:
1051 		case TARGET_TYPE_QCN9000:
1052 		case TARGET_TYPE_QCN6122:
1053 		case TARGET_TYPE_QCN9160:
1054 #ifdef QCA_WIFI_QCA6390
1055 		case TARGET_TYPE_QCA6390:
1056 #endif
1057 		case TARGET_TYPE_QCA6490:
1058 			ppdu_info->rx_status.is_stbc =
1059 				HAL_RX_GET(vht_sig_a_info,
1060 					   VHT_SIG_A_INFO_0, STBC);
1061 			value =  HAL_RX_GET(vht_sig_a_info,
1062 					    VHT_SIG_A_INFO_0, N_STS);
1063 			value = value & VHT_SIG_SU_NSS_MASK;
1064 			if (ppdu_info->rx_status.is_stbc && (value > 0))
1065 				value = ((value + 1) >> 1) - 1;
1066 			ppdu_info->rx_status.nss =
1067 				((value & VHT_SIG_SU_NSS_MASK) + 1);
1068 
1069 			break;
1070 		case TARGET_TYPE_QCA6290:
1071 #if !defined(QCA_WIFI_QCA6290_11AX)
1072 			ppdu_info->rx_status.is_stbc =
1073 				HAL_RX_GET(vht_sig_a_info,
1074 					   VHT_SIG_A_INFO_0, STBC);
1075 			value =  HAL_RX_GET(vht_sig_a_info,
1076 					    VHT_SIG_A_INFO_0, N_STS);
1077 			value = value & VHT_SIG_SU_NSS_MASK;
1078 			if (ppdu_info->rx_status.is_stbc && (value > 0))
1079 				value = ((value + 1) >> 1) - 1;
1080 			ppdu_info->rx_status.nss =
1081 				((value & VHT_SIG_SU_NSS_MASK) + 1);
1082 #else
1083 			ppdu_info->rx_status.nss = 0;
1084 #endif
1085 			break;
1086 		case TARGET_TYPE_QCA6750:
1087 			ppdu_info->rx_status.nss = 0;
1088 			break;
1089 		default:
1090 			break;
1091 		}
1092 		ppdu_info->rx_status.vht_flag_values3[0] =
1093 				(((ppdu_info->rx_status.mcs) << 4)
1094 				| ppdu_info->rx_status.nss);
1095 		ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info,
1096 				VHT_SIG_A_INFO_0, BANDWIDTH);
1097 		ppdu_info->rx_status.vht_flag_values2 =
1098 			ppdu_info->rx_status.bw;
1099 		ppdu_info->rx_status.vht_flag_values4 =
1100 			HAL_RX_GET(vht_sig_a_info,
1101 				  VHT_SIG_A_INFO_1, SU_MU_CODING);
1102 
1103 		ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info,
1104 				VHT_SIG_A_INFO_1, BEAMFORMED);
1105 		if (group_id == 0 || group_id == 63)
1106 			ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
1107 		else
1108 			ppdu_info->rx_status.reception_type =
1109 				HAL_RX_TYPE_MU_MIMO;
1110 
1111 		hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info);
1112 		break;
1113 	}
1114 	case WIFIPHYRX_HE_SIG_A_SU_E:
1115 	{
1116 		uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv +
1117 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0,
1118 			HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS);
1119 		ppdu_info->rx_status.he_flags = 1;
1120 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
1121 			FORMAT_INDICATION);
1122 		if (value == 0) {
1123 			ppdu_info->rx_status.he_data1 =
1124 				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
1125 		} else {
1126 			ppdu_info->rx_status.he_data1 =
1127 				 QDF_MON_STATUS_HE_SU_FORMAT_TYPE;
1128 		}
1129 
1130 		/* data1 */
1131 		ppdu_info->rx_status.he_data1 |=
1132 			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
1133 			QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN |
1134 			QDF_MON_STATUS_HE_DL_UL_KNOWN |
1135 			QDF_MON_STATUS_HE_MCS_KNOWN |
1136 			QDF_MON_STATUS_HE_DCM_KNOWN |
1137 			QDF_MON_STATUS_HE_CODING_KNOWN |
1138 			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
1139 			QDF_MON_STATUS_HE_STBC_KNOWN |
1140 			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
1141 			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
1142 
1143 		/* data2 */
1144 		ppdu_info->rx_status.he_data2 =
1145 			QDF_MON_STATUS_HE_GI_KNOWN;
1146 		ppdu_info->rx_status.he_data2 |=
1147 			QDF_MON_STATUS_TXBF_KNOWN |
1148 			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
1149 			QDF_MON_STATUS_TXOP_KNOWN |
1150 			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
1151 			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
1152 			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
1153 
1154 		/* data3 */
1155 		value = HAL_RX_GET(he_sig_a_su_info,
1156 				HE_SIG_A_SU_INFO_0, BSS_COLOR_ID);
1157 		ppdu_info->rx_status.he_data3 = value;
1158 		value = HAL_RX_GET(he_sig_a_su_info,
1159 				HE_SIG_A_SU_INFO_0, BEAM_CHANGE);
1160 		value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT;
1161 		ppdu_info->rx_status.he_data3 |= value;
1162 		value = HAL_RX_GET(he_sig_a_su_info,
1163 				HE_SIG_A_SU_INFO_0, DL_UL_FLAG);
1164 		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
1165 		ppdu_info->rx_status.he_data3 |= value;
1166 
1167 		value = HAL_RX_GET(he_sig_a_su_info,
1168 				HE_SIG_A_SU_INFO_0, TRANSMIT_MCS);
1169 		ppdu_info->rx_status.mcs = value;
1170 		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
1171 		ppdu_info->rx_status.he_data3 |= value;
1172 
1173 		value = HAL_RX_GET(he_sig_a_su_info,
1174 				HE_SIG_A_SU_INFO_0, DCM);
1175 		he_dcm = value;
1176 		value = value << QDF_MON_STATUS_DCM_SHIFT;
1177 		ppdu_info->rx_status.he_data3 |= value;
1178 		value = HAL_RX_GET(he_sig_a_su_info,
1179 				HE_SIG_A_SU_INFO_1, CODING);
1180 		ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ?
1181 			1 : 0;
1182 		value = value << QDF_MON_STATUS_CODING_SHIFT;
1183 		ppdu_info->rx_status.he_data3 |= value;
1184 		value = HAL_RX_GET(he_sig_a_su_info,
1185 				HE_SIG_A_SU_INFO_1,
1186 				LDPC_EXTRA_SYMBOL);
1187 		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
1188 		ppdu_info->rx_status.he_data3 |= value;
1189 		value = HAL_RX_GET(he_sig_a_su_info,
1190 				HE_SIG_A_SU_INFO_1, STBC);
1191 		he_stbc = value;
1192 		value = value << QDF_MON_STATUS_STBC_SHIFT;
1193 		ppdu_info->rx_status.he_data3 |= value;
1194 
1195 		/* data4 */
1196 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0,
1197 							SPATIAL_REUSE);
1198 		ppdu_info->rx_status.he_data4 = value;
1199 
1200 		/* data5 */
1201 		value = HAL_RX_GET(he_sig_a_su_info,
1202 				HE_SIG_A_SU_INFO_0, TRANSMIT_BW);
1203 		ppdu_info->rx_status.he_data5 = value;
1204 		ppdu_info->rx_status.bw = value;
1205 		value = HAL_RX_GET(he_sig_a_su_info,
1206 				HE_SIG_A_SU_INFO_0, CP_LTF_SIZE);
1207 		switch (value) {
1208 		case 0:
1209 				he_gi = HE_GI_0_8;
1210 				he_ltf = HE_LTF_1_X;
1211 				break;
1212 		case 1:
1213 				he_gi = HE_GI_0_8;
1214 				he_ltf = HE_LTF_2_X;
1215 				break;
1216 		case 2:
1217 				he_gi = HE_GI_1_6;
1218 				he_ltf = HE_LTF_2_X;
1219 				break;
1220 		case 3:
1221 				if (he_dcm && he_stbc) {
1222 					he_gi = HE_GI_0_8;
1223 					he_ltf = HE_LTF_4_X;
1224 				} else {
1225 					he_gi = HE_GI_3_2;
1226 					he_ltf = HE_LTF_4_X;
1227 				}
1228 				break;
1229 		}
1230 		ppdu_info->rx_status.sgi = he_gi;
1231 		ppdu_info->rx_status.ltf_size = he_ltf;
1232 		hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
1233 		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
1234 		ppdu_info->rx_status.he_data5 |= value;
1235 		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
1236 		ppdu_info->rx_status.he_data5 |= value;
1237 
1238 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
1239 		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
1240 		ppdu_info->rx_status.he_data5 |= value;
1241 
1242 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1243 						PACKET_EXTENSION_A_FACTOR);
1244 		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
1245 		ppdu_info->rx_status.he_data5 |= value;
1246 
1247 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF);
1248 		value = value << QDF_MON_STATUS_TXBF_SHIFT;
1249 		ppdu_info->rx_status.he_data5 |= value;
1250 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1251 					PACKET_EXTENSION_PE_DISAMBIGUITY);
1252 		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
1253 		ppdu_info->rx_status.he_data5 |= value;
1254 
1255 		/* data6 */
1256 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS);
1257 		value++;
1258 		ppdu_info->rx_status.nss = value;
1259 		ppdu_info->rx_status.he_data6 = value;
1260 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1261 							DOPPLER_INDICATION);
1262 		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
1263 		ppdu_info->rx_status.he_data6 |= value;
1264 		value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1,
1265 							TXOP_DURATION);
1266 		value = value << QDF_MON_STATUS_TXOP_SHIFT;
1267 		ppdu_info->rx_status.he_data6 |= value;
1268 
1269 		ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info,
1270 					HE_SIG_A_SU_INFO_1, TXBF);
1271 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU;
1272 		hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info);
1273 		break;
1274 	}
1275 	case WIFIPHYRX_HE_SIG_A_MU_DL_E:
1276 	{
1277 		uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv +
1278 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0,
1279 			HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS);
1280 
1281 		ppdu_info->rx_status.he_mu_flags = 1;
1282 
1283 		/* HE Flags */
1284 		/*data1*/
1285 		ppdu_info->rx_status.he_data1 =
1286 					QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
1287 		ppdu_info->rx_status.he_data1 |=
1288 			QDF_MON_STATUS_HE_BSS_COLOR_KNOWN |
1289 			QDF_MON_STATUS_HE_DL_UL_KNOWN |
1290 			QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN |
1291 			QDF_MON_STATUS_HE_STBC_KNOWN |
1292 			QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN |
1293 			QDF_MON_STATUS_HE_DOPPLER_KNOWN;
1294 
1295 		/* data2 */
1296 		ppdu_info->rx_status.he_data2 =
1297 			QDF_MON_STATUS_HE_GI_KNOWN;
1298 		ppdu_info->rx_status.he_data2 |=
1299 			QDF_MON_STATUS_LTF_SYMBOLS_KNOWN |
1300 			QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN |
1301 			QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN |
1302 			QDF_MON_STATUS_TXOP_KNOWN |
1303 			QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN;
1304 
1305 		/*data3*/
1306 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1307 				HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID);
1308 		ppdu_info->rx_status.he_data3 = value;
1309 
1310 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1311 				HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG);
1312 		value = value << QDF_MON_STATUS_DL_UL_SHIFT;
1313 		ppdu_info->rx_status.he_data3 |= value;
1314 
1315 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1316 				HE_SIG_A_MU_DL_INFO_1,
1317 				LDPC_EXTRA_SYMBOL);
1318 		value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT;
1319 		ppdu_info->rx_status.he_data3 |= value;
1320 
1321 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1322 				HE_SIG_A_MU_DL_INFO_1, STBC);
1323 		he_stbc = value;
1324 		value = value << QDF_MON_STATUS_STBC_SHIFT;
1325 		ppdu_info->rx_status.he_data3 |= value;
1326 
1327 		/*data4*/
1328 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
1329 							SPATIAL_REUSE);
1330 		ppdu_info->rx_status.he_data4 = value;
1331 
1332 		/*data5*/
1333 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1334 				HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
1335 		ppdu_info->rx_status.he_data5 = value;
1336 		ppdu_info->rx_status.bw = value;
1337 
1338 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1339 				HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE);
1340 		switch (value) {
1341 		case 0:
1342 			he_gi = HE_GI_0_8;
1343 			he_ltf = HE_LTF_4_X;
1344 			break;
1345 		case 1:
1346 			he_gi = HE_GI_0_8;
1347 			he_ltf = HE_LTF_2_X;
1348 			break;
1349 		case 2:
1350 			he_gi = HE_GI_1_6;
1351 			he_ltf = HE_LTF_2_X;
1352 			break;
1353 		case 3:
1354 			he_gi = HE_GI_3_2;
1355 			he_ltf = HE_LTF_4_X;
1356 			break;
1357 		}
1358 		ppdu_info->rx_status.sgi = he_gi;
1359 		ppdu_info->rx_status.ltf_size = he_ltf;
1360 		hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf);
1361 		value = he_gi << QDF_MON_STATUS_GI_SHIFT;
1362 		ppdu_info->rx_status.he_data5 |= value;
1363 
1364 		value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT;
1365 		ppdu_info->rx_status.he_data5 |= value;
1366 
1367 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1368 				   HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS);
1369 		value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT);
1370 		ppdu_info->rx_status.he_data5 |= value;
1371 
1372 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
1373 				   PACKET_EXTENSION_A_FACTOR);
1374 		value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT;
1375 		ppdu_info->rx_status.he_data5 |= value;
1376 
1377 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
1378 				   PACKET_EXTENSION_PE_DISAMBIGUITY);
1379 		value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT;
1380 		ppdu_info->rx_status.he_data5 |= value;
1381 
1382 		/*data6*/
1383 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0,
1384 							DOPPLER_INDICATION);
1385 		value = value << QDF_MON_STATUS_DOPPLER_SHIFT;
1386 		ppdu_info->rx_status.he_data6 |= value;
1387 
1388 		value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1,
1389 							TXOP_DURATION);
1390 		value = value << QDF_MON_STATUS_TXOP_SHIFT;
1391 		ppdu_info->rx_status.he_data6 |= value;
1392 
1393 		/* HE-MU Flags */
1394 		/* HE-MU-flags1 */
1395 		ppdu_info->rx_status.he_flags1 =
1396 			QDF_MON_STATUS_SIG_B_MCS_KNOWN |
1397 			QDF_MON_STATUS_SIG_B_DCM_KNOWN |
1398 			QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN |
1399 			QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN |
1400 			QDF_MON_STATUS_RU_0_KNOWN;
1401 
1402 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1403 				HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B);
1404 		ppdu_info->rx_status.he_flags1 |= value;
1405 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1406 				HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B);
1407 		value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT;
1408 		ppdu_info->rx_status.he_flags1 |= value;
1409 
1410 		/* HE-MU-flags2 */
1411 		ppdu_info->rx_status.he_flags2 =
1412 			QDF_MON_STATUS_BW_KNOWN;
1413 
1414 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1415 				HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW);
1416 		ppdu_info->rx_status.he_flags2 |= value;
1417 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1418 				HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B);
1419 		value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT;
1420 		ppdu_info->rx_status.he_flags2 |= value;
1421 		value = HAL_RX_GET(he_sig_a_mu_dl_info,
1422 				HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS);
1423 		value = value - 1;
1424 		value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT;
1425 		ppdu_info->rx_status.he_flags2 |= value;
1426 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
1427 		hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info,
1428 						   he_sig_a_mu_dl_info);
1429 		break;
1430 	}
1431 	case WIFIPHYRX_HE_SIG_B1_MU_E:
1432 	{
1433 		uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv +
1434 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0,
1435 			HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS);
1436 
1437 		ppdu_info->rx_status.he_sig_b_common_known |=
1438 			QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
1439 		/* TODO: Check on the availability of other fields in
1440 		 * sig_b_common
1441 		 */
1442 
1443 		value = HAL_RX_GET(he_sig_b1_mu_info,
1444 				HE_SIG_B1_MU_INFO_0, RU_ALLOCATION);
1445 		ppdu_info->rx_status.he_RU[0] = value;
1446 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO;
1447 		break;
1448 	}
1449 	case WIFIPHYRX_HE_SIG_B2_MU_E:
1450 	{
1451 		uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv +
1452 			HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0,
1453 			HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS);
1454 		/*
1455 		 * Not all "HE" fields can be updated from
1456 		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
1457 		 * to populate rest of the "HE" fields for MU scenarios.
1458 		 */
1459 
1460 		/* HE-data1 */
1461 		ppdu_info->rx_status.he_data1 |=
1462 			QDF_MON_STATUS_HE_MCS_KNOWN |
1463 			QDF_MON_STATUS_HE_CODING_KNOWN;
1464 
1465 		/* HE-data2 */
1466 
1467 		/* HE-data3 */
1468 		value = HAL_RX_GET(he_sig_b2_mu_info,
1469 				HE_SIG_B2_MU_INFO_0, STA_MCS);
1470 		ppdu_info->rx_status.mcs = value;
1471 		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
1472 		ppdu_info->rx_status.he_data3 |= value;
1473 
1474 		value = HAL_RX_GET(he_sig_b2_mu_info,
1475 				HE_SIG_B2_MU_INFO_0, STA_CODING);
1476 		value = value << QDF_MON_STATUS_CODING_SHIFT;
1477 		ppdu_info->rx_status.he_data3 |= value;
1478 
1479 		/* HE-data4 */
1480 		value = HAL_RX_GET(he_sig_b2_mu_info,
1481 				HE_SIG_B2_MU_INFO_0, STA_ID);
1482 		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
1483 		ppdu_info->rx_status.he_data4 |= value;
1484 
1485 		/* HE-data5 */
1486 
1487 		/* HE-data6 */
1488 		value = HAL_RX_GET(he_sig_b2_mu_info,
1489 				   HE_SIG_B2_MU_INFO_0, NSTS);
1490 		/* value n indicates n+1 spatial streams */
1491 		value++;
1492 		ppdu_info->rx_status.nss = value;
1493 		ppdu_info->rx_status.he_data6 |= value;
1494 
1495 		break;
1496 	}
1497 	case WIFIPHYRX_HE_SIG_B2_OFDMA_E:
1498 	{
1499 		uint8_t *he_sig_b2_ofdma_info =
1500 		(uint8_t *)rx_tlv +
1501 		HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0,
1502 		HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS);
1503 
1504 		/*
1505 		 * Not all "HE" fields can be updated from
1506 		 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E
1507 		 * to populate rest of "HE" fields for MU OFDMA scenarios.
1508 		 */
1509 
1510 		/* HE-data1 */
1511 		ppdu_info->rx_status.he_data1 |=
1512 			QDF_MON_STATUS_HE_MCS_KNOWN |
1513 			QDF_MON_STATUS_HE_DCM_KNOWN |
1514 			QDF_MON_STATUS_HE_CODING_KNOWN;
1515 
1516 		/* HE-data2 */
1517 		ppdu_info->rx_status.he_data2 |=
1518 					QDF_MON_STATUS_TXBF_KNOWN;
1519 
1520 		/* HE-data3 */
1521 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1522 				HE_SIG_B2_OFDMA_INFO_0, STA_MCS);
1523 		ppdu_info->rx_status.mcs = value;
1524 		value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT;
1525 		ppdu_info->rx_status.he_data3 |= value;
1526 
1527 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1528 				HE_SIG_B2_OFDMA_INFO_0, STA_DCM);
1529 		he_dcm = value;
1530 		value = value << QDF_MON_STATUS_DCM_SHIFT;
1531 		ppdu_info->rx_status.he_data3 |= value;
1532 
1533 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1534 				HE_SIG_B2_OFDMA_INFO_0, STA_CODING);
1535 		value = value << QDF_MON_STATUS_CODING_SHIFT;
1536 		ppdu_info->rx_status.he_data3 |= value;
1537 
1538 		/* HE-data4 */
1539 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1540 				HE_SIG_B2_OFDMA_INFO_0, STA_ID);
1541 		value = value << QDF_MON_STATUS_STA_ID_SHIFT;
1542 		ppdu_info->rx_status.he_data4 |= value;
1543 
1544 		/* HE-data5 */
1545 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1546 				   HE_SIG_B2_OFDMA_INFO_0, TXBF);
1547 		value = value << QDF_MON_STATUS_TXBF_SHIFT;
1548 		ppdu_info->rx_status.he_data5 |= value;
1549 
1550 		/* HE-data6 */
1551 		value = HAL_RX_GET(he_sig_b2_ofdma_info,
1552 				   HE_SIG_B2_OFDMA_INFO_0, NSTS);
1553 		/* value n indicates n+1 spatial streams */
1554 		value++;
1555 		ppdu_info->rx_status.nss = value;
1556 		ppdu_info->rx_status.he_data6 |= value;
1557 		ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA;
1558 		break;
1559 	}
1560 	case WIFIPHYRX_RSSI_LEGACY_E:
1561 	{
1562 		uint8_t reception_type;
1563 		int8_t rssi_value;
1564 		uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv +
1565 			HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19,
1566 				RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS);
1567 
1568 		ppdu_info->rx_status.rssi_comb =
1569 				hal_rx_phy_legacy_get_rssi(hal_soc_hdl, rx_tlv);
1570 		ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv);
1571 		ppdu_info->rx_status.he_re = 0;
1572 
1573 		reception_type = HAL_RX_GET(rx_tlv,
1574 					    PHYRX_RSSI_LEGACY_0,
1575 					    RECEPTION_TYPE);
1576 		switch (reception_type) {
1577 		case QDF_RECEPTION_TYPE_ULOFMDA:
1578 			ppdu_info->rx_status.reception_type =
1579 				HAL_RX_TYPE_MU_OFDMA;
1580 			ppdu_info->rx_status.ulofdma_flag = 1;
1581 			ppdu_info->rx_status.he_data1 =
1582 				QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE;
1583 			break;
1584 		case QDF_RECEPTION_TYPE_ULMIMO:
1585 			ppdu_info->rx_status.reception_type =
1586 				HAL_RX_TYPE_MU_MIMO;
1587 			ppdu_info->rx_status.he_data1 =
1588 				QDF_MON_STATUS_HE_MU_FORMAT_TYPE;
1589 			break;
1590 		default:
1591 			ppdu_info->rx_status.reception_type =
1592 				HAL_RX_TYPE_SU;
1593 			break;
1594 		}
1595 		hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv);
1596 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1597 					RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0);
1598 		ppdu_info->rx_status.rssi[0] = rssi_value;
1599 		dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value);
1600 
1601 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1602 					RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1);
1603 		ppdu_info->rx_status.rssi[1] = rssi_value;
1604 		dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value);
1605 
1606 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1607 					RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2);
1608 		ppdu_info->rx_status.rssi[2] = rssi_value;
1609 		dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value);
1610 
1611 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1612 					RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3);
1613 		ppdu_info->rx_status.rssi[3] = rssi_value;
1614 		dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value);
1615 
1616 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1617 					RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4);
1618 		ppdu_info->rx_status.rssi[4] = rssi_value;
1619 		dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value);
1620 
1621 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1622 					RECEIVE_RSSI_INFO_10,
1623 					RSSI_PRI20_CHAIN5);
1624 		ppdu_info->rx_status.rssi[5] = rssi_value;
1625 		dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value);
1626 
1627 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1628 					RECEIVE_RSSI_INFO_12,
1629 					RSSI_PRI20_CHAIN6);
1630 		ppdu_info->rx_status.rssi[6] = rssi_value;
1631 		dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value);
1632 
1633 		rssi_value = HAL_RX_GET(rssi_info_tlv,
1634 					RECEIVE_RSSI_INFO_14,
1635 					RSSI_PRI20_CHAIN7);
1636 		ppdu_info->rx_status.rssi[7] = rssi_value;
1637 		dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value);
1638 		break;
1639 	}
1640 	case WIFIPHYRX_OTHER_RECEIVE_INFO_E:
1641 		hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr,
1642 								ppdu_info);
1643 		break;
1644 	case WIFIRX_HEADER_E:
1645 	{
1646 		struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info;
1647 
1648 		if (ppdu_info->fcs_ok_cnt >=
1649 		    HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) {
1650 			hal_err("Number of MPDUs(%d) per status buff exceeded",
1651 				ppdu_info->fcs_ok_cnt);
1652 			break;
1653 		}
1654 
1655 		/* Update first_msdu_payload for every mpdu and increment
1656 		 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV
1657 		 */
1658 		ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload =
1659 			rx_tlv;
1660 		ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len;
1661 		ppdu_info->msdu_info.first_msdu_payload = rx_tlv;
1662 		ppdu_info->msdu_info.payload_len = tlv_len;
1663 		ppdu_info->user_id = user_id;
1664 		ppdu_info->hdr_len = tlv_len;
1665 		ppdu_info->data = rx_tlv;
1666 		ppdu_info->data += 4;
1667 
1668 		/* for every RX_HEADER TLV increment mpdu_cnt */
1669 		com_info->mpdu_cnt++;
1670 		return HAL_TLV_STATUS_HEADER;
1671 	}
1672 	case WIFIRX_MPDU_START_E:
1673 	{
1674 		uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv;
1675 		uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start);
1676 		uint8_t filter_category = 0;
1677 
1678 		hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info);
1679 
1680 		ppdu_info->nac_info.fc_valid =
1681 				HAL_RX_GET_FC_VALID(rx_mpdu_start);
1682 
1683 		ppdu_info->nac_info.to_ds_flag =
1684 				HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start);
1685 
1686 		ppdu_info->nac_info.frame_control =
1687 			HAL_RX_GET(rx_mpdu_start,
1688 				   RX_MPDU_INFO_14,
1689 				   MPDU_FRAME_CONTROL_FIELD);
1690 
1691 		ppdu_info->sw_frame_group_id =
1692 			HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start);
1693 
1694 		ppdu_info->rx_user_status[user_id].sw_peer_id =
1695 			HAL_RX_GET_SW_PEER_ID(rx_mpdu_start);
1696 
1697 		hal_update_rx_ctrl_frame_stats(ppdu_info, user_id);
1698 
1699 		if (ppdu_info->sw_frame_group_id ==
1700 		    HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) {
1701 			ppdu_info->rx_status.frame_control_info_valid =
1702 				ppdu_info->nac_info.fc_valid;
1703 			ppdu_info->rx_status.frame_control =
1704 				ppdu_info->nac_info.frame_control;
1705 		}
1706 
1707 		hal_get_mac_addr1(rx_mpdu_start,
1708 				  ppdu_info);
1709 
1710 		ppdu_info->nac_info.mac_addr2_valid =
1711 				HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start);
1712 
1713 		*(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] =
1714 			HAL_RX_GET(rx_mpdu_start,
1715 				   RX_MPDU_INFO_16,
1716 				   MAC_ADDR_AD2_15_0);
1717 
1718 		*(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] =
1719 			HAL_RX_GET(rx_mpdu_start,
1720 				   RX_MPDU_INFO_17,
1721 				   MAC_ADDR_AD2_47_16);
1722 
1723 		if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) {
1724 			ppdu_info->rx_status.prev_ppdu_id = ppdu_id;
1725 			ppdu_info->rx_status.ppdu_len =
1726 				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
1727 					   MPDU_LENGTH);
1728 		} else {
1729 			ppdu_info->rx_status.ppdu_len +=
1730 				HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13,
1731 					   MPDU_LENGTH);
1732 		}
1733 
1734 		filter_category =
1735 				HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start);
1736 
1737 		if (filter_category == 0)
1738 			ppdu_info->rx_status.rxpcu_filter_pass = 1;
1739 		else if (filter_category == 1)
1740 			ppdu_info->rx_status.monitor_direct_used = 1;
1741 
1742 		ppdu_info->nac_info.mcast_bcast =
1743 			HAL_RX_GET(rx_mpdu_start,
1744 				   RX_MPDU_INFO_13,
1745 				   MCAST_BCAST);
1746 		break;
1747 	}
1748 	case WIFIRX_MPDU_END_E:
1749 		ppdu_info->user_id = user_id;
1750 		ppdu_info->fcs_err =
1751 			HAL_RX_GET(rx_tlv, RX_MPDU_END_1,
1752 				   FCS_ERR);
1753 		return HAL_TLV_STATUS_MPDU_END;
1754 	case WIFIRX_MSDU_END_E:
1755 		if (user_id < HAL_MAX_UL_MU_USERS) {
1756 			ppdu_info->rx_msdu_info[user_id].cce_metadata =
1757 				HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv);
1758 			ppdu_info->rx_msdu_info[user_id].fse_metadata =
1759 				HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv);
1760 			ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout =
1761 				HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv);
1762 			ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid =
1763 				HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv);
1764 			ppdu_info->rx_msdu_info[user_id].flow_idx =
1765 				HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv);
1766 		}
1767 		return HAL_TLV_STATUS_MSDU_END;
1768 	case 0:
1769 		return HAL_TLV_STATUS_PPDU_DONE;
1770 
1771 	default:
1772 		if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info))
1773 			unhandled = false;
1774 		else
1775 			unhandled = true;
1776 		break;
1777 	}
1778 
1779 	if (!unhandled)
1780 		QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
1781 			  "%s TLV type: %d, TLV len:%d %s",
1782 			  __func__, tlv_tag, tlv_len,
1783 			  unhandled == true ? "unhandled" : "");
1784 
1785 	return HAL_TLV_STATUS_PPDU_NOT_DONE;
1786 }
1787 
1788 /**
1789  * hal_tx_comp_get_release_reason_generic_li() - TQM Release reason
1790  * @hal_desc: completion ring descriptor pointer
1791  *
1792  * This function will return the type of pointer - buffer or descriptor
1793  *
1794  * Return: buffer type
1795  */
hal_tx_comp_get_release_reason_generic_li(void * hal_desc)1796 static inline uint8_t hal_tx_comp_get_release_reason_generic_li(void *hal_desc)
1797 {
1798 	uint32_t comp_desc =
1799 		*(uint32_t *)(((uint8_t *)hal_desc) +
1800 			       WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET);
1801 
1802 	return (comp_desc & WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK) >>
1803 		WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB;
1804 }
1805 
1806 /**
1807  * hal_get_wbm_internal_error_generic_li() - is WBM internal error
1808  * @hal_desc: completion ring descriptor pointer
1809  *
1810  * This function will return 0 or 1  - is it WBM internal error or not
1811  *
1812  * Return: uint8_t
1813  */
hal_get_wbm_internal_error_generic_li(void * hal_desc)1814 static inline uint8_t hal_get_wbm_internal_error_generic_li(void *hal_desc)
1815 {
1816 	uint32_t comp_desc =
1817 		*(uint32_t *)(((uint8_t *)hal_desc) +
1818 			      HAL_WBM_INTERNAL_ERROR_OFFSET);
1819 
1820 	return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >>
1821 		HAL_WBM_INTERNAL_ERROR_LSB;
1822 }
1823 
1824 /**
1825  * hal_rx_dump_rx_attention_tlv_generic_li() - dump RX attention TLV in
1826  *					       structured humman readable
1827  *					       format.
1828  * @pkttlvs: pointer the pkt tlv struct.
1829  * @dbg_level: log level.
1830  *
1831  * Return: void
1832  */
1833 static inline
hal_rx_dump_rx_attention_tlv_generic_li(void * pkttlvs,uint8_t dbg_level)1834 void hal_rx_dump_rx_attention_tlv_generic_li(void *pkttlvs,
1835 					     uint8_t dbg_level)
1836 {
1837 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
1838 	struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
1839 
1840 	hal_verbose_debug("rx_attention tlv (1/2) - "
1841 			  "rxpcu_mpdu_filter_in_category: %x "
1842 			  "sw_frame_group_id: %x "
1843 			  "reserved_0: %x "
1844 			  "phy_ppdu_id: %x "
1845 			  "first_mpdu : %x "
1846 			  "reserved_1a: %x "
1847 			  "mcast_bcast: %x "
1848 			  "ast_index_not_found: %x "
1849 			  "ast_index_timeout: %x "
1850 			  "power_mgmt: %x "
1851 			  "non_qos: %x "
1852 			  "null_data: %x "
1853 			  "mgmt_type: %x "
1854 			  "ctrl_type: %x "
1855 			  "more_data: %x "
1856 			  "eosp: %x "
1857 			  "a_msdu_error: %x "
1858 			  "fragment_flag: %x "
1859 			  "order: %x "
1860 			  "cce_match: %x "
1861 			  "overflow_err: %x "
1862 			  "msdu_length_err: %x "
1863 			  "tcp_udp_chksum_fail: %x "
1864 			  "ip_chksum_fail: %x "
1865 			  "sa_idx_invalid: %x "
1866 			  "da_idx_invalid: %x "
1867 			  "reserved_1b: %x "
1868 			  "rx_in_tx_decrypt_byp: %x ",
1869 			  rx_attn->rxpcu_mpdu_filter_in_category,
1870 			  rx_attn->sw_frame_group_id,
1871 			  rx_attn->reserved_0,
1872 			  rx_attn->phy_ppdu_id,
1873 			  rx_attn->first_mpdu,
1874 			  rx_attn->reserved_1a,
1875 			  rx_attn->mcast_bcast,
1876 			  rx_attn->ast_index_not_found,
1877 			  rx_attn->ast_index_timeout,
1878 			  rx_attn->power_mgmt,
1879 			  rx_attn->non_qos,
1880 			  rx_attn->null_data,
1881 			  rx_attn->mgmt_type,
1882 			  rx_attn->ctrl_type,
1883 			  rx_attn->more_data,
1884 			  rx_attn->eosp,
1885 			  rx_attn->a_msdu_error,
1886 			  rx_attn->fragment_flag,
1887 			  rx_attn->order,
1888 			  rx_attn->cce_match,
1889 			  rx_attn->overflow_err,
1890 			  rx_attn->msdu_length_err,
1891 			  rx_attn->tcp_udp_chksum_fail,
1892 			  rx_attn->ip_chksum_fail,
1893 			  rx_attn->sa_idx_invalid,
1894 			  rx_attn->da_idx_invalid,
1895 			  rx_attn->reserved_1b,
1896 			  rx_attn->rx_in_tx_decrypt_byp);
1897 
1898 	hal_verbose_debug("rx_attention tlv (2/2) - "
1899 			  "encrypt_required: %x "
1900 			  "directed: %x "
1901 			  "buffer_fragment: %x "
1902 			  "mpdu_length_err: %x "
1903 			  "tkip_mic_err: %x "
1904 			  "decrypt_err: %x "
1905 			  "unencrypted_frame_err: %x "
1906 			  "fcs_err: %x "
1907 			  "flow_idx_timeout: %x "
1908 			  "flow_idx_invalid: %x "
1909 			  "wifi_parser_error: %x "
1910 			  "amsdu_parser_error: %x "
1911 			  "sa_idx_timeout: %x "
1912 			  "da_idx_timeout: %x "
1913 			  "msdu_limit_error: %x "
1914 			  "da_is_valid: %x "
1915 			  "da_is_mcbc: %x "
1916 			  "sa_is_valid: %x "
1917 			  "decrypt_status_code: %x "
1918 			  "rx_bitmap_not_updated: %x "
1919 			  "reserved_2: %x "
1920 			  "msdu_done: %x ",
1921 			  rx_attn->encrypt_required,
1922 			  rx_attn->directed,
1923 			  rx_attn->buffer_fragment,
1924 			  rx_attn->mpdu_length_err,
1925 			  rx_attn->tkip_mic_err,
1926 			  rx_attn->decrypt_err,
1927 			  rx_attn->unencrypted_frame_err,
1928 			  rx_attn->fcs_err,
1929 			  rx_attn->flow_idx_timeout,
1930 			  rx_attn->flow_idx_invalid,
1931 			  rx_attn->wifi_parser_error,
1932 			  rx_attn->amsdu_parser_error,
1933 			  rx_attn->sa_idx_timeout,
1934 			  rx_attn->da_idx_timeout,
1935 			  rx_attn->msdu_limit_error,
1936 			  rx_attn->da_is_valid,
1937 			  rx_attn->da_is_mcbc,
1938 			  rx_attn->sa_is_valid,
1939 			  rx_attn->decrypt_status_code,
1940 			  rx_attn->rx_bitmap_not_updated,
1941 			  rx_attn->reserved_2,
1942 			  rx_attn->msdu_done);
1943 }
1944 
1945 /**
1946  * hal_rx_dump_mpdu_end_tlv_generic_li() - dump RX mpdu_end TLV in structured
1947  *					   human readable format.
1948  * @pkttlvs: pointer the pkt tlv struct.
1949  * @dbg_level: log level.
1950  *
1951  * Return: void
1952  */
1953 static inline
hal_rx_dump_mpdu_end_tlv_generic_li(void * pkttlvs,uint8_t dbg_level)1954 void hal_rx_dump_mpdu_end_tlv_generic_li(void *pkttlvs,
1955 					 uint8_t dbg_level)
1956 {
1957 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
1958 	struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
1959 
1960 	hal_verbose_debug("rx_mpdu_end tlv - "
1961 			  "rxpcu_mpdu_filter_in_category: %x "
1962 			  "sw_frame_group_id: %x "
1963 			  "phy_ppdu_id: %x "
1964 			  "unsup_ktype_short_frame: %x "
1965 			  "rx_in_tx_decrypt_byp: %x "
1966 			  "overflow_err: %x "
1967 			  "mpdu_length_err: %x "
1968 			  "tkip_mic_err: %x "
1969 			  "decrypt_err: %x "
1970 			  "unencrypted_frame_err: %x "
1971 			  "pn_fields_contain_valid_info: %x "
1972 			  "fcs_err: %x "
1973 			  "msdu_length_err: %x "
1974 			  "rxdma0_destination_ring: %x "
1975 			  "rxdma1_destination_ring: %x "
1976 			  "decrypt_status_code: %x "
1977 			  "rx_bitmap_not_updated: %x ",
1978 			  mpdu_end->rxpcu_mpdu_filter_in_category,
1979 			  mpdu_end->sw_frame_group_id,
1980 			  mpdu_end->phy_ppdu_id,
1981 			  mpdu_end->unsup_ktype_short_frame,
1982 			  mpdu_end->rx_in_tx_decrypt_byp,
1983 			  mpdu_end->overflow_err,
1984 			  mpdu_end->mpdu_length_err,
1985 			  mpdu_end->tkip_mic_err,
1986 			  mpdu_end->decrypt_err,
1987 			  mpdu_end->unencrypted_frame_err,
1988 			  mpdu_end->pn_fields_contain_valid_info,
1989 			  mpdu_end->fcs_err,
1990 			  mpdu_end->msdu_length_err,
1991 			  mpdu_end->rxdma0_destination_ring,
1992 			  mpdu_end->rxdma1_destination_ring,
1993 			  mpdu_end->decrypt_status_code,
1994 			  mpdu_end->rx_bitmap_not_updated);
1995 }
1996 
1997 #ifdef NO_RX_PKT_HDR_TLV
1998 static inline
hal_rx_dump_pkt_hdr_tlv_generic_li(void * pkttlvs,uint8_t dbg_level)1999 void hal_rx_dump_pkt_hdr_tlv_generic_li(void *pkttlvs,
2000 					uint8_t dbg_level)
2001 {
2002 }
2003 #else
2004 /**
2005  * hal_rx_dump_pkt_hdr_tlv_generic_li() - dump RX pkt header TLV in hex format
2006  * @pkttlvs: pointer the pkt tlv struct.
2007  * @dbg_level: log level.
2008  *
2009  * Return: void
2010  */
2011 static inline
hal_rx_dump_pkt_hdr_tlv_generic_li(void * pkttlvs,uint8_t dbg_level)2012 void hal_rx_dump_pkt_hdr_tlv_generic_li(void *pkttlvs,
2013 					uint8_t dbg_level)
2014 {
2015 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
2016 	struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
2017 
2018 	hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv"
2019 			  "\n---------------\nphy_ppdu_id %d ",
2020 			  pkt_hdr_tlv->phy_ppdu_id);
2021 	hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
2022 }
2023 #endif
2024 
2025 /**
2026  * hal_rx_tlv_decrypt_err_get_li() - API to get the Decrypt ERR
2027  * from rx_mpdu_end TLV
2028  *
2029  * @buf: pointer to the start of RX PKT TLV headers
2030  * Return: uint32_t(decrypt_err)
2031  */
2032 static inline uint32_t
hal_rx_tlv_decrypt_err_get_li(uint8_t * buf)2033 hal_rx_tlv_decrypt_err_get_li(uint8_t *buf)
2034 {
2035 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
2036 	struct rx_mpdu_end *mpdu_end =
2037 		&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
2038 	uint32_t decrypt_err;
2039 
2040 	decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
2041 
2042 	return decrypt_err;
2043 }
2044 
2045 /**
2046  * hal_rx_tlv_mic_err_get_li() - API to get the MIC ERR
2047  * from rx_mpdu_end TLV
2048  *
2049  * @buf: pointer to the start of RX PKT TLV headers
2050  * Return: uint32_t(mic_err)
2051  */
2052 static inline uint32_t
hal_rx_tlv_mic_err_get_li(uint8_t * buf)2053 hal_rx_tlv_mic_err_get_li(uint8_t *buf)
2054 {
2055 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
2056 	struct rx_mpdu_end *mpdu_end =
2057 		&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
2058 	uint32_t mic_err;
2059 
2060 	mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
2061 
2062 	return mic_err;
2063 }
2064 
2065 static
hal_rx_tlv_get_pkt_capture_flags_li(uint8_t * rx_tlv_pkt_hdr,struct hal_rx_pkt_capture_flags * flags)2066 void hal_rx_tlv_get_pkt_capture_flags_li(uint8_t *rx_tlv_pkt_hdr,
2067 					 struct hal_rx_pkt_capture_flags *flags)
2068 {
2069 	struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr;
2070 	struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn;
2071 	struct rx_mpdu_start *mpdu_start =
2072 				&rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start;
2073 	struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end;
2074 	struct rx_msdu_start *msdu_start =
2075 				&rx_tlv_hdr->msdu_start_tlv.rx_msdu_start;
2076 
2077 	flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type;
2078 	flags->fcs_err = mpdu_end->fcs_err;
2079 	flags->fragment_flag = rx_attn->fragment_flag;
2080 	flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
2081 	flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
2082 	flags->tsft = msdu_start->ppdu_start_timestamp;
2083 }
2084 
2085 static inline bool
hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t * buf)2086 hal_rx_mpdu_info_ampdu_flag_get_li(uint8_t *buf)
2087 {
2088 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
2089 	struct rx_mpdu_start *mpdu_start =
2090 				 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
2091 
2092 	struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
2093 	bool ampdu_flag;
2094 
2095 	ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
2096 
2097 	return ampdu_flag;
2098 }
2099 
2100 /**
2101  * hal_rx_tlv_get_pn_num_li() - Get packet number from RX TLV
2102  * @buf: rx tlv address
2103  * @pn_num: buffer to store packet number
2104  *
2105  * Return: None
2106  */
hal_rx_tlv_get_pn_num_li(uint8_t * buf,uint64_t * pn_num)2107 static inline void hal_rx_tlv_get_pn_num_li(uint8_t *buf, uint64_t *pn_num)
2108 {
2109 	struct rx_pkt_tlvs *rx_pkt_tlv =
2110 			(struct rx_pkt_tlvs *)buf;
2111 	struct rx_mpdu_info *rx_mpdu_info_details =
2112 	 &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
2113 
2114 	pn_num[0] = rx_mpdu_info_details->pn_31_0;
2115 	pn_num[0] |=
2116 		((uint64_t)rx_mpdu_info_details->pn_63_32 << 32);
2117 	pn_num[1] = rx_mpdu_info_details->pn_95_64;
2118 	pn_num[1] |=
2119 		((uint64_t)rx_mpdu_info_details->pn_127_96 << 32);
2120 }
2121 
2122 /**
2123  * hal_rx_dump_mpdu_start_tlv_generic_li() - dump RX mpdu_start TLV in
2124  *			                     structured human readable
2125  *			                     format.
2126  * @pkttlvs: pointer to the pkttlvs.
2127  * @dbg_level: log level.
2128  *
2129  * Return: void
2130  */
2131 static inline
hal_rx_dump_mpdu_start_tlv_generic_li(void * pkttlvs,uint8_t dbg_level)2132 void hal_rx_dump_mpdu_start_tlv_generic_li(void *pkttlvs,
2133 					   uint8_t dbg_level)
2134 {
2135 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
2136 	struct rx_mpdu_start *mpdu_start =
2137 					&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
2138 	struct rx_mpdu_info *mpdu_info =
2139 		(struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
2140 
2141 	hal_verbose_debug(
2142 			  "rx_mpdu_start tlv (1/5) - "
2143 			  "rxpcu_mpdu_filter_in_category: %x "
2144 			  "sw_frame_group_id: %x "
2145 			  "ndp_frame: %x "
2146 			  "phy_err: %x "
2147 			  "phy_err_during_mpdu_header: %x "
2148 			  "protocol_version_err: %x "
2149 			  "ast_based_lookup_valid: %x "
2150 			  "phy_ppdu_id: %x "
2151 			  "ast_index: %x "
2152 			  "sw_peer_id: %x "
2153 			  "mpdu_frame_control_valid: %x "
2154 			  "mpdu_duration_valid: %x "
2155 			  "mac_addr_ad1_valid: %x "
2156 			  "mac_addr_ad2_valid: %x "
2157 			  "mac_addr_ad3_valid: %x "
2158 			  "mac_addr_ad4_valid: %x "
2159 			  "mpdu_sequence_control_valid: %x "
2160 			  "mpdu_qos_control_valid: %x "
2161 			  "mpdu_ht_control_valid: %x "
2162 			  "frame_encryption_info_valid: %x ",
2163 			  mpdu_info->rxpcu_mpdu_filter_in_category,
2164 			  mpdu_info->sw_frame_group_id,
2165 			  mpdu_info->ndp_frame,
2166 			  mpdu_info->phy_err,
2167 			  mpdu_info->phy_err_during_mpdu_header,
2168 			  mpdu_info->protocol_version_err,
2169 			  mpdu_info->ast_based_lookup_valid,
2170 			  mpdu_info->phy_ppdu_id,
2171 			  mpdu_info->ast_index,
2172 			  mpdu_info->sw_peer_id,
2173 			  mpdu_info->mpdu_frame_control_valid,
2174 			  mpdu_info->mpdu_duration_valid,
2175 			  mpdu_info->mac_addr_ad1_valid,
2176 			  mpdu_info->mac_addr_ad2_valid,
2177 			  mpdu_info->mac_addr_ad3_valid,
2178 			  mpdu_info->mac_addr_ad4_valid,
2179 			  mpdu_info->mpdu_sequence_control_valid,
2180 			  mpdu_info->mpdu_qos_control_valid,
2181 			  mpdu_info->mpdu_ht_control_valid,
2182 			  mpdu_info->frame_encryption_info_valid);
2183 
2184 	hal_verbose_debug(
2185 			  "rx_mpdu_start tlv (2/5) - "
2186 			  "fr_ds: %x "
2187 			  "to_ds: %x "
2188 			  "encrypted: %x "
2189 			  "mpdu_retry: %x "
2190 			  "mpdu_sequence_number: %x "
2191 			  "epd_en: %x "
2192 			  "all_frames_shall_be_encrypted: %x "
2193 			  "encrypt_type: %x "
2194 			  "mesh_sta: %x "
2195 			  "bssid_hit: %x "
2196 			  "bssid_number: %x "
2197 			  "tid: %x "
2198 			  "pn_31_0: %x "
2199 			  "pn_63_32: %x "
2200 			  "pn_95_64: %x "
2201 			  "pn_127_96: %x "
2202 			  "peer_meta_data: %x "
2203 			  "rxpt_classify_info.reo_destination_indication: %x "
2204 			  "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x "
2205 			  "rx_reo_queue_desc_addr_31_0: %x ",
2206 			  mpdu_info->fr_ds,
2207 			  mpdu_info->to_ds,
2208 			  mpdu_info->encrypted,
2209 			  mpdu_info->mpdu_retry,
2210 			  mpdu_info->mpdu_sequence_number,
2211 			  mpdu_info->epd_en,
2212 			  mpdu_info->all_frames_shall_be_encrypted,
2213 			  mpdu_info->encrypt_type,
2214 			  mpdu_info->mesh_sta,
2215 			  mpdu_info->bssid_hit,
2216 			  mpdu_info->bssid_number,
2217 			  mpdu_info->tid,
2218 			  mpdu_info->pn_31_0,
2219 			  mpdu_info->pn_63_32,
2220 			  mpdu_info->pn_95_64,
2221 			  mpdu_info->pn_127_96,
2222 			  mpdu_info->peer_meta_data,
2223 			  mpdu_info->rxpt_classify_info_details.reo_destination_indication,
2224 			  mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy,
2225 			  mpdu_info->rx_reo_queue_desc_addr_31_0);
2226 
2227 	hal_verbose_debug(
2228 			  "rx_mpdu_start tlv (3/5) - "
2229 			  "rx_reo_queue_desc_addr_39_32: %x "
2230 			  "receive_queue_number: %x "
2231 			  "pre_delim_err_warning: %x "
2232 			  "first_delim_err: %x "
2233 			  "key_id_octet: %x "
2234 			  "new_peer_entry: %x "
2235 			  "decrypt_needed: %x "
2236 			  "decap_type: %x "
2237 			  "rx_insert_vlan_c_tag_padding: %x "
2238 			  "rx_insert_vlan_s_tag_padding: %x "
2239 			  "strip_vlan_c_tag_decap: %x "
2240 			  "strip_vlan_s_tag_decap: %x "
2241 			  "pre_delim_count: %x "
2242 			  "ampdu_flag: %x "
2243 			  "bar_frame: %x "
2244 			  "mpdu_length: %x "
2245 			  "first_mpdu: %x "
2246 			  "mcast_bcast: %x "
2247 			  "ast_index_not_found: %x "
2248 			  "ast_index_timeout: %x ",
2249 			  mpdu_info->rx_reo_queue_desc_addr_39_32,
2250 			  mpdu_info->receive_queue_number,
2251 			  mpdu_info->pre_delim_err_warning,
2252 			  mpdu_info->first_delim_err,
2253 			  mpdu_info->key_id_octet,
2254 			  mpdu_info->new_peer_entry,
2255 			  mpdu_info->decrypt_needed,
2256 			  mpdu_info->decap_type,
2257 			  mpdu_info->rx_insert_vlan_c_tag_padding,
2258 			  mpdu_info->rx_insert_vlan_s_tag_padding,
2259 			  mpdu_info->strip_vlan_c_tag_decap,
2260 			  mpdu_info->strip_vlan_s_tag_decap,
2261 			  mpdu_info->pre_delim_count,
2262 			  mpdu_info->ampdu_flag,
2263 			  mpdu_info->bar_frame,
2264 			  mpdu_info->mpdu_length,
2265 			  mpdu_info->first_mpdu,
2266 			  mpdu_info->mcast_bcast,
2267 			  mpdu_info->ast_index_not_found,
2268 			  mpdu_info->ast_index_timeout);
2269 
2270 	hal_verbose_debug(
2271 			  "rx_mpdu_start tlv (4/5) - "
2272 			  "power_mgmt: %x "
2273 			  "non_qos: %x "
2274 			  "null_data: %x "
2275 			  "mgmt_type: %x "
2276 			  "ctrl_type: %x "
2277 			  "more_data: %x "
2278 			  "eosp: %x "
2279 			  "fragment_flag: %x "
2280 			  "order: %x "
2281 			  "u_apsd_trigger: %x "
2282 			  "encrypt_required: %x "
2283 			  "directed: %x "
2284 			  "mpdu_frame_control_field: %x "
2285 			  "mpdu_duration_field: %x "
2286 			  "mac_addr_ad1_31_0: %x "
2287 			  "mac_addr_ad1_47_32: %x "
2288 			  "mac_addr_ad2_15_0: %x "
2289 			  "mac_addr_ad2_47_16: %x "
2290 			  "mac_addr_ad3_31_0: %x "
2291 			  "mac_addr_ad3_47_32: %x ",
2292 			  mpdu_info->power_mgmt,
2293 			  mpdu_info->non_qos,
2294 			  mpdu_info->null_data,
2295 			  mpdu_info->mgmt_type,
2296 			  mpdu_info->ctrl_type,
2297 			  mpdu_info->more_data,
2298 			  mpdu_info->eosp,
2299 			  mpdu_info->fragment_flag,
2300 			  mpdu_info->order,
2301 			  mpdu_info->u_apsd_trigger,
2302 			  mpdu_info->encrypt_required,
2303 			  mpdu_info->directed,
2304 			  mpdu_info->mpdu_frame_control_field,
2305 			  mpdu_info->mpdu_duration_field,
2306 			  mpdu_info->mac_addr_ad1_31_0,
2307 			  mpdu_info->mac_addr_ad1_47_32,
2308 			  mpdu_info->mac_addr_ad2_15_0,
2309 			  mpdu_info->mac_addr_ad2_47_16,
2310 			  mpdu_info->mac_addr_ad3_31_0,
2311 			  mpdu_info->mac_addr_ad3_47_32);
2312 
2313 	hal_verbose_debug(
2314 			  "rx_mpdu_start tlv (5/5) - "
2315 			  "mpdu_sequence_control_field: %x "
2316 			  "mac_addr_ad4_31_0: %x "
2317 			  "mac_addr_ad4_47_32: %x "
2318 			  "mpdu_qos_control_field: %x "
2319 			  "mpdu_ht_control_field: %x ",
2320 			  mpdu_info->mpdu_sequence_control_field,
2321 			  mpdu_info->mac_addr_ad4_31_0,
2322 			  mpdu_info->mac_addr_ad4_47_32,
2323 			  mpdu_info->mpdu_qos_control_field,
2324 			  mpdu_info->mpdu_ht_control_field);
2325 }
2326 
2327 /**
2328  * hal_tx_set_pcp_tid_map_generic_li() - Configure default PCP to TID map table
2329  * @soc: HAL SoC context
2330  * @map: PCP-TID mapping table
2331  *
2332  * PCP are mapped to 8 TID values using TID values programmed
2333  * in one set of mapping registers PCP_TID_MAP_<0 to 6>
2334  * The mapping register has TID mapping for 8 PCP values
2335  *
2336  * Return: none
2337  */
hal_tx_set_pcp_tid_map_generic_li(struct hal_soc * soc,uint8_t * map)2338 static void hal_tx_set_pcp_tid_map_generic_li(struct hal_soc *soc, uint8_t *map)
2339 {
2340 	uint32_t addr, value;
2341 
2342 	addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
2343 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
2344 
2345 	value = (map[0] |
2346 		(map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) |
2347 		(map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) |
2348 		(map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) |
2349 		(map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) |
2350 		(map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) |
2351 		(map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) |
2352 		(map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT));
2353 
2354 	HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
2355 }
2356 
2357 /**
2358  * hal_tx_update_pcp_tid_generic_li() - Update the pcp tid map table with
2359  *					value received from user-space
2360  * @soc: HAL SoC context
2361  * @pcp: pcp value
2362  * @tid : tid value
2363  *
2364  * Return: void
2365  */
2366 static void
hal_tx_update_pcp_tid_generic_li(struct hal_soc * soc,uint8_t pcp,uint8_t tid)2367 hal_tx_update_pcp_tid_generic_li(struct hal_soc *soc,
2368 				 uint8_t pcp, uint8_t tid)
2369 {
2370 	uint32_t addr, value, regval;
2371 
2372 	addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR(
2373 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
2374 
2375 	value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp);
2376 
2377 	/* Read back previous PCP TID config and update
2378 	 * with new config.
2379 	 */
2380 	regval = HAL_REG_READ(soc, addr);
2381 	regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp));
2382 	regval |= value;
2383 
2384 	HAL_REG_WRITE(soc, addr,
2385 		      (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK));
2386 }
2387 
2388 /**
2389  * hal_tx_update_tidmap_prty_generic_li() - Update the tid map priority
2390  * @soc: HAL SoC context
2391  * @value: priority value
2392  *
2393  * Return: void
2394  */
2395 static
hal_tx_update_tidmap_prty_generic_li(struct hal_soc * soc,uint8_t value)2396 void hal_tx_update_tidmap_prty_generic_li(struct hal_soc *soc, uint8_t value)
2397 {
2398 	uint32_t addr;
2399 
2400 	addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR(
2401 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
2402 
2403 	HAL_REG_WRITE(soc, addr,
2404 		      (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK));
2405 }
2406 
2407 /**
2408  * hal_rx_msdu_packet_metadata_get_generic_li() - API to get the msdu
2409  *                                                information from
2410  *                                                rx_msdu_end TLV
2411  * @buf: pointer to the start of RX PKT TLV headers
2412  * @pkt_msdu_metadata: pointer to the msdu info structure
2413  */
2414 static void
hal_rx_msdu_packet_metadata_get_generic_li(uint8_t * buf,void * pkt_msdu_metadata)2415 hal_rx_msdu_packet_metadata_get_generic_li(uint8_t *buf,
2416 					   void *pkt_msdu_metadata)
2417 {
2418 	struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
2419 	struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
2420 	struct hal_rx_msdu_metadata *msdu_metadata =
2421 		(struct hal_rx_msdu_metadata *)pkt_msdu_metadata;
2422 
2423 	msdu_metadata->l3_hdr_pad =
2424 		HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
2425 	msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
2426 	msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
2427 	msdu_metadata->sa_sw_peer_id =
2428 		HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
2429 }
2430 
2431 /**
2432  * hal_rx_msdu_end_offset_get_generic() - API to get the
2433  * msdu_end structure offset rx_pkt_tlv structure
2434  *
2435  * NOTE: API returns offset of msdu_end TLV from structure
2436  * rx_pkt_tlvs
2437  */
hal_rx_msdu_end_offset_get_generic(void)2438 static uint32_t hal_rx_msdu_end_offset_get_generic(void)
2439 {
2440 	return RX_PKT_TLV_OFFSET(msdu_end_tlv);
2441 }
2442 
2443 /**
2444  * hal_rx_attn_offset_get_generic() - API to get the
2445  * msdu_end structure offset rx_pkt_tlv structure
2446  *
2447  * NOTE: API returns offset of attn TLV from structure
2448  * rx_pkt_tlvs
2449  */
hal_rx_attn_offset_get_generic(void)2450 static uint32_t hal_rx_attn_offset_get_generic(void)
2451 {
2452 	return RX_PKT_TLV_OFFSET(attn_tlv);
2453 }
2454 
2455 /**
2456  * hal_rx_msdu_start_offset_get_generic() - API to get the
2457  * msdu_start structure offset rx_pkt_tlv structure
2458  *
2459  * NOTE: API returns offset of attn TLV from structure
2460  * rx_pkt_tlvs
2461  */
hal_rx_msdu_start_offset_get_generic(void)2462 static uint32_t hal_rx_msdu_start_offset_get_generic(void)
2463 {
2464 	return RX_PKT_TLV_OFFSET(msdu_start_tlv);
2465 }
2466 
2467 /**
2468  * hal_rx_mpdu_start_offset_get_generic() - API to get the
2469  * mpdu_start structure offset rx_pkt_tlv structure
2470  *
2471  * NOTE: API returns offset of attn TLV from structure
2472  * rx_pkt_tlvs
2473  */
hal_rx_mpdu_start_offset_get_generic(void)2474 static uint32_t hal_rx_mpdu_start_offset_get_generic(void)
2475 {
2476 	return RX_PKT_TLV_OFFSET(mpdu_start_tlv);
2477 }
2478 
2479 /**
2480  * hal_rx_mpdu_end_offset_get_generic() - API to get the
2481  * mpdu_end structure offset rx_pkt_tlv structure
2482  *
2483  * NOTE: API returns offset of attn TLV from structure
2484  * rx_pkt_tlvs
2485  */
hal_rx_mpdu_end_offset_get_generic(void)2486 static uint32_t hal_rx_mpdu_end_offset_get_generic(void)
2487 {
2488 	return RX_PKT_TLV_OFFSET(mpdu_end_tlv);
2489 }
2490 
2491 #ifndef NO_RX_PKT_HDR_TLV
hal_rx_pkt_tlv_offset_get_generic(void)2492 static uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
2493 {
2494 	return RX_PKT_TLV_OFFSET(pkt_hdr_tlv);
2495 }
2496 #endif
2497 
2498 #if defined(QDF_BIG_ENDIAN_MACHINE)
2499 /**
2500  * hal_setup_reo_swap() - Set the swap flag for big endian machines
2501  * @soc: HAL soc handle
2502  *
2503  * Return: None
2504  */
hal_setup_reo_swap(struct hal_soc * soc)2505 static inline void hal_setup_reo_swap(struct hal_soc *soc)
2506 {
2507 	uint32_t reg_val;
2508 
2509 	reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
2510 		SEQ_WCSS_UMAC_REO_REG_OFFSET));
2511 
2512 	reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1);
2513 	reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1);
2514 
2515 	HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
2516 		SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
2517 }
2518 #else
hal_setup_reo_swap(struct hal_soc * soc)2519 static inline void hal_setup_reo_swap(struct hal_soc *soc)
2520 {
2521 }
2522 #endif
2523 
2524 /**
2525  * hal_reo_setup_generic_li() - Initialize HW REO block
2526  * @soc: Opaque HAL SOC handle
2527  * @reoparams: parameters needed by HAL for REO config
2528  * @qref_reset: reset qref
2529  */
2530 static
hal_reo_setup_generic_li(struct hal_soc * soc,void * reoparams,int qref_reset)2531 void hal_reo_setup_generic_li(struct hal_soc *soc, void *reoparams,
2532 			      int qref_reset)
2533 {
2534 	uint32_t reg_val;
2535 	struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
2536 
2537 	reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
2538 		SEQ_WCSS_UMAC_REO_REG_OFFSET));
2539 
2540 	hal_reo_config(soc, reg_val, reo_params);
2541 	/* Other ring enable bits and REO_ENABLE will be set by FW */
2542 
2543 	/* TODO: Setup destination ring mapping if enabled */
2544 
2545 	/* TODO: Error destination ring setting is left to default.
2546 	 * Default setting is to send all errors to release ring.
2547 	 */
2548 
2549 	/* Set the reo descriptor swap bits in case of BIG endian platform */
2550 	hal_setup_reo_swap(soc);
2551 
2552 	HAL_REG_WRITE(soc,
2553 		      HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
2554 		      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2555 		      HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
2556 
2557 	HAL_REG_WRITE(soc,
2558 		      HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
2559 		      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2560 		      (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
2561 
2562 	HAL_REG_WRITE(soc,
2563 		      HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
2564 		      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2565 		      (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
2566 
2567 	HAL_REG_WRITE(soc,
2568 		      HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
2569 		      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2570 		      (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
2571 
2572 	/*
2573 	 * When hash based routing is enabled, routing of the rx packet
2574 	 * is done based on the following value: 1 _ _ _ _ The last 4
2575 	 * bits are based on hash[3:0]. This means the possible values
2576 	 * are 0x10 to 0x1f. This value is used to look-up the
2577 	 * ring ID configured in Destination_Ring_Ctrl_IX_* register.
2578 	 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
2579 	 * registers need to be configured to set-up the 16 entries to
2580 	 * map the hash values to a ring number. There are 3 bits per
2581 	 * hash entry – which are mapped as follows:
2582 	 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
2583 	 * 7: NOT_USED.
2584 	 */
2585 	if (reo_params->rx_hash_enabled) {
2586 		if (reo_params->remap0)
2587 			HAL_REG_WRITE(soc,
2588 				      HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
2589 				      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2590 				      reo_params->remap0);
2591 
2592 		hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x",
2593 			  HAL_REG_READ(soc,
2594 				       HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
2595 				       SEQ_WCSS_UMAC_REO_REG_OFFSET)));
2596 
2597 		HAL_REG_WRITE(soc,
2598 			      HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
2599 			      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2600 			      reo_params->remap1);
2601 
2602 		hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
2603 			  HAL_REG_READ(soc,
2604 				       HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
2605 				       SEQ_WCSS_UMAC_REO_REG_OFFSET)));
2606 
2607 		HAL_REG_WRITE(soc,
2608 			      HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
2609 			      SEQ_WCSS_UMAC_REO_REG_OFFSET),
2610 			      reo_params->remap2);
2611 
2612 		hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
2613 			  HAL_REG_READ(soc,
2614 				       HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
2615 				       SEQ_WCSS_UMAC_REO_REG_OFFSET)));
2616 	}
2617 
2618 	/* TODO: Check if the following registers shoould be setup by host:
2619 	 * AGING_CONTROL
2620 	 * HIGH_MEMORY_THRESHOLD
2621 	 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
2622 	 * GLOBAL_LINK_DESC_COUNT_CTRL
2623 	 */
2624 }
2625 
2626 /**
2627  * hal_setup_link_idle_list_generic_li() - Setup scattered idle list
2628  *                                         using the buffer list provided
2629  * @soc: Opaque HAL SOC handle
2630  * @scatter_bufs_base_paddr: Array of physical base addresses
2631  * @scatter_bufs_base_vaddr: Array of virtual base addresses
2632  * @num_scatter_bufs: Number of scatter buffers in the above lists
2633  * @scatter_buf_size: Size of each scatter buffer
2634  * @last_buf_end_offset: Offset to the last entry
2635  * @num_entries: Total entries of all scatter bufs
2636  *
2637  * Return: None
2638  */
2639 static void
hal_setup_link_idle_list_generic_li(struct hal_soc * soc,qdf_dma_addr_t scatter_bufs_base_paddr[],void * scatter_bufs_base_vaddr[],uint32_t num_scatter_bufs,uint32_t scatter_buf_size,uint32_t last_buf_end_offset,uint32_t num_entries)2640 hal_setup_link_idle_list_generic_li(struct hal_soc *soc,
2641 				    qdf_dma_addr_t scatter_bufs_base_paddr[],
2642 				    void *scatter_bufs_base_vaddr[],
2643 				    uint32_t num_scatter_bufs,
2644 				    uint32_t scatter_buf_size,
2645 				    uint32_t last_buf_end_offset,
2646 				    uint32_t num_entries)
2647 {
2648 	int i;
2649 	uint32_t *prev_buf_link_ptr = NULL;
2650 	uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
2651 	uint32_t val;
2652 
2653 	/* Link the scatter buffers */
2654 	for (i = 0; i < num_scatter_bufs; i++) {
2655 		if (i > 0) {
2656 			prev_buf_link_ptr[0] =
2657 				scatter_bufs_base_paddr[i] & 0xffffffff;
2658 			prev_buf_link_ptr[1] = HAL_SM(
2659 				HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
2660 				BASE_ADDRESS_39_32,
2661 				((uint64_t)(scatter_bufs_base_paddr[i])
2662 				 >> 32)) | HAL_SM(
2663 				HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
2664 				ADDRESS_MATCH_TAG,
2665 				ADDRESS_MATCH_TAG_VAL);
2666 		}
2667 		prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
2668 			scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
2669 	}
2670 
2671 	/* TBD: Register programming partly based on MLD & the rest based on
2672 	 * inputs from HW team. Not complete yet.
2673 	 */
2674 
2675 	reg_scatter_buf_size = (scatter_buf_size -
2676 				WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
2677 	reg_tot_scatter_buf_size = ((scatter_buf_size -
2678 		WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
2679 
2680 	HAL_REG_WRITE(soc,
2681 		      HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR
2682 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2683 		      HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL,
2684 			     SCATTER_BUFFER_SIZE,
2685 			     reg_scatter_buf_size) |
2686 		      HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL,
2687 			     LINK_DESC_IDLE_LIST_MODE, 0x1));
2688 
2689 	HAL_REG_WRITE(soc,
2690 		      HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR
2691 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2692 		      HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
2693 			     SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
2694 			     reg_tot_scatter_buf_size));
2695 
2696 	HAL_REG_WRITE(soc,
2697 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR
2698 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2699 		      scatter_bufs_base_paddr[0] & 0xffffffff);
2700 
2701 	HAL_REG_WRITE(soc,
2702 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR
2703 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2704 		      ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
2705 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
2706 
2707 	HAL_REG_WRITE(soc,
2708 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR
2709 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2710 		      HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
2711 			     BASE_ADDRESS_39_32,
2712 			     ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
2713 		      HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
2714 			     ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
2715 
2716 	/* ADDRESS_MATCH_TAG field in the above register is expected to match
2717 	 * with the upper bits of link pointer. The above write sets this field
2718 	 * to zero and we are also setting the upper bits of link pointers to
2719 	 * zero while setting up the link list of scatter buffers above
2720 	 */
2721 
2722 	/* Setup head and tail pointers for the idle list */
2723 	HAL_REG_WRITE(soc,
2724 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR
2725 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2726 		      scatter_bufs_base_paddr[num_scatter_bufs - 1] &
2727 		      0xffffffff);
2728 	HAL_REG_WRITE(soc,
2729 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR
2730 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2731 		      HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
2732 			     BUFFER_ADDRESS_39_32,
2733 			     ((uint64_t)(scatter_bufs_base_paddr
2734 				     [num_scatter_bufs - 1]) >> 32)) |
2735 		      HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
2736 			     HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
2737 
2738 	HAL_REG_WRITE(soc,
2739 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR
2740 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2741 		      scatter_bufs_base_paddr[0] & 0xffffffff);
2742 
2743 	HAL_REG_WRITE(soc,
2744 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR
2745 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2746 		      scatter_bufs_base_paddr[0] & 0xffffffff);
2747 	HAL_REG_WRITE(soc,
2748 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR
2749 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2750 		      HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
2751 			     BUFFER_ADDRESS_39_32,
2752 			     ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32)) |
2753 		      HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
2754 			     TAIL_POINTER_OFFSET, 0));
2755 
2756 	HAL_REG_WRITE(soc,
2757 		      HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR
2758 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2 * num_entries);
2759 
2760 	/* Set RING_ID_DISABLE */
2761 	val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
2762 
2763 	/*
2764 	 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
2765 	 * check the presence of the bit before toggling it.
2766 	 */
2767 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
2768 	val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
2769 #endif
2770 	HAL_REG_WRITE(soc,
2771 		      HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR
2772 		      (SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2773 		      val);
2774 }
2775 
2776 #ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET
2777 /**
2778  * hal_tx_desc_set_search_type_generic_li() - Set the search type value
2779  * @desc: Handle to Tx Descriptor
2780  * @search_type: search type
2781  *		     0 – Normal search
2782  *		     1 – Index based address search
2783  *		     2 – Index based flow search
2784  *
2785  * Return: void
2786  */
2787 static inline
hal_tx_desc_set_search_type_generic_li(void * desc,uint8_t search_type)2788 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type)
2789 {
2790 	HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |=
2791 		HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type);
2792 }
2793 #else
2794 static inline
hal_tx_desc_set_search_type_generic_li(void * desc,uint8_t search_type)2795 void hal_tx_desc_set_search_type_generic_li(void *desc, uint8_t search_type)
2796 {
2797 }
2798 
2799 #endif
2800 
2801 #ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET
2802 /**
2803  * hal_tx_desc_set_search_index_generic_li() - Set the search index value
2804  * @desc: Handle to Tx Descriptor
2805  * @search_index: The index that will be used for index based address or
2806  *                flow search. The field is valid when 'search_type' is
2807  *                1 0r 2
2808  *
2809  * Return: void
2810  */
2811 static inline
hal_tx_desc_set_search_index_generic_li(void * desc,uint32_t search_index)2812 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index)
2813 {
2814 	HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |=
2815 		HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index);
2816 }
2817 #else
2818 static inline
hal_tx_desc_set_search_index_generic_li(void * desc,uint32_t search_index)2819 void hal_tx_desc_set_search_index_generic_li(void *desc, uint32_t search_index)
2820 {
2821 }
2822 #endif
2823 
2824 #ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET
2825 /**
2826  * hal_tx_desc_set_cache_set_num_generic_li() - Set the cache-set-num value
2827  * @desc: Handle to Tx Descriptor
2828  * @cache_num: Cache set number that should be used to cache the index
2829  *                based search results, for address and flow search.
2830  *                This value should be equal to LSB four bits of the hash value
2831  *                of match data, in case of search index points to an entry
2832  *                which may be used in content based search also. The value can
2833  *                be anything when the entry pointed by search index will not be
2834  *                used for content based search.
2835  *
2836  * Return: void
2837  */
2838 static inline
hal_tx_desc_set_cache_set_num_generic_li(void * desc,uint8_t cache_num)2839 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num)
2840 {
2841 	HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |=
2842 		HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num);
2843 }
2844 #else
2845 static inline
hal_tx_desc_set_cache_set_num_generic_li(void * desc,uint8_t cache_num)2846 void hal_tx_desc_set_cache_set_num_generic_li(void *desc, uint8_t cache_num)
2847 {
2848 }
2849 #endif
2850 
2851 #ifdef WLAN_SUPPORT_RX_FISA
2852 /**
2853  * hal_rx_flow_get_tuple_info_li() - Setup a flow search entry in HW FST
2854  * @rx_fst: Pointer to the Rx Flow Search Table
2855  * @hal_hash: HAL 5 tuple hash
2856  * @flow_tuple_info: 5-tuple info of the flow returned to the caller
2857  *
2858  * Return: Success/Failure
2859  */
2860 static void *
hal_rx_flow_get_tuple_info_li(uint8_t * rx_fst,uint32_t hal_hash,uint8_t * flow_tuple_info)2861 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash,
2862 			      uint8_t *flow_tuple_info)
2863 {
2864 	struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
2865 	void *hal_fse = NULL;
2866 	struct hal_flow_tuple_info *tuple_info
2867 		= (struct hal_flow_tuple_info *)flow_tuple_info;
2868 
2869 	hal_fse = (uint8_t *)fst->base_vaddr +
2870 		(hal_hash * HAL_RX_FST_ENTRY_SIZE);
2871 
2872 	if (!hal_fse || !tuple_info)
2873 		return NULL;
2874 
2875 	if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
2876 		return NULL;
2877 
2878 	tuple_info->src_ip_127_96 =
2879 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2880 						      RX_FLOW_SEARCH_ENTRY_0,
2881 						      SRC_IP_127_96));
2882 	tuple_info->src_ip_95_64 =
2883 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2884 						      RX_FLOW_SEARCH_ENTRY_1,
2885 						      SRC_IP_95_64));
2886 	tuple_info->src_ip_63_32 =
2887 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2888 						      RX_FLOW_SEARCH_ENTRY_2,
2889 						      SRC_IP_63_32));
2890 	tuple_info->src_ip_31_0 =
2891 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2892 						      RX_FLOW_SEARCH_ENTRY_3,
2893 						      SRC_IP_31_0));
2894 	tuple_info->dest_ip_127_96 =
2895 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2896 						      RX_FLOW_SEARCH_ENTRY_4,
2897 						      DEST_IP_127_96));
2898 	tuple_info->dest_ip_95_64 =
2899 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2900 						      RX_FLOW_SEARCH_ENTRY_5,
2901 						      DEST_IP_95_64));
2902 	tuple_info->dest_ip_63_32 =
2903 				qdf_ntohl(HAL_GET_FLD(hal_fse,
2904 						      RX_FLOW_SEARCH_ENTRY_6,
2905 						      DEST_IP_63_32));
2906 	tuple_info->dest_ip_31_0 =
2907 			qdf_ntohl(HAL_GET_FLD(hal_fse,
2908 					      RX_FLOW_SEARCH_ENTRY_7,
2909 					      DEST_IP_31_0));
2910 	tuple_info->dest_port = HAL_GET_FLD(hal_fse,
2911 					    RX_FLOW_SEARCH_ENTRY_8,
2912 					    DEST_PORT);
2913 	tuple_info->src_port = HAL_GET_FLD(hal_fse,
2914 					   RX_FLOW_SEARCH_ENTRY_8,
2915 					   SRC_PORT);
2916 	tuple_info->l4_protocol = HAL_GET_FLD(hal_fse,
2917 					      RX_FLOW_SEARCH_ENTRY_9,
2918 					      L4_PROTOCOL);
2919 
2920 	return hal_fse;
2921 }
2922 
2923 /**
2924  * hal_rx_flow_delete_entry_li() - Setup a flow search entry in HW FST
2925  * @rx_fst: Pointer to the Rx Flow Search Table
2926  * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST
2927  *
2928  * Return: Success/Failure
2929  */
2930 static QDF_STATUS
hal_rx_flow_delete_entry_li(uint8_t * rx_fst,void * hal_rx_fse)2931 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse)
2932 {
2933 	uint8_t *fse = (uint8_t *)hal_rx_fse;
2934 
2935 	if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID))
2936 		return QDF_STATUS_E_NOENT;
2937 
2938 	HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
2939 
2940 	return QDF_STATUS_SUCCESS;
2941 }
2942 
2943 /**
2944  * hal_rx_fst_get_fse_size_li() - Retrieve the size of each entry
2945  *
2946  * Return: size of each entry/flow in Rx FST
2947  */
2948 static inline uint32_t
hal_rx_fst_get_fse_size_li(void)2949 hal_rx_fst_get_fse_size_li(void)
2950 {
2951 	return HAL_RX_FST_ENTRY_SIZE;
2952 }
2953 #else
2954 static inline void *
hal_rx_flow_get_tuple_info_li(uint8_t * rx_fst,uint32_t hal_hash,uint8_t * flow_tuple_info)2955 hal_rx_flow_get_tuple_info_li(uint8_t *rx_fst, uint32_t hal_hash,
2956 			      uint8_t *flow_tuple_info)
2957 {
2958 	return NULL;
2959 }
2960 
2961 static inline QDF_STATUS
hal_rx_flow_delete_entry_li(uint8_t * rx_fst,void * hal_rx_fse)2962 hal_rx_flow_delete_entry_li(uint8_t *rx_fst, void *hal_rx_fse)
2963 {
2964 	return QDF_STATUS_SUCCESS;
2965 }
2966 
2967 static inline uint32_t
hal_rx_fst_get_fse_size_li(void)2968 hal_rx_fst_get_fse_size_li(void)
2969 {
2970 	return 0;
2971 }
2972 #endif /* WLAN_SUPPORT_RX_FISA */
2973 
2974 /**
2975  * hal_rx_get_frame_ctrl_field_li() - Function to retrieve frame control field
2976  * @buf: Network buffer
2977  *
2978  * Return: rx more fragment bit
2979  */
hal_rx_get_frame_ctrl_field_li(uint8_t * buf)2980 static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf)
2981 {
2982 	struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
2983 	struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
2984 	uint16_t frame_ctrl = 0;
2985 
2986 	frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
2987 
2988 	return frame_ctrl;
2989 }
2990 #endif /* _HAL_LI_GENERIC_API_H_ */
2991