1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for
6*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the
7*5113495bSYour Name * above copyright notice and this permission notice appear in all
8*5113495bSYour Name * copies.
9*5113495bSYour Name *
10*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE.
18*5113495bSYour Name */
19*5113495bSYour Name
20*5113495bSYour Name #include "qdf_module.h"
21*5113495bSYour Name #include "hal_li_hw_headers.h"
22*5113495bSYour Name #include "hal_reo.h"
23*5113495bSYour Name #include "hal_li_reo.h"
24*5113495bSYour Name #include "hal_li_api.h"
25*5113495bSYour Name
hal_get_reo_reg_base_offset_li(void)26*5113495bSYour Name uint32_t hal_get_reo_reg_base_offset_li(void)
27*5113495bSYour Name {
28*5113495bSYour Name return SEQ_WCSS_UMAC_REO_REG_OFFSET;
29*5113495bSYour Name }
30*5113495bSYour Name
hal_reo_qdesc_setup_li(hal_soc_handle_t hal_soc_hdl,int tid,uint32_t ba_window_size,uint32_t start_seq,void * hw_qdesc_vaddr,qdf_dma_addr_t hw_qdesc_paddr,int pn_type,uint8_t vdev_stats_id)31*5113495bSYour Name void hal_reo_qdesc_setup_li(hal_soc_handle_t hal_soc_hdl, int tid,
32*5113495bSYour Name uint32_t ba_window_size,
33*5113495bSYour Name uint32_t start_seq, void *hw_qdesc_vaddr,
34*5113495bSYour Name qdf_dma_addr_t hw_qdesc_paddr,
35*5113495bSYour Name int pn_type, uint8_t vdev_stats_id)
36*5113495bSYour Name {
37*5113495bSYour Name uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
38*5113495bSYour Name uint32_t *reo_queue_ext_desc;
39*5113495bSYour Name uint32_t reg_val;
40*5113495bSYour Name uint32_t pn_enable;
41*5113495bSYour Name uint32_t pn_size = 0;
42*5113495bSYour Name
43*5113495bSYour Name qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
44*5113495bSYour Name
45*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
46*5113495bSYour Name HAL_REO_QUEUE_DESC);
47*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
48*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER_0,
49*5113495bSYour Name RESERVED_0A, 0xDDBEEF);
50*5113495bSYour Name
51*5113495bSYour Name /* This a just a SW meta data and will be copied to REO destination
52*5113495bSYour Name * descriptors indicated by hardware.
53*5113495bSYour Name * TODO: Setting TID in this field. See if we should set something else.
54*5113495bSYour Name */
55*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_1,
56*5113495bSYour Name RECEIVE_QUEUE_NUMBER, tid);
57*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
58*5113495bSYour Name VLD, 1);
59*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
60*5113495bSYour Name ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
61*5113495bSYour Name HAL_RX_LINK_DESC_CNTR);
62*5113495bSYour Name
63*5113495bSYour Name /*
64*5113495bSYour Name * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
65*5113495bSYour Name */
66*5113495bSYour Name
67*5113495bSYour Name reg_val = TID_TO_WME_AC(tid);
68*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, AC, reg_val);
69*5113495bSYour Name
70*5113495bSYour Name if (ba_window_size < 1)
71*5113495bSYour Name ba_window_size = 1;
72*5113495bSYour Name
73*5113495bSYour Name /* WAR to get 2k exception in Non BA case.
74*5113495bSYour Name * Setting window size to 2 to get 2k jump exception
75*5113495bSYour Name * when we receive aggregates in Non BA case
76*5113495bSYour Name */
77*5113495bSYour Name ba_window_size = hal_update_non_ba_win_size(tid, ba_window_size);
78*5113495bSYour Name
79*5113495bSYour Name /* Set RTY bit for non-BA case. Duplicate detection is currently not
80*5113495bSYour Name * done by HW in non-BA case if RTY bit is not set.
81*5113495bSYour Name * TODO: This is a temporary War and should be removed once HW fix is
82*5113495bSYour Name * made to check and discard duplicates even if RTY bit is not set.
83*5113495bSYour Name */
84*5113495bSYour Name if (ba_window_size == 1)
85*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, RTY, 1);
86*5113495bSYour Name
87*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, BA_WINDOW_SIZE,
88*5113495bSYour Name ba_window_size - 1);
89*5113495bSYour Name
90*5113495bSYour Name switch (pn_type) {
91*5113495bSYour Name case HAL_PN_WPA:
92*5113495bSYour Name pn_enable = 1;
93*5113495bSYour Name pn_size = PN_SIZE_48;
94*5113495bSYour Name break;
95*5113495bSYour Name case HAL_PN_WAPI_EVEN:
96*5113495bSYour Name case HAL_PN_WAPI_UNEVEN:
97*5113495bSYour Name pn_enable = 1;
98*5113495bSYour Name pn_size = PN_SIZE_128;
99*5113495bSYour Name break;
100*5113495bSYour Name default:
101*5113495bSYour Name pn_enable = 0;
102*5113495bSYour Name break;
103*5113495bSYour Name }
104*5113495bSYour Name
105*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_CHECK_NEEDED,
106*5113495bSYour Name pn_enable);
107*5113495bSYour Name
108*5113495bSYour Name if (pn_type == HAL_PN_WAPI_EVEN)
109*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
110*5113495bSYour Name PN_SHALL_BE_EVEN, 1);
111*5113495bSYour Name else if (pn_type == HAL_PN_WAPI_UNEVEN)
112*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
113*5113495bSYour Name PN_SHALL_BE_UNEVEN, 1);
114*5113495bSYour Name
115*5113495bSYour Name /*
116*5113495bSYour Name * TODO: Need to check if PN handling in SW needs to be enabled
117*5113495bSYour Name * So far this is not a requirement
118*5113495bSYour Name */
119*5113495bSYour Name
120*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_SIZE,
121*5113495bSYour Name pn_size);
122*5113495bSYour Name
123*5113495bSYour Name /* TODO: Check if RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG need to be set
124*5113495bSYour Name * based on BA window size and/or AMPDU capabilities
125*5113495bSYour Name */
126*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
127*5113495bSYour Name IGNORE_AMPDU_FLAG, 1);
128*5113495bSYour Name
129*5113495bSYour Name if (start_seq <= 0xfff)
130*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SSN,
131*5113495bSYour Name start_seq);
132*5113495bSYour Name
133*5113495bSYour Name /* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
134*5113495bSYour Name * but REO is not delivering packets if we set it to 1. Need to enable
135*5113495bSYour Name * this once the issue is resolved
136*5113495bSYour Name */
137*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SVLD, 0);
138*5113495bSYour Name
139*5113495bSYour Name /* TODO: Check if we should set start PN for WAPI */
140*5113495bSYour Name
141*5113495bSYour Name /* TODO: HW queue descriptors are currently allocated for max BA
142*5113495bSYour Name * window size for all QOS TIDs so that same descriptor can be used
143*5113495bSYour Name * later when ADDBA request is received. This should be changed to
144*5113495bSYour Name * allocate HW queue descriptors based on BA window size being
145*5113495bSYour Name * negotiated (0 for non BA cases), and reallocate when BA window
146*5113495bSYour Name * size changes and also send WMI message to FW to change the REO
147*5113495bSYour Name * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
148*5113495bSYour Name */
149*5113495bSYour Name if (tid == HAL_NON_QOS_TID)
150*5113495bSYour Name return;
151*5113495bSYour Name
152*5113495bSYour Name reo_queue_ext_desc = (uint32_t *)
153*5113495bSYour Name (((struct rx_reo_queue *)reo_queue_desc) + 1);
154*5113495bSYour Name qdf_mem_zero(reo_queue_ext_desc, 3 *
155*5113495bSYour Name sizeof(struct rx_reo_queue_ext));
156*5113495bSYour Name /* Initialize first reo queue extension descriptor */
157*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
158*5113495bSYour Name HAL_DESC_REO_OWNED,
159*5113495bSYour Name HAL_REO_QUEUE_EXT_DESC);
160*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
161*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_ext_desc,
162*5113495bSYour Name UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A,
163*5113495bSYour Name 0xADBEEF);
164*5113495bSYour Name /* Initialize second reo queue extension descriptor */
165*5113495bSYour Name reo_queue_ext_desc = (uint32_t *)
166*5113495bSYour Name (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
167*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
168*5113495bSYour Name HAL_DESC_REO_OWNED,
169*5113495bSYour Name HAL_REO_QUEUE_EXT_DESC);
170*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
171*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_ext_desc,
172*5113495bSYour Name UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A,
173*5113495bSYour Name 0xBDBEEF);
174*5113495bSYour Name /* Initialize third reo queue extension descriptor */
175*5113495bSYour Name reo_queue_ext_desc = (uint32_t *)
176*5113495bSYour Name (((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
177*5113495bSYour Name hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
178*5113495bSYour Name HAL_DESC_REO_OWNED,
179*5113495bSYour Name HAL_REO_QUEUE_EXT_DESC);
180*5113495bSYour Name /* Fixed pattern in reserved bits for debugging */
181*5113495bSYour Name HAL_DESC_SET_FIELD(reo_queue_ext_desc,
182*5113495bSYour Name UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A,
183*5113495bSYour Name 0xCDBEEF);
184*5113495bSYour Name }
185*5113495bSYour Name
186*5113495bSYour Name qdf_export_symbol(hal_reo_qdesc_setup_li);
187*5113495bSYour Name
hal_get_ba_aging_timeout_li(hal_soc_handle_t hal_soc_hdl,uint8_t ac,uint32_t * value)188*5113495bSYour Name void hal_get_ba_aging_timeout_li(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
189*5113495bSYour Name uint32_t *value)
190*5113495bSYour Name {
191*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
192*5113495bSYour Name
193*5113495bSYour Name switch (ac) {
194*5113495bSYour Name case WME_AC_BE:
195*5113495bSYour Name *value = HAL_REG_READ(soc,
196*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
197*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
198*5113495bSYour Name break;
199*5113495bSYour Name case WME_AC_BK:
200*5113495bSYour Name *value = HAL_REG_READ(soc,
201*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
202*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
203*5113495bSYour Name break;
204*5113495bSYour Name case WME_AC_VI:
205*5113495bSYour Name *value = HAL_REG_READ(soc,
206*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
207*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
208*5113495bSYour Name break;
209*5113495bSYour Name case WME_AC_VO:
210*5113495bSYour Name *value = HAL_REG_READ(soc,
211*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
212*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET)) / 1000;
213*5113495bSYour Name break;
214*5113495bSYour Name default:
215*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
216*5113495bSYour Name "Invalid AC: %d\n", ac);
217*5113495bSYour Name }
218*5113495bSYour Name }
219*5113495bSYour Name qdf_export_symbol(hal_get_ba_aging_timeout_li);
220*5113495bSYour Name
hal_set_ba_aging_timeout_li(hal_soc_handle_t hal_soc_hdl,uint8_t ac,uint32_t value)221*5113495bSYour Name void hal_set_ba_aging_timeout_li(hal_soc_handle_t hal_soc_hdl, uint8_t ac,
222*5113495bSYour Name uint32_t value)
223*5113495bSYour Name {
224*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
225*5113495bSYour Name
226*5113495bSYour Name switch (ac) {
227*5113495bSYour Name case WME_AC_BE:
228*5113495bSYour Name HAL_REG_WRITE(soc,
229*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
230*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET),
231*5113495bSYour Name value * 1000);
232*5113495bSYour Name break;
233*5113495bSYour Name case WME_AC_BK:
234*5113495bSYour Name HAL_REG_WRITE(soc,
235*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
236*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET),
237*5113495bSYour Name value * 1000);
238*5113495bSYour Name break;
239*5113495bSYour Name case WME_AC_VI:
240*5113495bSYour Name HAL_REG_WRITE(soc,
241*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
242*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET),
243*5113495bSYour Name value * 1000);
244*5113495bSYour Name break;
245*5113495bSYour Name case WME_AC_VO:
246*5113495bSYour Name HAL_REG_WRITE(soc,
247*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
248*5113495bSYour Name SEQ_WCSS_UMAC_REO_REG_OFFSET),
249*5113495bSYour Name value * 1000);
250*5113495bSYour Name break;
251*5113495bSYour Name default:
252*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
253*5113495bSYour Name "Invalid AC: %d\n", ac);
254*5113495bSYour Name }
255*5113495bSYour Name }
256*5113495bSYour Name qdf_export_symbol(hal_set_ba_aging_timeout_li);
257*5113495bSYour Name
258*5113495bSYour Name static inline void
hal_reo_cmd_set_descr_addr_li(uint32_t * reo_desc,enum hal_reo_cmd_type type,uint32_t paddr_lo,uint8_t paddr_hi)259*5113495bSYour Name hal_reo_cmd_set_descr_addr_li(uint32_t *reo_desc, enum hal_reo_cmd_type type,
260*5113495bSYour Name uint32_t paddr_lo, uint8_t paddr_hi)
261*5113495bSYour Name {
262*5113495bSYour Name switch (type) {
263*5113495bSYour Name case CMD_GET_QUEUE_STATS:
264*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_1,
265*5113495bSYour Name RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
266*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_2,
267*5113495bSYour Name RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
268*5113495bSYour Name break;
269*5113495bSYour Name case CMD_FLUSH_QUEUE:
270*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_1,
271*5113495bSYour Name FLUSH_DESC_ADDR_31_0, paddr_lo);
272*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2,
273*5113495bSYour Name FLUSH_DESC_ADDR_39_32, paddr_hi);
274*5113495bSYour Name break;
275*5113495bSYour Name case CMD_FLUSH_CACHE:
276*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_1,
277*5113495bSYour Name FLUSH_ADDR_31_0, paddr_lo);
278*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
279*5113495bSYour Name FLUSH_ADDR_39_32, paddr_hi);
280*5113495bSYour Name break;
281*5113495bSYour Name case CMD_UPDATE_RX_REO_QUEUE:
282*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_1,
283*5113495bSYour Name RX_REO_QUEUE_DESC_ADDR_31_0, paddr_lo);
284*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
285*5113495bSYour Name RX_REO_QUEUE_DESC_ADDR_39_32, paddr_hi);
286*5113495bSYour Name break;
287*5113495bSYour Name default:
288*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
289*5113495bSYour Name "%s: Invalid REO command type", __func__);
290*5113495bSYour Name break;
291*5113495bSYour Name }
292*5113495bSYour Name }
293*5113495bSYour Name
294*5113495bSYour Name static inline int
hal_reo_cmd_queue_stats_li(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)295*5113495bSYour Name hal_reo_cmd_queue_stats_li(hal_ring_handle_t hal_ring_hdl,
296*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
297*5113495bSYour Name struct hal_reo_cmd_params *cmd)
298*5113495bSYour Name {
299*5113495bSYour Name uint32_t *reo_desc, val;
300*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
301*5113495bSYour Name
302*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
303*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
304*5113495bSYour Name if (!reo_desc) {
305*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
306*5113495bSYour Name "%s: Out of cmd ring entries", __func__);
307*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
308*5113495bSYour Name return -EBUSY;
309*5113495bSYour Name }
310*5113495bSYour Name
311*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_GET_QUEUE_STATS_E,
312*5113495bSYour Name sizeof(struct reo_get_queue_stats));
313*5113495bSYour Name
314*5113495bSYour Name /*
315*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
316*5113495bSYour Name * the field after TLV header
317*5113495bSYour Name */
318*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
319*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
320*5113495bSYour Name sizeof(struct reo_get_queue_stats) -
321*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
322*5113495bSYour Name
323*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
324*5113495bSYour Name REO_STATUS_REQUIRED, cmd->std.need_status);
325*5113495bSYour Name
326*5113495bSYour Name hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_GET_QUEUE_STATS,
327*5113495bSYour Name cmd->std.addr_lo,
328*5113495bSYour Name cmd->std.addr_hi);
329*5113495bSYour Name
330*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_GET_QUEUE_STATS_2, CLEAR_STATS,
331*5113495bSYour Name cmd->u.stats_params.clear);
332*5113495bSYour Name
333*5113495bSYour Name if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_HAL_REO_CMD) == 0) {
334*5113495bSYour Name if (hif_system_pm_state_check(hal_soc->hif_handle)) {
335*5113495bSYour Name hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
336*5113495bSYour Name hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
337*5113495bSYour Name hal_srng_inc_flush_cnt(hal_ring_hdl);
338*5113495bSYour Name } else {
339*5113495bSYour Name hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
340*5113495bSYour Name }
341*5113495bSYour Name
342*5113495bSYour Name hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_HAL_REO_CMD);
343*5113495bSYour Name } else {
344*5113495bSYour Name hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
345*5113495bSYour Name hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
346*5113495bSYour Name hal_srng_inc_flush_cnt(hal_ring_hdl);
347*5113495bSYour Name }
348*5113495bSYour Name
349*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
350*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
351*5113495bSYour Name val);
352*5113495bSYour Name }
353*5113495bSYour Name
354*5113495bSYour Name static inline int
hal_reo_cmd_flush_queue_li(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)355*5113495bSYour Name hal_reo_cmd_flush_queue_li(hal_ring_handle_t hal_ring_hdl,
356*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
357*5113495bSYour Name struct hal_reo_cmd_params *cmd)
358*5113495bSYour Name {
359*5113495bSYour Name uint32_t *reo_desc, val;
360*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
361*5113495bSYour Name
362*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
363*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
364*5113495bSYour Name if (!reo_desc) {
365*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
366*5113495bSYour Name "%s: Out of cmd ring entries", __func__);
367*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
368*5113495bSYour Name return -EBUSY;
369*5113495bSYour Name }
370*5113495bSYour Name
371*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_QUEUE_E,
372*5113495bSYour Name sizeof(struct reo_flush_queue));
373*5113495bSYour Name
374*5113495bSYour Name /*
375*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
376*5113495bSYour Name * the field after TLV header
377*5113495bSYour Name */
378*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
379*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
380*5113495bSYour Name sizeof(struct reo_flush_queue) -
381*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
382*5113495bSYour Name
383*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
384*5113495bSYour Name REO_STATUS_REQUIRED, cmd->std.need_status);
385*5113495bSYour Name
386*5113495bSYour Name hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_FLUSH_QUEUE,
387*5113495bSYour Name cmd->std.addr_lo, cmd->std.addr_hi);
388*5113495bSYour Name
389*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2,
390*5113495bSYour Name BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH,
391*5113495bSYour Name cmd->u.fl_queue_params.block_use_after_flush);
392*5113495bSYour Name
393*5113495bSYour Name if (cmd->u.fl_queue_params.block_use_after_flush) {
394*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_QUEUE_2,
395*5113495bSYour Name BLOCK_RESOURCE_INDEX,
396*5113495bSYour Name cmd->u.fl_queue_params.index);
397*5113495bSYour Name }
398*5113495bSYour Name
399*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
400*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
401*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
402*5113495bSYour Name val);
403*5113495bSYour Name }
404*5113495bSYour Name
405*5113495bSYour Name static inline int
hal_reo_cmd_flush_cache_li(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)406*5113495bSYour Name hal_reo_cmd_flush_cache_li(hal_ring_handle_t hal_ring_hdl,
407*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
408*5113495bSYour Name struct hal_reo_cmd_params *cmd)
409*5113495bSYour Name {
410*5113495bSYour Name uint32_t *reo_desc, val;
411*5113495bSYour Name struct hal_reo_cmd_flush_cache_params *cp;
412*5113495bSYour Name uint8_t index = 0;
413*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
414*5113495bSYour Name
415*5113495bSYour Name cp = &cmd->u.fl_cache_params;
416*5113495bSYour Name
417*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
418*5113495bSYour Name
419*5113495bSYour Name /* We need a cache block resource for this operation, and REO HW has
420*5113495bSYour Name * only 4 such blocking resources. These resources are managed using
421*5113495bSYour Name * reo_res_bitmap, and we return failure if none is available.
422*5113495bSYour Name */
423*5113495bSYour Name if (cp->block_use_after_flush) {
424*5113495bSYour Name index = hal_find_zero_bit(hal_soc->reo_res_bitmap);
425*5113495bSYour Name if (index > 3) {
426*5113495bSYour Name qdf_print("No blocking resource available!");
427*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
428*5113495bSYour Name return -EBUSY;
429*5113495bSYour Name }
430*5113495bSYour Name hal_soc->index = index;
431*5113495bSYour Name }
432*5113495bSYour Name
433*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
434*5113495bSYour Name if (!reo_desc) {
435*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
436*5113495bSYour Name hal_srng_dump(hal_ring_handle_to_hal_srng(hal_ring_hdl));
437*5113495bSYour Name return -EBUSY;
438*5113495bSYour Name }
439*5113495bSYour Name
440*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_CACHE_E,
441*5113495bSYour Name sizeof(struct reo_flush_cache));
442*5113495bSYour Name
443*5113495bSYour Name /*
444*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
445*5113495bSYour Name * the field after TLV header
446*5113495bSYour Name */
447*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
448*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
449*5113495bSYour Name sizeof(struct reo_flush_cache) -
450*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
451*5113495bSYour Name
452*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
453*5113495bSYour Name REO_STATUS_REQUIRED, cmd->std.need_status);
454*5113495bSYour Name
455*5113495bSYour Name hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_FLUSH_CACHE,
456*5113495bSYour Name cmd->std.addr_lo, cmd->std.addr_hi);
457*5113495bSYour Name
458*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
459*5113495bSYour Name FORWARD_ALL_MPDUS_IN_QUEUE, cp->fwd_mpdus_in_queue);
460*5113495bSYour Name
461*5113495bSYour Name /* set it to 0 for now */
462*5113495bSYour Name cp->rel_block_index = 0;
463*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
464*5113495bSYour Name RELEASE_CACHE_BLOCK_INDEX, cp->rel_block_index);
465*5113495bSYour Name
466*5113495bSYour Name if (cp->block_use_after_flush) {
467*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
468*5113495bSYour Name CACHE_BLOCK_RESOURCE_INDEX, index);
469*5113495bSYour Name }
470*5113495bSYour Name
471*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
472*5113495bSYour Name FLUSH_WITHOUT_INVALIDATE, cp->flush_no_inval);
473*5113495bSYour Name
474*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2,
475*5113495bSYour Name BLOCK_CACHE_USAGE_AFTER_FLUSH,
476*5113495bSYour Name cp->block_use_after_flush);
477*5113495bSYour Name
478*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_CACHE_2, FLUSH_ENTIRE_CACHE,
479*5113495bSYour Name cp->flush_entire_cache);
480*5113495bSYour Name
481*5113495bSYour Name if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_HAL_REO_CMD) == 0) {
482*5113495bSYour Name if (hif_system_pm_state_check(hal_soc->hif_handle)) {
483*5113495bSYour Name hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
484*5113495bSYour Name hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
485*5113495bSYour Name hal_srng_inc_flush_cnt(hal_ring_hdl);
486*5113495bSYour Name } else {
487*5113495bSYour Name hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
488*5113495bSYour Name }
489*5113495bSYour Name
490*5113495bSYour Name hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_HAL_REO_CMD);
491*5113495bSYour Name } else {
492*5113495bSYour Name hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
493*5113495bSYour Name hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
494*5113495bSYour Name hal_srng_inc_flush_cnt(hal_ring_hdl);
495*5113495bSYour Name }
496*5113495bSYour Name
497*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
498*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
499*5113495bSYour Name val);
500*5113495bSYour Name }
501*5113495bSYour Name
502*5113495bSYour Name static inline int
hal_reo_cmd_unblock_cache_li(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)503*5113495bSYour Name hal_reo_cmd_unblock_cache_li(hal_ring_handle_t hal_ring_hdl,
504*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
505*5113495bSYour Name struct hal_reo_cmd_params *cmd)
506*5113495bSYour Name
507*5113495bSYour Name {
508*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
509*5113495bSYour Name uint32_t *reo_desc, val;
510*5113495bSYour Name uint8_t index = 0;
511*5113495bSYour Name
512*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
513*5113495bSYour Name
514*5113495bSYour Name if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
515*5113495bSYour Name index = hal_find_one_bit(hal_soc->reo_res_bitmap);
516*5113495bSYour Name if (index > 3) {
517*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
518*5113495bSYour Name qdf_print("No blocking resource to unblock!");
519*5113495bSYour Name return -EBUSY;
520*5113495bSYour Name }
521*5113495bSYour Name }
522*5113495bSYour Name
523*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
524*5113495bSYour Name if (!reo_desc) {
525*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
526*5113495bSYour Name "%s: Out of cmd ring entries", __func__);
527*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
528*5113495bSYour Name return -EBUSY;
529*5113495bSYour Name }
530*5113495bSYour Name
531*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_UNBLOCK_CACHE_E,
532*5113495bSYour Name sizeof(struct reo_unblock_cache));
533*5113495bSYour Name
534*5113495bSYour Name /*
535*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
536*5113495bSYour Name * the field after TLV header
537*5113495bSYour Name */
538*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
539*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
540*5113495bSYour Name sizeof(struct reo_unblock_cache) -
541*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
542*5113495bSYour Name
543*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
544*5113495bSYour Name REO_STATUS_REQUIRED, cmd->std.need_status);
545*5113495bSYour Name
546*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE_1,
547*5113495bSYour Name UNBLOCK_TYPE, cmd->u.unblk_cache_params.type);
548*5113495bSYour Name
549*5113495bSYour Name if (cmd->u.unblk_cache_params.type == UNBLOCK_RES_INDEX) {
550*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UNBLOCK_CACHE_1,
551*5113495bSYour Name CACHE_BLOCK_RESOURCE_INDEX,
552*5113495bSYour Name cmd->u.unblk_cache_params.index);
553*5113495bSYour Name }
554*5113495bSYour Name
555*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
556*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
557*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
558*5113495bSYour Name val);
559*5113495bSYour Name }
560*5113495bSYour Name
561*5113495bSYour Name static inline int
hal_reo_cmd_flush_timeout_list_li(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)562*5113495bSYour Name hal_reo_cmd_flush_timeout_list_li(hal_ring_handle_t hal_ring_hdl,
563*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
564*5113495bSYour Name struct hal_reo_cmd_params *cmd)
565*5113495bSYour Name {
566*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
567*5113495bSYour Name uint32_t *reo_desc, val;
568*5113495bSYour Name
569*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
570*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
571*5113495bSYour Name if (!reo_desc) {
572*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
573*5113495bSYour Name "%s: Out of cmd ring entries", __func__);
574*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
575*5113495bSYour Name return -EBUSY;
576*5113495bSYour Name }
577*5113495bSYour Name
578*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_FLUSH_TIMEOUT_LIST_E,
579*5113495bSYour Name sizeof(struct reo_flush_timeout_list));
580*5113495bSYour Name
581*5113495bSYour Name /*
582*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
583*5113495bSYour Name * the field after TLV header
584*5113495bSYour Name */
585*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
586*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
587*5113495bSYour Name sizeof(struct reo_flush_timeout_list) -
588*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
589*5113495bSYour Name
590*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
591*5113495bSYour Name REO_STATUS_REQUIRED, cmd->std.need_status);
592*5113495bSYour Name
593*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_1, AC_TIMOUT_LIST,
594*5113495bSYour Name cmd->u.fl_tim_list_params.ac_list);
595*5113495bSYour Name
596*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_2,
597*5113495bSYour Name MINIMUM_RELEASE_DESC_COUNT,
598*5113495bSYour Name cmd->u.fl_tim_list_params.min_rel_desc);
599*5113495bSYour Name
600*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_FLUSH_TIMEOUT_LIST_2,
601*5113495bSYour Name MINIMUM_FORWARD_BUF_COUNT,
602*5113495bSYour Name cmd->u.fl_tim_list_params.min_fwd_buf);
603*5113495bSYour Name
604*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
605*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
606*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
607*5113495bSYour Name val);
608*5113495bSYour Name }
609*5113495bSYour Name
610*5113495bSYour Name static inline int
hal_reo_cmd_update_rx_queue_li(hal_ring_handle_t hal_ring_hdl,hal_soc_handle_t hal_soc_hdl,struct hal_reo_cmd_params * cmd)611*5113495bSYour Name hal_reo_cmd_update_rx_queue_li(hal_ring_handle_t hal_ring_hdl,
612*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
613*5113495bSYour Name struct hal_reo_cmd_params *cmd)
614*5113495bSYour Name {
615*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
616*5113495bSYour Name uint32_t *reo_desc, val;
617*5113495bSYour Name struct hal_reo_cmd_update_queue_params *p;
618*5113495bSYour Name
619*5113495bSYour Name p = &cmd->u.upd_queue_params;
620*5113495bSYour Name
621*5113495bSYour Name hal_srng_access_start(hal_soc_hdl, hal_ring_hdl);
622*5113495bSYour Name reo_desc = hal_srng_src_get_next(hal_soc, hal_ring_hdl);
623*5113495bSYour Name if (!reo_desc) {
624*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
625*5113495bSYour Name "%s: Out of cmd ring entries", __func__);
626*5113495bSYour Name hal_srng_access_end(hal_soc, hal_ring_hdl);
627*5113495bSYour Name return -EBUSY;
628*5113495bSYour Name }
629*5113495bSYour Name
630*5113495bSYour Name HAL_SET_TLV_HDR(reo_desc, WIFIREO_UPDATE_RX_REO_QUEUE_E,
631*5113495bSYour Name sizeof(struct reo_update_rx_reo_queue));
632*5113495bSYour Name
633*5113495bSYour Name /*
634*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start from
635*5113495bSYour Name * the field after TLV header
636*5113495bSYour Name */
637*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
638*5113495bSYour Name qdf_mem_zero((reo_desc + NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER),
639*5113495bSYour Name sizeof(struct reo_update_rx_reo_queue) -
640*5113495bSYour Name (NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER << 2));
641*5113495bSYour Name
642*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, UNIFORM_REO_CMD_HEADER_0,
643*5113495bSYour Name REO_STATUS_REQUIRED, cmd->std.need_status);
644*5113495bSYour Name
645*5113495bSYour Name hal_reo_cmd_set_descr_addr_li(reo_desc, CMD_UPDATE_RX_REO_QUEUE,
646*5113495bSYour Name cmd->std.addr_lo, cmd->std.addr_hi);
647*5113495bSYour Name
648*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
649*5113495bSYour Name UPDATE_RECEIVE_QUEUE_NUMBER, p->update_rx_queue_num);
650*5113495bSYour Name
651*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2, UPDATE_VLD,
652*5113495bSYour Name p->update_vld);
653*5113495bSYour Name
654*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
655*5113495bSYour Name UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
656*5113495bSYour Name p->update_assoc_link_desc);
657*5113495bSYour Name
658*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
659*5113495bSYour Name UPDATE_DISABLE_DUPLICATE_DETECTION,
660*5113495bSYour Name p->update_disable_dup_detect);
661*5113495bSYour Name
662*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
663*5113495bSYour Name UPDATE_DISABLE_DUPLICATE_DETECTION,
664*5113495bSYour Name p->update_disable_dup_detect);
665*5113495bSYour Name
666*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
667*5113495bSYour Name UPDATE_SOFT_REORDER_ENABLE,
668*5113495bSYour Name p->update_soft_reorder_enab);
669*5113495bSYour Name
670*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
671*5113495bSYour Name UPDATE_AC, p->update_ac);
672*5113495bSYour Name
673*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
674*5113495bSYour Name UPDATE_BAR, p->update_bar);
675*5113495bSYour Name
676*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
677*5113495bSYour Name UPDATE_BAR, p->update_bar);
678*5113495bSYour Name
679*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
680*5113495bSYour Name UPDATE_RTY, p->update_rty);
681*5113495bSYour Name
682*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
683*5113495bSYour Name UPDATE_CHK_2K_MODE, p->update_chk_2k_mode);
684*5113495bSYour Name
685*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
686*5113495bSYour Name UPDATE_OOR_MODE, p->update_oor_mode);
687*5113495bSYour Name
688*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
689*5113495bSYour Name UPDATE_BA_WINDOW_SIZE, p->update_ba_window_size);
690*5113495bSYour Name
691*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
692*5113495bSYour Name UPDATE_PN_CHECK_NEEDED, p->update_pn_check_needed);
693*5113495bSYour Name
694*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
695*5113495bSYour Name UPDATE_PN_SHALL_BE_EVEN, p->update_pn_even);
696*5113495bSYour Name
697*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
698*5113495bSYour Name UPDATE_PN_SHALL_BE_UNEVEN, p->update_pn_uneven);
699*5113495bSYour Name
700*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
701*5113495bSYour Name UPDATE_PN_HANDLING_ENABLE, p->update_pn_hand_enab);
702*5113495bSYour Name
703*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
704*5113495bSYour Name UPDATE_PN_SIZE, p->update_pn_size);
705*5113495bSYour Name
706*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
707*5113495bSYour Name UPDATE_IGNORE_AMPDU_FLAG, p->update_ignore_ampdu);
708*5113495bSYour Name
709*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
710*5113495bSYour Name UPDATE_SVLD, p->update_svld);
711*5113495bSYour Name
712*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
713*5113495bSYour Name UPDATE_SSN, p->update_ssn);
714*5113495bSYour Name
715*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
716*5113495bSYour Name UPDATE_SEQ_2K_ERROR_DETECTED_FLAG,
717*5113495bSYour Name p->update_seq_2k_err_detect);
718*5113495bSYour Name
719*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
720*5113495bSYour Name UPDATE_PN_VALID, p->update_pn_valid);
721*5113495bSYour Name
722*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_2,
723*5113495bSYour Name UPDATE_PN, p->update_pn);
724*5113495bSYour Name
725*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
726*5113495bSYour Name RECEIVE_QUEUE_NUMBER, p->rx_queue_num);
727*5113495bSYour Name
728*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
729*5113495bSYour Name VLD, p->vld);
730*5113495bSYour Name
731*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
732*5113495bSYour Name ASSOCIATED_LINK_DESCRIPTOR_COUNTER,
733*5113495bSYour Name p->assoc_link_desc);
734*5113495bSYour Name
735*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
736*5113495bSYour Name DISABLE_DUPLICATE_DETECTION, p->disable_dup_detect);
737*5113495bSYour Name
738*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
739*5113495bSYour Name SOFT_REORDER_ENABLE, p->soft_reorder_enab);
740*5113495bSYour Name
741*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3, AC, p->ac);
742*5113495bSYour Name
743*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
744*5113495bSYour Name BAR, p->bar);
745*5113495bSYour Name
746*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
747*5113495bSYour Name CHK_2K_MODE, p->chk_2k_mode);
748*5113495bSYour Name
749*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
750*5113495bSYour Name RTY, p->rty);
751*5113495bSYour Name
752*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
753*5113495bSYour Name OOR_MODE, p->oor_mode);
754*5113495bSYour Name
755*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
756*5113495bSYour Name PN_CHECK_NEEDED, p->pn_check_needed);
757*5113495bSYour Name
758*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
759*5113495bSYour Name PN_SHALL_BE_EVEN, p->pn_even);
760*5113495bSYour Name
761*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
762*5113495bSYour Name PN_SHALL_BE_UNEVEN, p->pn_uneven);
763*5113495bSYour Name
764*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
765*5113495bSYour Name PN_HANDLING_ENABLE, p->pn_hand_enab);
766*5113495bSYour Name
767*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_3,
768*5113495bSYour Name IGNORE_AMPDU_FLAG, p->ignore_ampdu);
769*5113495bSYour Name
770*5113495bSYour Name if (p->ba_window_size < 1)
771*5113495bSYour Name p->ba_window_size = 1;
772*5113495bSYour Name /*
773*5113495bSYour Name * WAR to get 2k exception in Non BA case.
774*5113495bSYour Name * Setting window size to 2 to get 2k jump exception
775*5113495bSYour Name * when we receive aggregates in Non BA case
776*5113495bSYour Name */
777*5113495bSYour Name if (p->ba_window_size == 1)
778*5113495bSYour Name p->ba_window_size++;
779*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
780*5113495bSYour Name BA_WINDOW_SIZE, p->ba_window_size - 1);
781*5113495bSYour Name
782*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
783*5113495bSYour Name PN_SIZE, p->pn_size);
784*5113495bSYour Name
785*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
786*5113495bSYour Name SVLD, p->svld);
787*5113495bSYour Name
788*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
789*5113495bSYour Name SSN, p->ssn);
790*5113495bSYour Name
791*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
792*5113495bSYour Name SEQ_2K_ERROR_DETECTED_FLAG, p->seq_2k_err_detect);
793*5113495bSYour Name
794*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_4,
795*5113495bSYour Name PN_ERROR_DETECTED_FLAG, p->pn_err_detect);
796*5113495bSYour Name
797*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_5,
798*5113495bSYour Name PN_31_0, p->pn_31_0);
799*5113495bSYour Name
800*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_6,
801*5113495bSYour Name PN_63_32, p->pn_63_32);
802*5113495bSYour Name
803*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_7,
804*5113495bSYour Name PN_95_64, p->pn_95_64);
805*5113495bSYour Name
806*5113495bSYour Name HAL_DESC_SET_FIELD(reo_desc, REO_UPDATE_RX_REO_QUEUE_8,
807*5113495bSYour Name PN_127_96, p->pn_127_96);
808*5113495bSYour Name
809*5113495bSYour Name if (hif_rtpm_get(HIF_RTPM_GET_ASYNC, HIF_RTPM_ID_HAL_REO_CMD) == 0) {
810*5113495bSYour Name if (hif_system_pm_state_check(hal_soc->hif_handle)) {
811*5113495bSYour Name hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
812*5113495bSYour Name hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
813*5113495bSYour Name hal_srng_inc_flush_cnt(hal_ring_hdl);
814*5113495bSYour Name } else {
815*5113495bSYour Name hal_srng_access_end(hal_soc_hdl, hal_ring_hdl);
816*5113495bSYour Name }
817*5113495bSYour Name
818*5113495bSYour Name hif_rtpm_put(HIF_RTPM_PUT_ASYNC, HIF_RTPM_ID_HAL_REO_CMD);
819*5113495bSYour Name } else {
820*5113495bSYour Name hal_srng_access_end_reap(hal_soc_hdl, hal_ring_hdl);
821*5113495bSYour Name hal_srng_set_event(hal_ring_hdl, HAL_SRNG_FLUSH_EVENT);
822*5113495bSYour Name hal_srng_inc_flush_cnt(hal_ring_hdl);
823*5113495bSYour Name }
824*5113495bSYour Name
825*5113495bSYour Name val = reo_desc[CMD_HEADER_DW_OFFSET];
826*5113495bSYour Name return HAL_GET_FIELD(UNIFORM_REO_CMD_HEADER_0, REO_CMD_NUMBER,
827*5113495bSYour Name val);
828*5113495bSYour Name }
829*5113495bSYour Name
hal_reo_send_cmd_li(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl,enum hal_reo_cmd_type cmd,void * params)830*5113495bSYour Name int hal_reo_send_cmd_li(hal_soc_handle_t hal_soc_hdl,
831*5113495bSYour Name hal_ring_handle_t hal_ring_hdl,
832*5113495bSYour Name enum hal_reo_cmd_type cmd,
833*5113495bSYour Name void *params)
834*5113495bSYour Name {
835*5113495bSYour Name struct hal_reo_cmd_params *cmd_params =
836*5113495bSYour Name (struct hal_reo_cmd_params *)params;
837*5113495bSYour Name int num = 0;
838*5113495bSYour Name
839*5113495bSYour Name switch (cmd) {
840*5113495bSYour Name case CMD_GET_QUEUE_STATS:
841*5113495bSYour Name num = hal_reo_cmd_queue_stats_li(hal_ring_hdl,
842*5113495bSYour Name hal_soc_hdl, cmd_params);
843*5113495bSYour Name break;
844*5113495bSYour Name case CMD_FLUSH_QUEUE:
845*5113495bSYour Name num = hal_reo_cmd_flush_queue_li(hal_ring_hdl,
846*5113495bSYour Name hal_soc_hdl, cmd_params);
847*5113495bSYour Name break;
848*5113495bSYour Name case CMD_FLUSH_CACHE:
849*5113495bSYour Name num = hal_reo_cmd_flush_cache_li(hal_ring_hdl,
850*5113495bSYour Name hal_soc_hdl, cmd_params);
851*5113495bSYour Name break;
852*5113495bSYour Name case CMD_UNBLOCK_CACHE:
853*5113495bSYour Name num = hal_reo_cmd_unblock_cache_li(hal_ring_hdl,
854*5113495bSYour Name hal_soc_hdl, cmd_params);
855*5113495bSYour Name break;
856*5113495bSYour Name case CMD_FLUSH_TIMEOUT_LIST:
857*5113495bSYour Name num = hal_reo_cmd_flush_timeout_list_li(hal_ring_hdl,
858*5113495bSYour Name hal_soc_hdl,
859*5113495bSYour Name cmd_params);
860*5113495bSYour Name break;
861*5113495bSYour Name case CMD_UPDATE_RX_REO_QUEUE:
862*5113495bSYour Name num = hal_reo_cmd_update_rx_queue_li(hal_ring_hdl,
863*5113495bSYour Name hal_soc_hdl, cmd_params);
864*5113495bSYour Name break;
865*5113495bSYour Name default:
866*5113495bSYour Name hal_err("Invalid REO command type: %d", cmd);
867*5113495bSYour Name return -EINVAL;
868*5113495bSYour Name };
869*5113495bSYour Name
870*5113495bSYour Name return num;
871*5113495bSYour Name }
872*5113495bSYour Name
873*5113495bSYour Name void
hal_reo_queue_stats_status_li(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)874*5113495bSYour Name hal_reo_queue_stats_status_li(hal_ring_desc_t ring_desc,
875*5113495bSYour Name void *st_handle,
876*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
877*5113495bSYour Name {
878*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
879*5113495bSYour Name struct hal_reo_queue_status *st =
880*5113495bSYour Name (struct hal_reo_queue_status *)st_handle;
881*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
882*5113495bSYour Name uint32_t val;
883*5113495bSYour Name
884*5113495bSYour Name /*
885*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
886*5113495bSYour Name * from the field after TLV header
887*5113495bSYour Name */
888*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
889*5113495bSYour Name
890*5113495bSYour Name /* header */
891*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
892*5113495bSYour Name &(st->header), hal_soc);
893*5113495bSYour Name
894*5113495bSYour Name /* SSN */
895*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2, SSN)];
896*5113495bSYour Name st->ssn = HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_2, SSN, val);
897*5113495bSYour Name
898*5113495bSYour Name /* current index */
899*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2,
900*5113495bSYour Name CURRENT_INDEX)];
901*5113495bSYour Name st->curr_idx =
902*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_2,
903*5113495bSYour Name CURRENT_INDEX, val);
904*5113495bSYour Name
905*5113495bSYour Name /* PN bits */
906*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_3,
907*5113495bSYour Name PN_31_0)];
908*5113495bSYour Name st->pn_31_0 =
909*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_3,
910*5113495bSYour Name PN_31_0, val);
911*5113495bSYour Name
912*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_4,
913*5113495bSYour Name PN_63_32)];
914*5113495bSYour Name st->pn_63_32 =
915*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_4,
916*5113495bSYour Name PN_63_32, val);
917*5113495bSYour Name
918*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_5,
919*5113495bSYour Name PN_95_64)];
920*5113495bSYour Name st->pn_95_64 =
921*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_5,
922*5113495bSYour Name PN_95_64, val);
923*5113495bSYour Name
924*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_6,
925*5113495bSYour Name PN_127_96)];
926*5113495bSYour Name st->pn_127_96 =
927*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_6,
928*5113495bSYour Name PN_127_96, val);
929*5113495bSYour Name
930*5113495bSYour Name /* timestamps */
931*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_7,
932*5113495bSYour Name LAST_RX_ENQUEUE_TIMESTAMP)];
933*5113495bSYour Name st->last_rx_enq_tstamp =
934*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_7,
935*5113495bSYour Name LAST_RX_ENQUEUE_TIMESTAMP, val);
936*5113495bSYour Name
937*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_8,
938*5113495bSYour Name LAST_RX_DEQUEUE_TIMESTAMP)];
939*5113495bSYour Name st->last_rx_deq_tstamp =
940*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_8,
941*5113495bSYour Name LAST_RX_DEQUEUE_TIMESTAMP, val);
942*5113495bSYour Name
943*5113495bSYour Name /* rx bitmap */
944*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_9,
945*5113495bSYour Name RX_BITMAP_31_0)];
946*5113495bSYour Name st->rx_bitmap_31_0 =
947*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_9,
948*5113495bSYour Name RX_BITMAP_31_0, val);
949*5113495bSYour Name
950*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_10,
951*5113495bSYour Name RX_BITMAP_63_32)];
952*5113495bSYour Name st->rx_bitmap_63_32 =
953*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_10,
954*5113495bSYour Name RX_BITMAP_63_32, val);
955*5113495bSYour Name
956*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_11,
957*5113495bSYour Name RX_BITMAP_95_64)];
958*5113495bSYour Name st->rx_bitmap_95_64 =
959*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_11,
960*5113495bSYour Name RX_BITMAP_95_64, val);
961*5113495bSYour Name
962*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_12,
963*5113495bSYour Name RX_BITMAP_127_96)];
964*5113495bSYour Name st->rx_bitmap_127_96 =
965*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_12,
966*5113495bSYour Name RX_BITMAP_127_96, val);
967*5113495bSYour Name
968*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_13,
969*5113495bSYour Name RX_BITMAP_159_128)];
970*5113495bSYour Name st->rx_bitmap_159_128 =
971*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_13,
972*5113495bSYour Name RX_BITMAP_159_128, val);
973*5113495bSYour Name
974*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_14,
975*5113495bSYour Name RX_BITMAP_191_160)];
976*5113495bSYour Name st->rx_bitmap_191_160 =
977*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_14,
978*5113495bSYour Name RX_BITMAP_191_160, val);
979*5113495bSYour Name
980*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_15,
981*5113495bSYour Name RX_BITMAP_223_192)];
982*5113495bSYour Name st->rx_bitmap_223_192 =
983*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_15,
984*5113495bSYour Name RX_BITMAP_223_192, val);
985*5113495bSYour Name
986*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_16,
987*5113495bSYour Name RX_BITMAP_255_224)];
988*5113495bSYour Name st->rx_bitmap_255_224 =
989*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_16,
990*5113495bSYour Name RX_BITMAP_255_224, val);
991*5113495bSYour Name
992*5113495bSYour Name /* various counts */
993*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_17,
994*5113495bSYour Name CURRENT_MPDU_COUNT)];
995*5113495bSYour Name st->curr_mpdu_cnt =
996*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_17,
997*5113495bSYour Name CURRENT_MPDU_COUNT, val);
998*5113495bSYour Name
999*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_17,
1000*5113495bSYour Name CURRENT_MSDU_COUNT)];
1001*5113495bSYour Name st->curr_msdu_cnt =
1002*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_17,
1003*5113495bSYour Name CURRENT_MSDU_COUNT, val);
1004*5113495bSYour Name
1005*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18,
1006*5113495bSYour Name TIMEOUT_COUNT)];
1007*5113495bSYour Name st->fwd_timeout_cnt =
1008*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18,
1009*5113495bSYour Name TIMEOUT_COUNT, val);
1010*5113495bSYour Name
1011*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18,
1012*5113495bSYour Name FORWARD_DUE_TO_BAR_COUNT)];
1013*5113495bSYour Name st->fwd_bar_cnt =
1014*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18,
1015*5113495bSYour Name FORWARD_DUE_TO_BAR_COUNT, val);
1016*5113495bSYour Name
1017*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_18,
1018*5113495bSYour Name DUPLICATE_COUNT)];
1019*5113495bSYour Name st->dup_cnt =
1020*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_18,
1021*5113495bSYour Name DUPLICATE_COUNT, val);
1022*5113495bSYour Name
1023*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_19,
1024*5113495bSYour Name FRAMES_IN_ORDER_COUNT)];
1025*5113495bSYour Name st->frms_in_order_cnt =
1026*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_19,
1027*5113495bSYour Name FRAMES_IN_ORDER_COUNT, val);
1028*5113495bSYour Name
1029*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_19,
1030*5113495bSYour Name BAR_RECEIVED_COUNT)];
1031*5113495bSYour Name st->bar_rcvd_cnt =
1032*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_19,
1033*5113495bSYour Name BAR_RECEIVED_COUNT, val);
1034*5113495bSYour Name
1035*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_20,
1036*5113495bSYour Name MPDU_FRAMES_PROCESSED_COUNT)];
1037*5113495bSYour Name st->mpdu_frms_cnt =
1038*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_20,
1039*5113495bSYour Name MPDU_FRAMES_PROCESSED_COUNT, val);
1040*5113495bSYour Name
1041*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_21,
1042*5113495bSYour Name MSDU_FRAMES_PROCESSED_COUNT)];
1043*5113495bSYour Name st->msdu_frms_cnt =
1044*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_21,
1045*5113495bSYour Name MSDU_FRAMES_PROCESSED_COUNT, val);
1046*5113495bSYour Name
1047*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_22,
1048*5113495bSYour Name TOTAL_PROCESSED_BYTE_COUNT)];
1049*5113495bSYour Name st->total_cnt =
1050*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_22,
1051*5113495bSYour Name TOTAL_PROCESSED_BYTE_COUNT, val);
1052*5113495bSYour Name
1053*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23,
1054*5113495bSYour Name LATE_RECEIVE_MPDU_COUNT)];
1055*5113495bSYour Name st->late_recv_mpdu_cnt =
1056*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23,
1057*5113495bSYour Name LATE_RECEIVE_MPDU_COUNT, val);
1058*5113495bSYour Name
1059*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23,
1060*5113495bSYour Name WINDOW_JUMP_2K)];
1061*5113495bSYour Name st->win_jump_2k =
1062*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23,
1063*5113495bSYour Name WINDOW_JUMP_2K, val);
1064*5113495bSYour Name
1065*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_23,
1066*5113495bSYour Name HOLE_COUNT)];
1067*5113495bSYour Name st->hole_cnt =
1068*5113495bSYour Name HAL_GET_FIELD(REO_GET_QUEUE_STATS_STATUS_23,
1069*5113495bSYour Name HOLE_COUNT, val);
1070*5113495bSYour Name }
1071*5113495bSYour Name
1072*5113495bSYour Name void
hal_reo_flush_queue_status_li(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1073*5113495bSYour Name hal_reo_flush_queue_status_li(hal_ring_desc_t ring_desc,
1074*5113495bSYour Name void *st_handle,
1075*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1076*5113495bSYour Name {
1077*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1078*5113495bSYour Name struct hal_reo_flush_queue_status *st =
1079*5113495bSYour Name (struct hal_reo_flush_queue_status *)st_handle;
1080*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
1081*5113495bSYour Name uint32_t val;
1082*5113495bSYour Name
1083*5113495bSYour Name /*
1084*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1085*5113495bSYour Name * from the field after TLV header
1086*5113495bSYour Name */
1087*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
1088*5113495bSYour Name
1089*5113495bSYour Name /* header */
1090*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
1091*5113495bSYour Name &(st->header), hal_soc);
1092*5113495bSYour Name
1093*5113495bSYour Name /* error bit */
1094*5113495bSYour Name val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS_2,
1095*5113495bSYour Name ERROR_DETECTED)];
1096*5113495bSYour Name st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS_2, ERROR_DETECTED,
1097*5113495bSYour Name val);
1098*5113495bSYour Name }
1099*5113495bSYour Name
1100*5113495bSYour Name void
hal_reo_flush_cache_status_li(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1101*5113495bSYour Name hal_reo_flush_cache_status_li(hal_ring_desc_t ring_desc,
1102*5113495bSYour Name void *st_handle,
1103*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1104*5113495bSYour Name {
1105*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1106*5113495bSYour Name struct hal_reo_flush_cache_status *st =
1107*5113495bSYour Name (struct hal_reo_flush_cache_status *)st_handle;
1108*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
1109*5113495bSYour Name uint32_t val;
1110*5113495bSYour Name
1111*5113495bSYour Name /*
1112*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1113*5113495bSYour Name * from the field after TLV header
1114*5113495bSYour Name */
1115*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
1116*5113495bSYour Name
1117*5113495bSYour Name /* header */
1118*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
1119*5113495bSYour Name &(st->header), hal_soc);
1120*5113495bSYour Name
1121*5113495bSYour Name /* error bit */
1122*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
1123*5113495bSYour Name ERROR_DETECTED)];
1124*5113495bSYour Name st->error = HAL_GET_FIELD(REO_FLUSH_QUEUE_STATUS_2, ERROR_DETECTED,
1125*5113495bSYour Name val);
1126*5113495bSYour Name
1127*5113495bSYour Name /* block error */
1128*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
1129*5113495bSYour Name BLOCK_ERROR_DETAILS)];
1130*5113495bSYour Name st->block_error = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
1131*5113495bSYour Name BLOCK_ERROR_DETAILS,
1132*5113495bSYour Name val);
1133*5113495bSYour Name if (!st->block_error)
1134*5113495bSYour Name qdf_set_bit(hal_soc->index,
1135*5113495bSYour Name (unsigned long *)&hal_soc->reo_res_bitmap);
1136*5113495bSYour Name
1137*5113495bSYour Name /* cache flush status */
1138*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
1139*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_HIT)];
1140*5113495bSYour Name st->cache_flush_status = HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
1141*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_HIT,
1142*5113495bSYour Name val);
1143*5113495bSYour Name
1144*5113495bSYour Name /* cache flush descriptor type */
1145*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
1146*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE)];
1147*5113495bSYour Name st->cache_flush_status_desc_type =
1148*5113495bSYour Name HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
1149*5113495bSYour Name CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE,
1150*5113495bSYour Name val);
1151*5113495bSYour Name
1152*5113495bSYour Name /* cache flush count */
1153*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
1154*5113495bSYour Name CACHE_CONTROLLER_FLUSH_COUNT)];
1155*5113495bSYour Name st->cache_flush_cnt =
1156*5113495bSYour Name HAL_GET_FIELD(REO_FLUSH_CACHE_STATUS_2,
1157*5113495bSYour Name CACHE_CONTROLLER_FLUSH_COUNT,
1158*5113495bSYour Name val);
1159*5113495bSYour Name }
1160*5113495bSYour Name
1161*5113495bSYour Name void
hal_reo_unblock_cache_status_li(hal_ring_desc_t ring_desc,hal_soc_handle_t hal_soc_hdl,void * st_handle)1162*5113495bSYour Name hal_reo_unblock_cache_status_li(hal_ring_desc_t ring_desc,
1163*5113495bSYour Name hal_soc_handle_t hal_soc_hdl,
1164*5113495bSYour Name void *st_handle)
1165*5113495bSYour Name {
1166*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1167*5113495bSYour Name struct hal_reo_unblk_cache_status *st =
1168*5113495bSYour Name (struct hal_reo_unblk_cache_status *)st_handle;
1169*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
1170*5113495bSYour Name uint32_t val;
1171*5113495bSYour Name
1172*5113495bSYour Name /*
1173*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1174*5113495bSYour Name * from the field after TLV header
1175*5113495bSYour Name */
1176*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
1177*5113495bSYour Name
1178*5113495bSYour Name /* header */
1179*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
1180*5113495bSYour Name &st->header, hal_soc);
1181*5113495bSYour Name
1182*5113495bSYour Name /* error bit */
1183*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2,
1184*5113495bSYour Name ERROR_DETECTED)];
1185*5113495bSYour Name st->error = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS_2,
1186*5113495bSYour Name ERROR_DETECTED,
1187*5113495bSYour Name val);
1188*5113495bSYour Name
1189*5113495bSYour Name /* unblock type */
1190*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2,
1191*5113495bSYour Name UNBLOCK_TYPE)];
1192*5113495bSYour Name st->unblock_type = HAL_GET_FIELD(REO_UNBLOCK_CACHE_STATUS_2,
1193*5113495bSYour Name UNBLOCK_TYPE,
1194*5113495bSYour Name val);
1195*5113495bSYour Name
1196*5113495bSYour Name if (!st->error && (st->unblock_type == UNBLOCK_RES_INDEX))
1197*5113495bSYour Name qdf_clear_bit(hal_soc->index,
1198*5113495bSYour Name (unsigned long *)&hal_soc->reo_res_bitmap);
1199*5113495bSYour Name }
1200*5113495bSYour Name
hal_reo_flush_timeout_list_status_li(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1201*5113495bSYour Name void hal_reo_flush_timeout_list_status_li(hal_ring_desc_t ring_desc,
1202*5113495bSYour Name void *st_handle,
1203*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1204*5113495bSYour Name {
1205*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1206*5113495bSYour Name struct hal_reo_flush_timeout_list_status *st =
1207*5113495bSYour Name (struct hal_reo_flush_timeout_list_status *)st_handle;
1208*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
1209*5113495bSYour Name uint32_t val;
1210*5113495bSYour Name
1211*5113495bSYour Name /*
1212*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1213*5113495bSYour Name * from the field after TLV header
1214*5113495bSYour Name */
1215*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
1216*5113495bSYour Name
1217*5113495bSYour Name /* header */
1218*5113495bSYour Name hal_reo_status_get_header(ring_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
1219*5113495bSYour Name &(st->header), hal_soc);
1220*5113495bSYour Name
1221*5113495bSYour Name /* error bit */
1222*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
1223*5113495bSYour Name ERROR_DETECTED)];
1224*5113495bSYour Name st->error = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
1225*5113495bSYour Name ERROR_DETECTED,
1226*5113495bSYour Name val);
1227*5113495bSYour Name
1228*5113495bSYour Name /* list empty */
1229*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
1230*5113495bSYour Name TIMOUT_LIST_EMPTY)];
1231*5113495bSYour Name st->list_empty = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
1232*5113495bSYour Name TIMOUT_LIST_EMPTY,
1233*5113495bSYour Name val);
1234*5113495bSYour Name
1235*5113495bSYour Name /* release descriptor count */
1236*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
1237*5113495bSYour Name RELEASE_DESC_COUNT)];
1238*5113495bSYour Name st->rel_desc_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
1239*5113495bSYour Name RELEASE_DESC_COUNT,
1240*5113495bSYour Name val);
1241*5113495bSYour Name
1242*5113495bSYour Name /* forward buf count */
1243*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
1244*5113495bSYour Name FORWARD_BUF_COUNT)];
1245*5113495bSYour Name st->fwd_buf_cnt = HAL_GET_FIELD(REO_FLUSH_TIMEOUT_LIST_STATUS_3,
1246*5113495bSYour Name FORWARD_BUF_COUNT,
1247*5113495bSYour Name val);
1248*5113495bSYour Name }
1249*5113495bSYour Name
hal_reo_desc_thres_reached_status_li(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1250*5113495bSYour Name void hal_reo_desc_thres_reached_status_li(hal_ring_desc_t ring_desc,
1251*5113495bSYour Name void *st_handle,
1252*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1253*5113495bSYour Name {
1254*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1255*5113495bSYour Name struct hal_reo_desc_thres_reached_status *st =
1256*5113495bSYour Name (struct hal_reo_desc_thres_reached_status *)st_handle;
1257*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
1258*5113495bSYour Name uint32_t val;
1259*5113495bSYour Name
1260*5113495bSYour Name /*
1261*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1262*5113495bSYour Name * from the field after TLV header
1263*5113495bSYour Name */
1264*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
1265*5113495bSYour Name
1266*5113495bSYour Name /* header */
1267*5113495bSYour Name hal_reo_status_get_header(ring_desc,
1268*5113495bSYour Name HAL_REO_DESC_THRES_STATUS_TLV,
1269*5113495bSYour Name &(st->header), hal_soc);
1270*5113495bSYour Name
1271*5113495bSYour Name /* threshold index */
1272*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(
1273*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2,
1274*5113495bSYour Name THRESHOLD_INDEX)];
1275*5113495bSYour Name st->thres_index = HAL_GET_FIELD(
1276*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2,
1277*5113495bSYour Name THRESHOLD_INDEX,
1278*5113495bSYour Name val);
1279*5113495bSYour Name
1280*5113495bSYour Name /* link desc counters */
1281*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(
1282*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3,
1283*5113495bSYour Name LINK_DESCRIPTOR_COUNTER0)];
1284*5113495bSYour Name st->link_desc_counter0 = HAL_GET_FIELD(
1285*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3,
1286*5113495bSYour Name LINK_DESCRIPTOR_COUNTER0,
1287*5113495bSYour Name val);
1288*5113495bSYour Name
1289*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(
1290*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4,
1291*5113495bSYour Name LINK_DESCRIPTOR_COUNTER1)];
1292*5113495bSYour Name st->link_desc_counter1 = HAL_GET_FIELD(
1293*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4,
1294*5113495bSYour Name LINK_DESCRIPTOR_COUNTER1,
1295*5113495bSYour Name val);
1296*5113495bSYour Name
1297*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(
1298*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5,
1299*5113495bSYour Name LINK_DESCRIPTOR_COUNTER2)];
1300*5113495bSYour Name st->link_desc_counter2 = HAL_GET_FIELD(
1301*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5,
1302*5113495bSYour Name LINK_DESCRIPTOR_COUNTER2,
1303*5113495bSYour Name val);
1304*5113495bSYour Name
1305*5113495bSYour Name val = reo_desc[HAL_OFFSET_DW(
1306*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6,
1307*5113495bSYour Name LINK_DESCRIPTOR_COUNTER_SUM)];
1308*5113495bSYour Name st->link_desc_counter_sum = HAL_GET_FIELD(
1309*5113495bSYour Name REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6,
1310*5113495bSYour Name LINK_DESCRIPTOR_COUNTER_SUM,
1311*5113495bSYour Name val);
1312*5113495bSYour Name }
1313*5113495bSYour Name
1314*5113495bSYour Name void
hal_reo_rx_update_queue_status_li(hal_ring_desc_t ring_desc,void * st_handle,hal_soc_handle_t hal_soc_hdl)1315*5113495bSYour Name hal_reo_rx_update_queue_status_li(hal_ring_desc_t ring_desc,
1316*5113495bSYour Name void *st_handle,
1317*5113495bSYour Name hal_soc_handle_t hal_soc_hdl)
1318*5113495bSYour Name {
1319*5113495bSYour Name struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
1320*5113495bSYour Name struct hal_reo_update_rx_queue_status *st =
1321*5113495bSYour Name (struct hal_reo_update_rx_queue_status *)st_handle;
1322*5113495bSYour Name uint32_t *reo_desc = (uint32_t *)ring_desc;
1323*5113495bSYour Name
1324*5113495bSYour Name /*
1325*5113495bSYour Name * Offsets of descriptor fields defined in HW headers start
1326*5113495bSYour Name * from the field after TLV header
1327*5113495bSYour Name */
1328*5113495bSYour Name reo_desc += (sizeof(struct tlv_32_hdr) >> 2);
1329*5113495bSYour Name
1330*5113495bSYour Name /* header */
1331*5113495bSYour Name hal_reo_status_get_header(ring_desc,
1332*5113495bSYour Name HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
1333*5113495bSYour Name &(st->header), hal_soc);
1334*5113495bSYour Name }
1335*5113495bSYour Name
hal_get_tlv_hdr_size_li(void)1336*5113495bSYour Name uint8_t hal_get_tlv_hdr_size_li(void)
1337*5113495bSYour Name {
1338*5113495bSYour Name return sizeof(struct tlv_32_hdr);
1339*5113495bSYour Name }
1340*5113495bSYour Name
hal_rx_get_qdesc_addr_li(uint8_t * dst_ring_desc,uint8_t * buf)1341*5113495bSYour Name uint64_t hal_rx_get_qdesc_addr_li(uint8_t *dst_ring_desc, uint8_t *buf)
1342*5113495bSYour Name {
1343*5113495bSYour Name uint8_t *dst_qdesc_addr = dst_ring_desc +
1344*5113495bSYour Name REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
1345*5113495bSYour Name
1346*5113495bSYour Name return *(uint64_t *)dst_qdesc_addr;
1347*5113495bSYour Name }
1348