1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 20 ((uint8_t *)(link_desc_va) + \ 21 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET) 22 23 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 24 ((uint8_t *)(msdu0) + \ 25 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET) 26 27 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 28 ((uint8_t *)(ent_ring_desc) + \ 29 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 30 31 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 32 ((uint8_t *)(dst_ring_desc) + \ 33 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET) 34 35 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ 36 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) 37 38 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ 39 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) 40 41 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 42 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) 43 44 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ 45 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) 46 47 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ 48 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) 49 50 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ 51 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) 52 53 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 54 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) 55 56 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ 57 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_10, SW_PEER_ID) 58 59 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 60 do { \ 61 (reg_val) &= \ 62 ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 63 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 64 (reg_val) |= \ 65 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 66 AGING_LIST_ENABLE, 1) |\ 67 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 68 AGING_FLUSH_ENABLE, 1);\ 69 HAL_REG_WRITE((soc), \ 70 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 71 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 72 (reg_val)); \ 73 (reg_val) = \ 74 HAL_REG_READ((soc), \ 75 HWIO_REO_R0_MISC_CTL_ADDR( \ 76 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 77 (reg_val) &= \ 78 ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 79 (reg_val) |= \ 80 HAL_SM(HWIO_REO_R0_MISC_CTL, \ 81 FRAGMENT_DEST_RING, \ 82 (reo_params)->frag_dst_ring); \ 83 HAL_REG_WRITE((soc), \ 84 HWIO_REO_R0_MISC_CTL_ADDR( \ 85 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 86 (reg_val)); \ 87 (reg_val) = \ 88 HAL_REG_READ((soc), \ 89 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 90 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \ 91 (reg_val) &= \ 92 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \ 93 (reg_val) |= \ 94 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \ 95 DEST_RING_ALT_MAPPING_0, \ 96 (reo_params)->alt_dst_ind_0); \ 97 HAL_REG_WRITE((soc), \ 98 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \ 99 SEQ_WCSS_UMAC_REO_REG_OFFSET), \ 100 (reg_val)); \ 101 } while (0) 102 103 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 104 ((struct rx_msdu_desc_info *) \ 105 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \ 106 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 107 108 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 109 ((struct rx_msdu_details *) \ 110 _OFFSET_TO_BYTE_PTR((link_desc),\ 111 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET)) 112 113 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ 114 (_HAL_MS( \ 115 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ 116 msdu_end_tlv.rx_msdu_end), \ 117 RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ 118 RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ 119 RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) 120 121 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ 122 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 123 RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ 124 RX_MSDU_END_10_FIRST_MSDU_MASK, \ 125 RX_MSDU_END_10_FIRST_MSDU_LSB)) 126 127 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ 128 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 129 RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ 130 RX_MSDU_END_10_LAST_MSDU_MASK, \ 131 RX_MSDU_END_10_LAST_MSDU_LSB)) 132 133 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ 134 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 135 RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ 136 RX_MSDU_END_10_SA_IS_VALID_MASK, \ 137 RX_MSDU_END_10_SA_IS_VALID_LSB)) 138 139 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ 140 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 141 RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ 142 RX_MSDU_END_10_DA_IS_VALID_MASK, \ 143 RX_MSDU_END_10_DA_IS_VALID_LSB)) 144 145 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ 146 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 147 RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ 148 RX_MSDU_END_10_DA_IS_MCBC_MASK, \ 149 RX_MSDU_END_10_DA_IS_MCBC_LSB)) 150 151 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ 152 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 153 RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ 154 RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ 155 RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) 156 157 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ 158 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 159 RX_MSDU_END_11_SA_IDX_OFFSET)), \ 160 RX_MSDU_END_11_SA_IDX_MASK, \ 161 RX_MSDU_END_11_SA_IDX_LSB)) 162 163 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ 164 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 165 RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ 166 RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ 167 RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) 168 169 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ 170 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 171 RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ 172 RX_MSDU_END_14_CCE_METADATA_MASK, \ 173 RX_MSDU_END_14_CCE_METADATA_LSB)) 174 175 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ 176 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 177 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ 178 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ 179 RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) 180 181 #define HAL_RX_MPDU_SW_FRAME_GROUP_ID_GET(_rx_mpdu_info) \ 182 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 183 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), \ 184 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, \ 185 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)) \ 186 187 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ 188 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 189 RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ 190 RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ 191 RX_MPDU_INFO_10_SW_PEER_ID_LSB)) 192 193 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ 194 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 195 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ 196 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ 197 RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) 198 199 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ 200 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 201 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ 202 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ 203 RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) 204 205 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ 206 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 207 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ 208 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ 209 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) 210 211 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ 212 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 213 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ 214 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ 215 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) 216 217 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ 218 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 219 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ 220 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ 221 RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) 222 223 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ 224 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 225 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ 226 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ 227 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) 228 229 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ 230 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 231 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ 232 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ 233 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) 234 235 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ 236 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 237 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ 238 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ 239 RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) 240 241 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ 242 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 243 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ 244 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ 245 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) 246 247 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ 248 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 249 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ 250 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ 251 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) 252 253 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ 254 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 255 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ 256 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ 257 RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) 258 259 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ 260 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 261 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ 262 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ 263 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) 264 265 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ 266 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 267 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ 268 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ 269 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) 270 271 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ 272 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 273 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 274 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 275 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 276 277 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \ 278 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 279 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ 280 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ 281 RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) 282 283 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ 284 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 285 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ 286 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ 287 RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) 288 289 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ 290 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 291 RX_MPDU_INFO_11_FR_DS_OFFSET)), \ 292 RX_MPDU_INFO_11_FR_DS_MASK, \ 293 RX_MPDU_INFO_11_FR_DS_LSB)) 294 295 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ 296 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 297 RX_MPDU_INFO_11_TO_DS_OFFSET)), \ 298 RX_MPDU_INFO_11_TO_DS_MASK, \ 299 RX_MPDU_INFO_11_TO_DS_LSB)) 300 301 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ 302 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 303 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ 304 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ 305 RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) 306 307 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ 308 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 309 RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ 310 RX_MPDU_INFO_3_PN_31_0_MASK, \ 311 RX_MPDU_INFO_3_PN_31_0_LSB)) 312 313 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ 314 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 315 RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ 316 RX_MPDU_INFO_4_PN_63_32_MASK, \ 317 RX_MPDU_INFO_4_PN_63_32_LSB)) 318 319 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ 320 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 321 RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ 322 RX_MPDU_INFO_5_PN_95_64_MASK, \ 323 RX_MPDU_INFO_5_PN_95_64_LSB)) 324 325 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ 326 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ 327 RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ 328 RX_MPDU_INFO_6_PN_127_96_MASK, \ 329 RX_MPDU_INFO_6_PN_127_96_LSB)) 330 331 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ 332 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 333 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ 334 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ 335 RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) 336 337 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ 338 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 339 RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ 340 RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ 341 RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) 342 343 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ 344 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 345 RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ 346 RX_MSDU_END_12_FLOW_IDX_MASK, \ 347 RX_MSDU_END_12_FLOW_IDX_LSB)) 348 349 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ 350 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ 351 RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ 352 RX_MSDU_END_13_FSE_METADATA_MASK, \ 353 RX_MSDU_END_13_FSE_METADATA_LSB)) 354 355 #define HAL_RX_MPDU_GET_PHY_PPDU_ID(_rx_mpdu_info) \ 356 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 357 RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET)), \ 358 RX_MPDU_INFO_9_PHY_PPDU_ID_MASK, \ 359 RX_MPDU_INFO_9_PHY_PPDU_ID_LSB)) \ 360 361 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ 362 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ 363 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ 364 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ 365 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) 366 367 #ifdef GET_MSDU_AGGREGATION 368 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\ 369 {\ 370 struct rx_msdu_end *rx_msdu_end;\ 371 bool first_msdu, last_msdu; \ 372 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\ 373 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, FIRST_MSDU);\ 374 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_10, LAST_MSDU);\ 375 if (first_msdu && last_msdu)\ 376 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\ 377 else\ 378 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \ 379 } \ 380 381 #else 382 #define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs) 383 #endif 384 385 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ 386 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ 387 RX_MPDU_INFO_7_TID_OFFSET)), \ 388 RX_MPDU_INFO_7_TID_MASK, \ 389 RX_MPDU_INFO_7_TID_LSB)) 390 391 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ 392 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ 393 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ 394 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ 395 RX_MSDU_START_5_RECEPTION_TYPE_LSB)) 396 397 #define HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent_desc) \ 398 (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc, \ 399 REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET)), \ 400 REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK, \ 401 REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB)) 402