1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any
6*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above
7*5113495bSYour Name * copyright notice and this permission notice appear in all copies.
8*5113495bSYour Name *
9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
16*5113495bSYour Name */
17*5113495bSYour Name #include "qdf_types.h"
18*5113495bSYour Name #include "qdf_util.h"
19*5113495bSYour Name #include "qdf_mem.h"
20*5113495bSYour Name #include "qdf_nbuf.h"
21*5113495bSYour Name #include "qdf_module.h"
22*5113495bSYour Name
23*5113495bSYour Name #include "target_type.h"
24*5113495bSYour Name #include "wcss_version.h"
25*5113495bSYour Name
26*5113495bSYour Name #include "hal_be_hw_headers.h"
27*5113495bSYour Name #include "hal_internal.h"
28*5113495bSYour Name #include "hal_api.h"
29*5113495bSYour Name #include "hal_flow.h"
30*5113495bSYour Name #include "rx_flow_search_entry.h"
31*5113495bSYour Name #include "hal_rx_flow_info.h"
32*5113495bSYour Name #include "hal_be_api.h"
33*5113495bSYour Name #include "tcl_entrance_from_ppe_ring.h"
34*5113495bSYour Name #include "sw_monitor_ring.h"
35*5113495bSYour Name #include "wcss_seq_hwioreg_umac.h"
36*5113495bSYour Name #include "wfss_ce_reg_seq_hwioreg.h"
37*5113495bSYour Name #include <uniform_reo_status_header.h>
38*5113495bSYour Name #include <wbm_release_ring_tx.h>
39*5113495bSYour Name #include <phyrx_location.h>
40*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \
41*5113495bSYour Name defined(WLAN_PKT_CAPTURE_RX_2_0)
42*5113495bSYour Name #include <mon_ingress_ring.h>
43*5113495bSYour Name #include <mon_destination_ring.h>
44*5113495bSYour Name #endif
45*5113495bSYour Name #include "rx_reo_queue_1k.h"
46*5113495bSYour Name
47*5113495bSYour Name #include <hal_be_rx.h>
48*5113495bSYour Name
49*5113495bSYour Name #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
50*5113495bSYour Name RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
51*5113495bSYour Name #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
52*5113495bSYour Name RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
53*5113495bSYour Name #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
54*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
55*5113495bSYour Name #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
56*5113495bSYour Name RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
57*5113495bSYour Name #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
58*5113495bSYour Name REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
59*5113495bSYour Name #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
60*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER
61*5113495bSYour Name #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
62*5113495bSYour Name STATUS_HEADER_TIMESTAMP
63*5113495bSYour Name #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
64*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
65*5113495bSYour Name #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
66*5113495bSYour Name RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
67*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
68*5113495bSYour Name TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
69*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
70*5113495bSYour Name TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
71*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
72*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
73*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
74*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
75*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
76*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
77*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
78*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
79*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
80*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
81*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
82*5113495bSYour Name BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
83*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
84*5113495bSYour Name BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
85*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
86*5113495bSYour Name BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
87*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
88*5113495bSYour Name BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
89*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
90*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
91*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
92*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
93*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
94*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
95*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
96*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
97*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
98*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
99*5113495bSYour Name
100*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0)
101*5113495bSYour Name #include "hal_be_api_mon.h"
102*5113495bSYour Name #endif
103*5113495bSYour Name
104*5113495bSYour Name #define CMEM_REG_BASE 0x00100000
105*5113495bSYour Name
106*5113495bSYour Name /* For Berryllium sw2rxdma ring size increased to 20 bits */
107*5113495bSYour Name #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
108*5113495bSYour Name
109*5113495bSYour Name #include "hal_5332_rx.h"
110*5113495bSYour Name #include "hal_5332_tx.h"
111*5113495bSYour Name #include "hal_be_rx_tlv.h"
112*5113495bSYour Name #include <hal_be_generic_api.h>
113*5113495bSYour Name
114*5113495bSYour Name
115*5113495bSYour Name /**
116*5113495bSYour Name * hal_read_pmm_scratch_reg_5332() - API to read PMM Scratch register
117*5113495bSYour Name *
118*5113495bSYour Name * @soc: HAL soc
119*5113495bSYour Name * @reg_enum: Enum of the scratch register
120*5113495bSYour Name *
121*5113495bSYour Name * Return: uint32_t
122*5113495bSYour Name */
123*5113495bSYour Name static inline
hal_read_pmm_scratch_reg_5332(struct hal_soc * soc,enum hal_scratch_reg_enum reg_enum)124*5113495bSYour Name uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc,
125*5113495bSYour Name enum hal_scratch_reg_enum reg_enum)
126*5113495bSYour Name {
127*5113495bSYour Name uint32_t val = 0;
128*5113495bSYour Name
129*5113495bSYour Name pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val,
130*5113495bSYour Name soc->dev_base_addr_pmm);
131*5113495bSYour Name return val;
132*5113495bSYour Name }
133*5113495bSYour Name
134*5113495bSYour Name /**
135*5113495bSYour Name * hal_get_tsf2_scratch_reg_qca5332() - API to read tsf2 scratch register
136*5113495bSYour Name *
137*5113495bSYour Name * @hal_soc_hdl: HAL soc context
138*5113495bSYour Name * @mac_id: mac id
139*5113495bSYour Name * @value: Pointer to update tsf2 value
140*5113495bSYour Name *
141*5113495bSYour Name * Return: void
142*5113495bSYour Name */
hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,uint8_t mac_id,uint64_t * value)143*5113495bSYour Name static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
144*5113495bSYour Name uint8_t mac_id, uint64_t *value)
145*5113495bSYour Name {
146*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
147*5113495bSYour Name uint32_t offset_lo, offset_hi;
148*5113495bSYour Name enum hal_scratch_reg_enum enum_lo, enum_hi;
149*5113495bSYour Name
150*5113495bSYour Name hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
151*5113495bSYour Name
152*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg_5332(soc,
153*5113495bSYour Name enum_lo);
154*5113495bSYour Name
155*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg_5332(soc,
156*5113495bSYour Name enum_hi);
157*5113495bSYour Name
158*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
159*5113495bSYour Name }
160*5113495bSYour Name
161*5113495bSYour Name /**
162*5113495bSYour Name * hal_get_tqm_scratch_reg_qca5332() - API to read tqm scratch register
163*5113495bSYour Name *
164*5113495bSYour Name * @hal_soc_hdl: HAL soc context
165*5113495bSYour Name * @value: Pointer to update tqm value
166*5113495bSYour Name *
167*5113495bSYour Name * Return: void
168*5113495bSYour Name */
hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,uint64_t * value)169*5113495bSYour Name static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
170*5113495bSYour Name uint64_t *value)
171*5113495bSYour Name {
172*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
173*5113495bSYour Name uint32_t offset_lo, offset_hi;
174*5113495bSYour Name
175*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg_5332(soc,
176*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_LO_US);
177*5113495bSYour Name
178*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg_5332(soc,
179*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_HI_US);
180*5113495bSYour Name
181*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
182*5113495bSYour Name }
183*5113495bSYour Name
184*5113495bSYour Name #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
185*5113495bSYour Name #define HAL_PPE_VP_ENTRIES_MAX 32
186*5113495bSYour Name /**
187*5113495bSYour Name * hal_get_link_desc_size_5332() - API to get the link desc size
188*5113495bSYour Name *
189*5113495bSYour Name * Return: uint32_t
190*5113495bSYour Name */
hal_get_link_desc_size_5332(void)191*5113495bSYour Name static uint32_t hal_get_link_desc_size_5332(void)
192*5113495bSYour Name {
193*5113495bSYour Name return LINK_DESC_SIZE;
194*5113495bSYour Name }
195*5113495bSYour Name
196*5113495bSYour Name /**
197*5113495bSYour Name * hal_rx_get_tlv_5332() - API to get the tlv
198*5113495bSYour Name *
199*5113495bSYour Name * @rx_tlv: TLV data extracted from the rx packet
200*5113495bSYour Name * Return: uint8_t
201*5113495bSYour Name */
hal_rx_get_tlv_5332(void * rx_tlv)202*5113495bSYour Name static uint8_t hal_rx_get_tlv_5332(void *rx_tlv)
203*5113495bSYour Name {
204*5113495bSYour Name return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
205*5113495bSYour Name }
206*5113495bSYour Name
207*5113495bSYour Name /**
208*5113495bSYour Name * hal_rx_wbm_err_msdu_continuation_get_5332() - API to check if WBM
209*5113495bSYour Name * msdu continuation bit is set
210*5113495bSYour Name *
211*5113495bSYour Name * @wbm_desc: wbm release ring descriptor
212*5113495bSYour Name *
213*5113495bSYour Name * Return: true if msdu continuation bit is set.
214*5113495bSYour Name */
hal_rx_wbm_err_msdu_continuation_get_5332(void * wbm_desc)215*5113495bSYour Name uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc)
216*5113495bSYour Name {
217*5113495bSYour Name uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
218*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
219*5113495bSYour Name
220*5113495bSYour Name return (comp_desc &
221*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
222*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
223*5113495bSYour Name }
224*5113495bSYour Name
225*5113495bSYour Name /**
226*5113495bSYour Name * hal_rx_proc_phyrx_other_receive_info_tlv_5332() - API to get tlv info
227*5113495bSYour Name * @rx_tlv_hdr: start address of rx_pkt_tlvs
228*5113495bSYour Name * @ppdu_info_hdl: PPDU info handle to fill
229*5113495bSYour Name *
230*5113495bSYour Name * Return: uint32_t
231*5113495bSYour Name */
232*5113495bSYour Name static inline
hal_rx_proc_phyrx_other_receive_info_tlv_5332(void * rx_tlv_hdr,void * ppdu_info_hdl)233*5113495bSYour Name void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr,
234*5113495bSYour Name void *ppdu_info_hdl)
235*5113495bSYour Name {
236*5113495bSYour Name uint32_t tlv_tag, tlv_len;
237*5113495bSYour Name uint32_t temp_len, other_tlv_len, other_tlv_tag;
238*5113495bSYour Name void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
239*5113495bSYour Name void *other_tlv_hdr = NULL;
240*5113495bSYour Name void *other_tlv = NULL;
241*5113495bSYour Name
242*5113495bSYour Name tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
243*5113495bSYour Name tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
244*5113495bSYour Name temp_len = 0;
245*5113495bSYour Name
246*5113495bSYour Name other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
247*5113495bSYour Name other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
248*5113495bSYour Name other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
249*5113495bSYour Name
250*5113495bSYour Name temp_len += other_tlv_len;
251*5113495bSYour Name other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
252*5113495bSYour Name
253*5113495bSYour Name switch (other_tlv_tag) {
254*5113495bSYour Name default:
255*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
256*5113495bSYour Name "%s unhandled TLV type: %d, TLV len:%d",
257*5113495bSYour Name __func__, other_tlv_tag, other_tlv_len);
258*5113495bSYour Name break;
259*5113495bSYour Name }
260*5113495bSYour Name }
261*5113495bSYour Name
262*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
263*5113495bSYour Name static inline
hal_rx_get_bb_info_5332(void * rx_tlv,void * ppdu_info_hdl)264*5113495bSYour Name void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl)
265*5113495bSYour Name {
266*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
267*5113495bSYour Name
268*5113495bSYour Name ppdu_info->cfr_info.bb_captured_channel =
269*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
270*5113495bSYour Name
271*5113495bSYour Name ppdu_info->cfr_info.bb_captured_timeout =
272*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
273*5113495bSYour Name
274*5113495bSYour Name ppdu_info->cfr_info.bb_captured_reason =
275*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
276*5113495bSYour Name }
277*5113495bSYour Name
278*5113495bSYour Name static inline
hal_rx_get_rtt_info_5332(void * rx_tlv,void * ppdu_info_hdl)279*5113495bSYour Name void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl)
280*5113495bSYour Name {
281*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
282*5113495bSYour Name
283*5113495bSYour Name ppdu_info->cfr_info.rx_location_info_valid =
284*5113495bSYour Name HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
285*5113495bSYour Name RX_LOCATION_INFO_VALID);
286*5113495bSYour Name
287*5113495bSYour Name ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
288*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
289*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
290*5113495bSYour Name RTT_CHE_BUFFER_POINTER_LOW32);
291*5113495bSYour Name
292*5113495bSYour Name ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
293*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
294*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
295*5113495bSYour Name RTT_CHE_BUFFER_POINTER_HIGH8);
296*5113495bSYour Name
297*5113495bSYour Name ppdu_info->cfr_info.chan_capture_status =
298*5113495bSYour Name HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
299*5113495bSYour Name
300*5113495bSYour Name ppdu_info->cfr_info.rx_start_ts =
301*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
302*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
303*5113495bSYour Name RX_START_TS);
304*5113495bSYour Name
305*5113495bSYour Name ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
306*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
307*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
308*5113495bSYour Name RTT_CFO_MEASUREMENT);
309*5113495bSYour Name
310*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info0 =
311*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
312*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
313*5113495bSYour Name GAIN_CHAIN0);
314*5113495bSYour Name
315*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info0 |=
316*5113495bSYour Name (((uint32_t)HAL_RX_GET_64(rx_tlv,
317*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
318*5113495bSYour Name GAIN_CHAIN1)) << 16);
319*5113495bSYour Name
320*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info1 =
321*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
322*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
323*5113495bSYour Name GAIN_CHAIN2);
324*5113495bSYour Name
325*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info1 |=
326*5113495bSYour Name (((uint32_t)HAL_RX_GET_64(rx_tlv,
327*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
328*5113495bSYour Name GAIN_CHAIN3)) << 16);
329*5113495bSYour Name
330*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info2 = 0;
331*5113495bSYour Name
332*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info3 = 0;
333*5113495bSYour Name
334*5113495bSYour Name ppdu_info->cfr_info.mcs_rate =
335*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
336*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
337*5113495bSYour Name RTT_MCS_RATE);
338*5113495bSYour Name
339*5113495bSYour Name ppdu_info->cfr_info.gi_type =
340*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
341*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
342*5113495bSYour Name RTT_GI_TYPE);
343*5113495bSYour Name }
344*5113495bSYour Name #endif
345*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
346*5113495bSYour Name /**
347*5113495bSYour Name * hal_rx_dump_mpdu_start_tlv_5332() - dump RX mpdu_start TLV in structured
348*5113495bSYour Name * human readable format.
349*5113495bSYour Name * @mpdustart: pointer the rx_attention TLV in pkt.
350*5113495bSYour Name * @dbg_level: log level.
351*5113495bSYour Name *
352*5113495bSYour Name * Return: void
353*5113495bSYour Name */
hal_rx_dump_mpdu_start_tlv_5332(void * mpdustart,uint8_t dbg_level)354*5113495bSYour Name static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
355*5113495bSYour Name uint8_t dbg_level)
356*5113495bSYour Name {
357*5113495bSYour Name struct rx_mpdu_start_compact *mpdu_info =
358*5113495bSYour Name (struct rx_mpdu_start_compact *)mpdustart;
359*5113495bSYour Name
360*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
361*5113495bSYour Name "rx_mpdu_start tlv (1/5) - "
362*5113495bSYour Name "rx_reo_queue_desc_addr_39_32 :%x"
363*5113495bSYour Name "receive_queue_number:%x "
364*5113495bSYour Name "pre_delim_err_warning:%x "
365*5113495bSYour Name "first_delim_err:%x "
366*5113495bSYour Name "pn_31_0:%x "
367*5113495bSYour Name "pn_63_32:%x "
368*5113495bSYour Name "pn_95_64:%x ",
369*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_39_32,
370*5113495bSYour Name mpdu_info->receive_queue_number,
371*5113495bSYour Name mpdu_info->pre_delim_err_warning,
372*5113495bSYour Name mpdu_info->first_delim_err,
373*5113495bSYour Name mpdu_info->pn_31_0,
374*5113495bSYour Name mpdu_info->pn_63_32,
375*5113495bSYour Name mpdu_info->pn_95_64);
376*5113495bSYour Name
377*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
378*5113495bSYour Name "rx_mpdu_start tlv (2/5) - "
379*5113495bSYour Name "ast_index:%x "
380*5113495bSYour Name "sw_peer_id:%x "
381*5113495bSYour Name "mpdu_frame_control_valid:%x "
382*5113495bSYour Name "mpdu_duration_valid:%x "
383*5113495bSYour Name "mac_addr_ad1_valid:%x "
384*5113495bSYour Name "mac_addr_ad2_valid:%x "
385*5113495bSYour Name "mac_addr_ad3_valid:%x "
386*5113495bSYour Name "mac_addr_ad4_valid:%x "
387*5113495bSYour Name "mpdu_sequence_control_valid :%x"
388*5113495bSYour Name "mpdu_qos_control_valid:%x "
389*5113495bSYour Name "mpdu_ht_control_valid:%x "
390*5113495bSYour Name "frame_encryption_info_valid :%x",
391*5113495bSYour Name mpdu_info->ast_index,
392*5113495bSYour Name mpdu_info->sw_peer_id,
393*5113495bSYour Name mpdu_info->mpdu_frame_control_valid,
394*5113495bSYour Name mpdu_info->mpdu_duration_valid,
395*5113495bSYour Name mpdu_info->mac_addr_ad1_valid,
396*5113495bSYour Name mpdu_info->mac_addr_ad2_valid,
397*5113495bSYour Name mpdu_info->mac_addr_ad3_valid,
398*5113495bSYour Name mpdu_info->mac_addr_ad4_valid,
399*5113495bSYour Name mpdu_info->mpdu_sequence_control_valid,
400*5113495bSYour Name mpdu_info->mpdu_qos_control_valid,
401*5113495bSYour Name mpdu_info->mpdu_ht_control_valid,
402*5113495bSYour Name mpdu_info->frame_encryption_info_valid);
403*5113495bSYour Name
404*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
405*5113495bSYour Name "rx_mpdu_start tlv (3/5) - "
406*5113495bSYour Name "mpdu_fragment_number:%x "
407*5113495bSYour Name "more_fragment_flag:%x "
408*5113495bSYour Name "fr_ds:%x "
409*5113495bSYour Name "to_ds:%x "
410*5113495bSYour Name "encrypted:%x "
411*5113495bSYour Name "mpdu_retry:%x "
412*5113495bSYour Name "mpdu_sequence_number:%x ",
413*5113495bSYour Name mpdu_info->mpdu_fragment_number,
414*5113495bSYour Name mpdu_info->more_fragment_flag,
415*5113495bSYour Name mpdu_info->fr_ds,
416*5113495bSYour Name mpdu_info->to_ds,
417*5113495bSYour Name mpdu_info->encrypted,
418*5113495bSYour Name mpdu_info->mpdu_retry,
419*5113495bSYour Name mpdu_info->mpdu_sequence_number);
420*5113495bSYour Name
421*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
422*5113495bSYour Name "rx_mpdu_start tlv (4/5) - "
423*5113495bSYour Name "mpdu_frame_control_field:%x "
424*5113495bSYour Name "mpdu_duration_field:%x ",
425*5113495bSYour Name mpdu_info->mpdu_frame_control_field,
426*5113495bSYour Name mpdu_info->mpdu_duration_field);
427*5113495bSYour Name
428*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
429*5113495bSYour Name "rx_mpdu_start tlv (5/5) - "
430*5113495bSYour Name "mac_addr_ad1_31_0:%x "
431*5113495bSYour Name "mac_addr_ad1_47_32:%x "
432*5113495bSYour Name "mac_addr_ad2_15_0:%x "
433*5113495bSYour Name "mac_addr_ad2_47_16:%x "
434*5113495bSYour Name "mac_addr_ad3_31_0:%x "
435*5113495bSYour Name "mac_addr_ad3_47_32:%x "
436*5113495bSYour Name "mpdu_sequence_control_field :%x",
437*5113495bSYour Name mpdu_info->mac_addr_ad1_31_0,
438*5113495bSYour Name mpdu_info->mac_addr_ad1_47_32,
439*5113495bSYour Name mpdu_info->mac_addr_ad2_15_0,
440*5113495bSYour Name mpdu_info->mac_addr_ad2_47_16,
441*5113495bSYour Name mpdu_info->mac_addr_ad3_31_0,
442*5113495bSYour Name mpdu_info->mac_addr_ad3_47_32,
443*5113495bSYour Name mpdu_info->mpdu_sequence_control_field);
444*5113495bSYour Name }
445*5113495bSYour Name
446*5113495bSYour Name /**
447*5113495bSYour Name * hal_rx_dump_msdu_end_tlv_5332() - dump RX msdu_end TLV in structured
448*5113495bSYour Name * human readable format.
449*5113495bSYour Name * @msduend: pointer the msdu_end TLV in pkt.
450*5113495bSYour Name * @dbg_level: log level.
451*5113495bSYour Name *
452*5113495bSYour Name * Return: void
453*5113495bSYour Name */
hal_rx_dump_msdu_end_tlv_5332(void * msduend,uint8_t dbg_level)454*5113495bSYour Name static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
455*5113495bSYour Name uint8_t dbg_level)
456*5113495bSYour Name {
457*5113495bSYour Name struct rx_msdu_end_compact *msdu_end =
458*5113495bSYour Name (struct rx_msdu_end_compact *)msduend;
459*5113495bSYour Name
460*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
461*5113495bSYour Name "rx_msdu_end tlv - "
462*5113495bSYour Name "key_id_octet: %d "
463*5113495bSYour Name "tcp_udp_chksum: %d "
464*5113495bSYour Name "sa_idx_timeout: %d "
465*5113495bSYour Name "da_idx_timeout: %d "
466*5113495bSYour Name "msdu_limit_error: %d "
467*5113495bSYour Name "flow_idx_timeout: %d "
468*5113495bSYour Name "flow_idx_invalid: %d "
469*5113495bSYour Name "wifi_parser_error: %d "
470*5113495bSYour Name "sa_is_valid: %d "
471*5113495bSYour Name "da_is_valid: %d "
472*5113495bSYour Name "da_is_mcbc: %d "
473*5113495bSYour Name "tkip_mic_err: %d "
474*5113495bSYour Name "l3_header_padding: %d "
475*5113495bSYour Name "first_msdu: %d "
476*5113495bSYour Name "last_msdu: %d "
477*5113495bSYour Name "sa_idx: %d "
478*5113495bSYour Name "msdu_drop: %d "
479*5113495bSYour Name "reo_destination_indication: %d "
480*5113495bSYour Name "flow_idx: %d "
481*5113495bSYour Name "fse_metadata: %d "
482*5113495bSYour Name "cce_metadata: %d "
483*5113495bSYour Name "sa_sw_peer_id: %d ",
484*5113495bSYour Name msdu_end->key_id_octet,
485*5113495bSYour Name msdu_end->tcp_udp_chksum,
486*5113495bSYour Name msdu_end->sa_idx_timeout,
487*5113495bSYour Name msdu_end->da_idx_timeout,
488*5113495bSYour Name msdu_end->msdu_limit_error,
489*5113495bSYour Name msdu_end->flow_idx_timeout,
490*5113495bSYour Name msdu_end->flow_idx_invalid,
491*5113495bSYour Name msdu_end->wifi_parser_error,
492*5113495bSYour Name msdu_end->sa_is_valid,
493*5113495bSYour Name msdu_end->da_is_valid,
494*5113495bSYour Name msdu_end->da_is_mcbc,
495*5113495bSYour Name msdu_end->tkip_mic_err,
496*5113495bSYour Name msdu_end->l3_header_padding,
497*5113495bSYour Name msdu_end->first_msdu,
498*5113495bSYour Name msdu_end->last_msdu,
499*5113495bSYour Name msdu_end->sa_idx,
500*5113495bSYour Name msdu_end->msdu_drop,
501*5113495bSYour Name msdu_end->reo_destination_indication,
502*5113495bSYour Name msdu_end->flow_idx,
503*5113495bSYour Name msdu_end->fse_metadata,
504*5113495bSYour Name msdu_end->cce_metadata,
505*5113495bSYour Name msdu_end->sa_sw_peer_id);
506*5113495bSYour Name }
507*5113495bSYour Name #else
hal_rx_dump_mpdu_start_tlv_5332(void * mpdustart,uint8_t dbg_level)508*5113495bSYour Name static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
509*5113495bSYour Name uint8_t dbg_level)
510*5113495bSYour Name {
511*5113495bSYour Name struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
512*5113495bSYour Name struct rx_mpdu_info *mpdu_info =
513*5113495bSYour Name (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
514*5113495bSYour Name
515*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
516*5113495bSYour Name "rx_mpdu_start tlv (1/5) - "
517*5113495bSYour Name "rx_reo_queue_desc_addr_31_0 :%x"
518*5113495bSYour Name "rx_reo_queue_desc_addr_39_32 :%x"
519*5113495bSYour Name "receive_queue_number:%x "
520*5113495bSYour Name "pre_delim_err_warning:%x "
521*5113495bSYour Name "first_delim_err:%x "
522*5113495bSYour Name "reserved_2a:%x "
523*5113495bSYour Name "pn_31_0:%x "
524*5113495bSYour Name "pn_63_32:%x "
525*5113495bSYour Name "pn_95_64:%x "
526*5113495bSYour Name "pn_127_96:%x "
527*5113495bSYour Name "epd_en:%x "
528*5113495bSYour Name "all_frames_shall_be_encrypted :%x"
529*5113495bSYour Name "encrypt_type:%x "
530*5113495bSYour Name "wep_key_width_for_variable_key :%x"
531*5113495bSYour Name "mesh_sta:%x "
532*5113495bSYour Name "bssid_hit:%x "
533*5113495bSYour Name "bssid_number:%x "
534*5113495bSYour Name "tid:%x "
535*5113495bSYour Name "reserved_7a:%x ",
536*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_31_0,
537*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_39_32,
538*5113495bSYour Name mpdu_info->receive_queue_number,
539*5113495bSYour Name mpdu_info->pre_delim_err_warning,
540*5113495bSYour Name mpdu_info->first_delim_err,
541*5113495bSYour Name mpdu_info->reserved_2a,
542*5113495bSYour Name mpdu_info->pn_31_0,
543*5113495bSYour Name mpdu_info->pn_63_32,
544*5113495bSYour Name mpdu_info->pn_95_64,
545*5113495bSYour Name mpdu_info->pn_127_96,
546*5113495bSYour Name mpdu_info->epd_en,
547*5113495bSYour Name mpdu_info->all_frames_shall_be_encrypted,
548*5113495bSYour Name mpdu_info->encrypt_type,
549*5113495bSYour Name mpdu_info->wep_key_width_for_variable_key,
550*5113495bSYour Name mpdu_info->mesh_sta,
551*5113495bSYour Name mpdu_info->bssid_hit,
552*5113495bSYour Name mpdu_info->bssid_number,
553*5113495bSYour Name mpdu_info->tid,
554*5113495bSYour Name mpdu_info->reserved_7a);
555*5113495bSYour Name
556*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
557*5113495bSYour Name "rx_mpdu_start tlv (2/5) - "
558*5113495bSYour Name "ast_index:%x "
559*5113495bSYour Name "sw_peer_id:%x "
560*5113495bSYour Name "mpdu_frame_control_valid:%x "
561*5113495bSYour Name "mpdu_duration_valid:%x "
562*5113495bSYour Name "mac_addr_ad1_valid:%x "
563*5113495bSYour Name "mac_addr_ad2_valid:%x "
564*5113495bSYour Name "mac_addr_ad3_valid:%x "
565*5113495bSYour Name "mac_addr_ad4_valid:%x "
566*5113495bSYour Name "mpdu_sequence_control_valid :%x"
567*5113495bSYour Name "mpdu_qos_control_valid:%x "
568*5113495bSYour Name "mpdu_ht_control_valid:%x "
569*5113495bSYour Name "frame_encryption_info_valid :%x",
570*5113495bSYour Name mpdu_info->ast_index,
571*5113495bSYour Name mpdu_info->sw_peer_id,
572*5113495bSYour Name mpdu_info->mpdu_frame_control_valid,
573*5113495bSYour Name mpdu_info->mpdu_duration_valid,
574*5113495bSYour Name mpdu_info->mac_addr_ad1_valid,
575*5113495bSYour Name mpdu_info->mac_addr_ad2_valid,
576*5113495bSYour Name mpdu_info->mac_addr_ad3_valid,
577*5113495bSYour Name mpdu_info->mac_addr_ad4_valid,
578*5113495bSYour Name mpdu_info->mpdu_sequence_control_valid,
579*5113495bSYour Name mpdu_info->mpdu_qos_control_valid,
580*5113495bSYour Name mpdu_info->mpdu_ht_control_valid,
581*5113495bSYour Name mpdu_info->frame_encryption_info_valid);
582*5113495bSYour Name
583*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
584*5113495bSYour Name "rx_mpdu_start tlv (3/5) - "
585*5113495bSYour Name "mpdu_fragment_number:%x "
586*5113495bSYour Name "more_fragment_flag:%x "
587*5113495bSYour Name "reserved_11a:%x "
588*5113495bSYour Name "fr_ds:%x "
589*5113495bSYour Name "to_ds:%x "
590*5113495bSYour Name "encrypted:%x "
591*5113495bSYour Name "mpdu_retry:%x "
592*5113495bSYour Name "mpdu_sequence_number:%x ",
593*5113495bSYour Name mpdu_info->mpdu_fragment_number,
594*5113495bSYour Name mpdu_info->more_fragment_flag,
595*5113495bSYour Name mpdu_info->reserved_11a,
596*5113495bSYour Name mpdu_info->fr_ds,
597*5113495bSYour Name mpdu_info->to_ds,
598*5113495bSYour Name mpdu_info->encrypted,
599*5113495bSYour Name mpdu_info->mpdu_retry,
600*5113495bSYour Name mpdu_info->mpdu_sequence_number);
601*5113495bSYour Name
602*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
603*5113495bSYour Name "rx_mpdu_start tlv (4/5) - "
604*5113495bSYour Name "mpdu_frame_control_field:%x "
605*5113495bSYour Name "mpdu_duration_field:%x ",
606*5113495bSYour Name mpdu_info->mpdu_frame_control_field,
607*5113495bSYour Name mpdu_info->mpdu_duration_field);
608*5113495bSYour Name
609*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
610*5113495bSYour Name "rx_mpdu_start tlv (5/5) - "
611*5113495bSYour Name "mac_addr_ad1_31_0:%x "
612*5113495bSYour Name "mac_addr_ad1_47_32:%x "
613*5113495bSYour Name "mac_addr_ad2_15_0:%x "
614*5113495bSYour Name "mac_addr_ad2_47_16:%x "
615*5113495bSYour Name "mac_addr_ad3_31_0:%x "
616*5113495bSYour Name "mac_addr_ad3_47_32:%x "
617*5113495bSYour Name "mpdu_sequence_control_field :%x"
618*5113495bSYour Name "mac_addr_ad4_31_0:%x "
619*5113495bSYour Name "mac_addr_ad4_47_32:%x "
620*5113495bSYour Name "mpdu_qos_control_field:%x ",
621*5113495bSYour Name mpdu_info->mac_addr_ad1_31_0,
622*5113495bSYour Name mpdu_info->mac_addr_ad1_47_32,
623*5113495bSYour Name mpdu_info->mac_addr_ad2_15_0,
624*5113495bSYour Name mpdu_info->mac_addr_ad2_47_16,
625*5113495bSYour Name mpdu_info->mac_addr_ad3_31_0,
626*5113495bSYour Name mpdu_info->mac_addr_ad3_47_32,
627*5113495bSYour Name mpdu_info->mpdu_sequence_control_field,
628*5113495bSYour Name mpdu_info->mac_addr_ad4_31_0,
629*5113495bSYour Name mpdu_info->mac_addr_ad4_47_32,
630*5113495bSYour Name mpdu_info->mpdu_qos_control_field);
631*5113495bSYour Name }
632*5113495bSYour Name
hal_rx_dump_msdu_end_tlv_5332(void * msduend,uint8_t dbg_level)633*5113495bSYour Name static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
634*5113495bSYour Name uint8_t dbg_level)
635*5113495bSYour Name {
636*5113495bSYour Name struct rx_msdu_end *msdu_end =
637*5113495bSYour Name (struct rx_msdu_end *)msduend;
638*5113495bSYour Name
639*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
640*5113495bSYour Name "rx_msdu_end tlv - "
641*5113495bSYour Name "key_id_octet: %d "
642*5113495bSYour Name "cce_super_rule: %d "
643*5113495bSYour Name "cce_classify_not_done_truncat: %d "
644*5113495bSYour Name "cce_classify_not_done_cce_dis: %d "
645*5113495bSYour Name "rule_indication_31_0: %d "
646*5113495bSYour Name "tcp_udp_chksum: %d "
647*5113495bSYour Name "sa_idx_timeout: %d "
648*5113495bSYour Name "da_idx_timeout: %d "
649*5113495bSYour Name "msdu_limit_error: %d "
650*5113495bSYour Name "flow_idx_timeout: %d "
651*5113495bSYour Name "flow_idx_invalid: %d "
652*5113495bSYour Name "wifi_parser_error: %d "
653*5113495bSYour Name "sa_is_valid: %d "
654*5113495bSYour Name "da_is_valid: %d "
655*5113495bSYour Name "da_is_mcbc: %d "
656*5113495bSYour Name "tkip_mic_err: %d "
657*5113495bSYour Name "l3_header_padding: %d "
658*5113495bSYour Name "first_msdu: %d "
659*5113495bSYour Name "last_msdu: %d "
660*5113495bSYour Name "sa_idx: %d "
661*5113495bSYour Name "msdu_drop: %d "
662*5113495bSYour Name "reo_destination_indication: %d "
663*5113495bSYour Name "flow_idx: %d "
664*5113495bSYour Name "fse_metadata: %d "
665*5113495bSYour Name "cce_metadata: %d "
666*5113495bSYour Name "sa_sw_peer_id: %d ",
667*5113495bSYour Name msdu_end->key_id_octet,
668*5113495bSYour Name msdu_end->cce_super_rule,
669*5113495bSYour Name msdu_end->cce_classify_not_done_truncate,
670*5113495bSYour Name msdu_end->cce_classify_not_done_cce_dis,
671*5113495bSYour Name msdu_end->rule_indication_31_0,
672*5113495bSYour Name msdu_end->tcp_udp_chksum,
673*5113495bSYour Name msdu_end->sa_idx_timeout,
674*5113495bSYour Name msdu_end->da_idx_timeout,
675*5113495bSYour Name msdu_end->msdu_limit_error,
676*5113495bSYour Name msdu_end->flow_idx_timeout,
677*5113495bSYour Name msdu_end->flow_idx_invalid,
678*5113495bSYour Name msdu_end->wifi_parser_error,
679*5113495bSYour Name msdu_end->sa_is_valid,
680*5113495bSYour Name msdu_end->da_is_valid,
681*5113495bSYour Name msdu_end->da_is_mcbc,
682*5113495bSYour Name msdu_end->tkip_mic_err,
683*5113495bSYour Name msdu_end->l3_header_padding,
684*5113495bSYour Name msdu_end->first_msdu,
685*5113495bSYour Name msdu_end->last_msdu,
686*5113495bSYour Name msdu_end->sa_idx,
687*5113495bSYour Name msdu_end->msdu_drop,
688*5113495bSYour Name msdu_end->reo_destination_indication,
689*5113495bSYour Name msdu_end->flow_idx,
690*5113495bSYour Name msdu_end->fse_metadata,
691*5113495bSYour Name msdu_end->cce_metadata,
692*5113495bSYour Name msdu_end->sa_sw_peer_id);
693*5113495bSYour Name }
694*5113495bSYour Name #endif
695*5113495bSYour Name
696*5113495bSYour Name /**
697*5113495bSYour Name * hal_reo_status_get_header_5332() - Process reo desc info
698*5113495bSYour Name * @ring_desc: Pointer to reo descriptor
699*5113495bSYour Name * @b: tlv type info
700*5113495bSYour Name * @h1: Pointer to hal_reo_status_header where info to be stored
701*5113495bSYour Name *
702*5113495bSYour Name * Return: none.
703*5113495bSYour Name *
704*5113495bSYour Name */
hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,int b,void * h1)705*5113495bSYour Name static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,
706*5113495bSYour Name int b, void *h1)
707*5113495bSYour Name {
708*5113495bSYour Name uint64_t *d = (uint64_t *)ring_desc;
709*5113495bSYour Name uint64_t val1 = 0;
710*5113495bSYour Name struct hal_reo_status_header *h =
711*5113495bSYour Name (struct hal_reo_status_header *)h1;
712*5113495bSYour Name
713*5113495bSYour Name /* Offsets of descriptor fields defined in HW headers start
714*5113495bSYour Name * from the field after TLV header
715*5113495bSYour Name */
716*5113495bSYour Name d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
717*5113495bSYour Name
718*5113495bSYour Name switch (b) {
719*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
720*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
721*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
722*5113495bSYour Name break;
723*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
724*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
725*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
726*5113495bSYour Name break;
727*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
728*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
729*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
730*5113495bSYour Name break;
731*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
732*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
733*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
734*5113495bSYour Name break;
735*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
736*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
737*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
738*5113495bSYour Name break;
739*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
740*5113495bSYour Name val1 =
741*5113495bSYour Name d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
742*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
743*5113495bSYour Name break;
744*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
745*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
746*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
747*5113495bSYour Name break;
748*5113495bSYour Name default:
749*5113495bSYour Name qdf_nofl_err("ERROR: Unknown tlv\n");
750*5113495bSYour Name break;
751*5113495bSYour Name }
752*5113495bSYour Name h->cmd_num =
753*5113495bSYour Name HAL_GET_FIELD(
754*5113495bSYour Name UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
755*5113495bSYour Name val1);
756*5113495bSYour Name h->exec_time =
757*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
758*5113495bSYour Name CMD_EXECUTION_TIME, val1);
759*5113495bSYour Name h->status =
760*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
761*5113495bSYour Name REO_CMD_EXECUTION_STATUS, val1);
762*5113495bSYour Name switch (b) {
763*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
764*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
765*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
766*5113495bSYour Name break;
767*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
768*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
769*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
770*5113495bSYour Name break;
771*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
772*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
773*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
774*5113495bSYour Name break;
775*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
776*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
777*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
778*5113495bSYour Name break;
779*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
780*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
781*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
782*5113495bSYour Name break;
783*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
784*5113495bSYour Name val1 =
785*5113495bSYour Name d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
786*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
787*5113495bSYour Name break;
788*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
789*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
790*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
791*5113495bSYour Name break;
792*5113495bSYour Name default:
793*5113495bSYour Name qdf_nofl_err("ERROR: Unknown tlv\n");
794*5113495bSYour Name break;
795*5113495bSYour Name }
796*5113495bSYour Name h->tstamp =
797*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
798*5113495bSYour Name }
799*5113495bSYour Name
800*5113495bSYour Name static
hal_rx_msdu0_buffer_addr_lsb_5332(void * link_desc_va)801*5113495bSYour Name void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va)
802*5113495bSYour Name {
803*5113495bSYour Name return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
804*5113495bSYour Name }
805*5113495bSYour Name
806*5113495bSYour Name static
hal_rx_msdu_desc_info_ptr_get_5332(void * msdu0)807*5113495bSYour Name void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0)
808*5113495bSYour Name {
809*5113495bSYour Name return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
810*5113495bSYour Name }
811*5113495bSYour Name
812*5113495bSYour Name static
hal_ent_mpdu_desc_info_5332(void * ent_ring_desc)813*5113495bSYour Name void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc)
814*5113495bSYour Name {
815*5113495bSYour Name return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
816*5113495bSYour Name }
817*5113495bSYour Name
818*5113495bSYour Name static
hal_dst_mpdu_desc_info_5332(void * dst_ring_desc)819*5113495bSYour Name void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc)
820*5113495bSYour Name {
821*5113495bSYour Name return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
822*5113495bSYour Name }
823*5113495bSYour Name
824*5113495bSYour Name /**
825*5113495bSYour Name * hal_reo_config_5332() - Set reo config parameters
826*5113495bSYour Name * @soc: hal soc handle
827*5113495bSYour Name * @reg_val: value to be set
828*5113495bSYour Name * @reo_params: reo parameters
829*5113495bSYour Name *
830*5113495bSYour Name * Return: void
831*5113495bSYour Name */
832*5113495bSYour Name static void
hal_reo_config_5332(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)833*5113495bSYour Name hal_reo_config_5332(struct hal_soc *soc,
834*5113495bSYour Name uint32_t reg_val,
835*5113495bSYour Name struct hal_reo_params *reo_params)
836*5113495bSYour Name {
837*5113495bSYour Name HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
838*5113495bSYour Name }
839*5113495bSYour Name
840*5113495bSYour Name /**
841*5113495bSYour Name * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr
842*5113495bSYour Name * @msdu_details_ptr: Pointer to msdu_details_ptr
843*5113495bSYour Name *
844*5113495bSYour Name * Return: Pointer to rx_msdu_desc_info structure.
845*5113495bSYour Name *
846*5113495bSYour Name */
hal_rx_msdu_desc_info_get_ptr_5332(void * msdu_details_ptr)847*5113495bSYour Name static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr)
848*5113495bSYour Name {
849*5113495bSYour Name return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
850*5113495bSYour Name }
851*5113495bSYour Name
852*5113495bSYour Name /**
853*5113495bSYour Name * hal_rx_link_desc_msdu0_ptr_5332() - Get pointer to rx_msdu details
854*5113495bSYour Name * @link_desc: Pointer to link desc
855*5113495bSYour Name *
856*5113495bSYour Name * Return: Pointer to rx_msdu_details structure
857*5113495bSYour Name *
858*5113495bSYour Name */
hal_rx_link_desc_msdu0_ptr_5332(void * link_desc)859*5113495bSYour Name static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc)
860*5113495bSYour Name {
861*5113495bSYour Name return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
862*5113495bSYour Name }
863*5113495bSYour Name
864*5113495bSYour Name /**
865*5113495bSYour Name * hal_get_window_address_5332() - Function to get hp/tp address
866*5113495bSYour Name * @hal_soc: Pointer to hal_soc
867*5113495bSYour Name * @addr: address offset of register
868*5113495bSYour Name *
869*5113495bSYour Name * Return: modified address offset of register
870*5113495bSYour Name */
hal_get_window_address_5332(struct hal_soc * hal_soc,qdf_iomem_t addr)871*5113495bSYour Name static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc,
872*5113495bSYour Name qdf_iomem_t addr)
873*5113495bSYour Name {
874*5113495bSYour Name uint32_t offset = addr - hal_soc->dev_base_addr;
875*5113495bSYour Name qdf_iomem_t new_offset;
876*5113495bSYour Name
877*5113495bSYour Name /*
878*5113495bSYour Name * Check if offset lies within CE register range(0x740000)
879*5113495bSYour Name * or UMAC/DP register range (0x00A00000).
880*5113495bSYour Name * If offset lies within CE register range, map it
881*5113495bSYour Name * into CE region.
882*5113495bSYour Name */
883*5113495bSYour Name if (offset < 0xA00000) {
884*5113495bSYour Name offset = offset - CE_CFG_WFSS_CE_REG_BASE;
885*5113495bSYour Name new_offset = (hal_soc->dev_base_addr_ce + offset);
886*5113495bSYour Name
887*5113495bSYour Name return new_offset;
888*5113495bSYour Name } else {
889*5113495bSYour Name /*
890*5113495bSYour Name * If offset lies within DP register range,
891*5113495bSYour Name * return the address as such
892*5113495bSYour Name */
893*5113495bSYour Name return addr;
894*5113495bSYour Name }
895*5113495bSYour Name }
896*5113495bSYour Name
897*5113495bSYour Name static
hal_compute_reo_remap_ix2_ix3_5332(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)898*5113495bSYour Name void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings,
899*5113495bSYour Name uint32_t *remap1, uint32_t *remap2)
900*5113495bSYour Name {
901*5113495bSYour Name switch (num_rings) {
902*5113495bSYour Name case 1:
903*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
904*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 17) |
905*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 18) |
906*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 19) |
907*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
908*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 21) |
909*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 22) |
910*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 23);
911*5113495bSYour Name
912*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
913*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
914*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 26) |
915*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 27) |
916*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
917*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 29) |
918*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 30) |
919*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 31);
920*5113495bSYour Name break;
921*5113495bSYour Name case 2:
922*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
923*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 17) |
924*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 18) |
925*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 19) |
926*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
927*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 21) |
928*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 22) |
929*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 23);
930*5113495bSYour Name
931*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
932*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
933*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 26) |
934*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 27) |
935*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
936*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 29) |
937*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 30) |
938*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 31);
939*5113495bSYour Name break;
940*5113495bSYour Name case 3:
941*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
942*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 17) |
943*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 18) |
944*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 19) |
945*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 20) |
946*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 21) |
947*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 22) |
948*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 23);
949*5113495bSYour Name
950*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
951*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
952*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 26) |
953*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 27) |
954*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
955*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 29) |
956*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 30) |
957*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 31);
958*5113495bSYour Name break;
959*5113495bSYour Name case 4:
960*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
961*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 17) |
962*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 18) |
963*5113495bSYour Name HAL_REO_REMAP_IX2(ring[3], 19) |
964*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
965*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 21) |
966*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 22) |
967*5113495bSYour Name HAL_REO_REMAP_IX2(ring[3], 23);
968*5113495bSYour Name
969*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
970*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 25) |
971*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 26) |
972*5113495bSYour Name HAL_REO_REMAP_IX3(ring[3], 27) |
973*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
974*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 29) |
975*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 30) |
976*5113495bSYour Name HAL_REO_REMAP_IX3(ring[3], 31);
977*5113495bSYour Name break;
978*5113495bSYour Name }
979*5113495bSYour Name }
980*5113495bSYour Name
981*5113495bSYour Name /**
982*5113495bSYour Name * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST
983*5113495bSYour Name * @rx_fst: Pointer to the Rx Flow Search Table
984*5113495bSYour Name * @table_offset: offset into the table where the flow is to be setup
985*5113495bSYour Name * @rx_flow: Flow Parameters
986*5113495bSYour Name *
987*5113495bSYour Name * Return: Success/Failure
988*5113495bSYour Name */
989*5113495bSYour Name static void *
hal_rx_flow_setup_fse_5332(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)990*5113495bSYour Name hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset,
991*5113495bSYour Name uint8_t *rx_flow)
992*5113495bSYour Name {
993*5113495bSYour Name struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
994*5113495bSYour Name struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
995*5113495bSYour Name uint8_t *fse;
996*5113495bSYour Name bool fse_valid;
997*5113495bSYour Name
998*5113495bSYour Name if (table_offset >= fst->max_entries) {
999*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1000*5113495bSYour Name "HAL FSE table offset %u exceeds max entries %u",
1001*5113495bSYour Name table_offset, fst->max_entries);
1002*5113495bSYour Name return NULL;
1003*5113495bSYour Name }
1004*5113495bSYour Name
1005*5113495bSYour Name fse = (uint8_t *)fst->base_vaddr +
1006*5113495bSYour Name (table_offset * HAL_RX_FST_ENTRY_SIZE);
1007*5113495bSYour Name
1008*5113495bSYour Name fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1009*5113495bSYour Name
1010*5113495bSYour Name if (fse_valid) {
1011*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1012*5113495bSYour Name "HAL FSE %pK already valid", fse);
1013*5113495bSYour Name return NULL;
1014*5113495bSYour Name }
1015*5113495bSYour Name
1016*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
1017*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1018*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_127_96));
1019*5113495bSYour Name
1020*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
1021*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1022*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_95_64));
1023*5113495bSYour Name
1024*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
1025*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1026*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_63_32));
1027*5113495bSYour Name
1028*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
1029*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1030*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_31_0));
1031*5113495bSYour Name
1032*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
1033*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1034*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_127_96));
1035*5113495bSYour Name
1036*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
1037*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1038*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_95_64));
1039*5113495bSYour Name
1040*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
1041*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1042*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_63_32));
1043*5113495bSYour Name
1044*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
1045*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1046*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_31_0));
1047*5113495bSYour Name
1048*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
1049*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
1050*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1051*5113495bSYour Name (flow->tuple_info.dest_port));
1052*5113495bSYour Name
1053*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
1054*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
1055*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1056*5113495bSYour Name (flow->tuple_info.src_port));
1057*5113495bSYour Name
1058*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
1059*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
1060*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1061*5113495bSYour Name flow->tuple_info.l4_protocol);
1062*5113495bSYour Name
1063*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
1064*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
1065*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1066*5113495bSYour Name flow->reo_destination_handler);
1067*5113495bSYour Name
1068*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1069*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
1070*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1071*5113495bSYour Name
1072*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
1073*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
1074*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1075*5113495bSYour Name flow->fse_metadata);
1076*5113495bSYour Name
1077*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
1078*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
1079*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1080*5113495bSYour Name REO_DESTINATION_INDICATION,
1081*5113495bSYour Name flow->reo_destination_indication);
1082*5113495bSYour Name
1083*5113495bSYour Name /* Reset all the other fields in FSE */
1084*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
1085*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
1086*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
1087*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
1088*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
1089*5113495bSYour Name
1090*5113495bSYour Name return fse;
1091*5113495bSYour Name }
1092*5113495bSYour Name
1093*5113495bSYour Name /**
1094*5113495bSYour Name * hal_rx_dump_pkt_hdr_tlv_5332() - dump RX pkt header TLV in hex format
1095*5113495bSYour Name * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
1096*5113495bSYour Name * @dbg_level: log level.
1097*5113495bSYour Name *
1098*5113495bSYour Name * Return: void
1099*5113495bSYour Name */
1100*5113495bSYour Name #ifndef NO_RX_PKT_HDR_TLV
hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1101*5113495bSYour Name static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
1102*5113495bSYour Name uint8_t dbg_level)
1103*5113495bSYour Name {
1104*5113495bSYour Name struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
1105*5113495bSYour Name
1106*5113495bSYour Name hal_verbose_debug("\n---------------\n"
1107*5113495bSYour Name "rx_pkt_hdr_tlv\n"
1108*5113495bSYour Name "---------------\n"
1109*5113495bSYour Name "phy_ppdu_id 0x%x ",
1110*5113495bSYour Name pkt_hdr_tlv->phy_ppdu_id);
1111*5113495bSYour Name
1112*5113495bSYour Name hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
1113*5113495bSYour Name sizeof(pkt_hdr_tlv->rx_pkt_hdr));
1114*5113495bSYour Name }
1115*5113495bSYour Name #else
hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1116*5113495bSYour Name static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
1117*5113495bSYour Name uint8_t dbg_level)
1118*5113495bSYour Name {
1119*5113495bSYour Name }
1120*5113495bSYour Name #endif
1121*5113495bSYour Name
1122*5113495bSYour Name /**
1123*5113495bSYour Name * hal_rx_dump_pkt_tlvs_5332() - API to print RX Pkt TLVS qca5332
1124*5113495bSYour Name * @hal_soc_hdl: hal_soc handle
1125*5113495bSYour Name * @buf: pointer the pkt buffer
1126*5113495bSYour Name * @dbg_level: log level
1127*5113495bSYour Name *
1128*5113495bSYour Name * Return: void
1129*5113495bSYour Name */
1130*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1131*5113495bSYour Name static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
1132*5113495bSYour Name uint8_t *buf, uint8_t dbg_level)
1133*5113495bSYour Name {
1134*5113495bSYour Name struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1135*5113495bSYour Name struct rx_msdu_end_compact *msdu_end =
1136*5113495bSYour Name &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1137*5113495bSYour Name struct rx_mpdu_start_compact *mpdu_start =
1138*5113495bSYour Name &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1139*5113495bSYour Name
1140*5113495bSYour Name hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
1141*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
1142*5113495bSYour Name hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
1143*5113495bSYour Name }
1144*5113495bSYour Name #else
hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1145*5113495bSYour Name static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
1146*5113495bSYour Name uint8_t *buf, uint8_t dbg_level)
1147*5113495bSYour Name {
1148*5113495bSYour Name struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1149*5113495bSYour Name struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1150*5113495bSYour Name struct rx_mpdu_start *mpdu_start =
1151*5113495bSYour Name &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1152*5113495bSYour Name
1153*5113495bSYour Name hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
1154*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
1155*5113495bSYour Name hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
1156*5113495bSYour Name }
1157*5113495bSYour Name #endif
1158*5113495bSYour Name
1159*5113495bSYour Name #define HAL_NUM_TCL_BANKS_5332 24
1160*5113495bSYour Name
1161*5113495bSYour Name /**
1162*5113495bSYour Name * hal_cmem_write_5332() - function for CMEM buffer writing
1163*5113495bSYour Name * @hal_soc_hdl: HAL SOC handle
1164*5113495bSYour Name * @offset: CMEM address
1165*5113495bSYour Name * @value: value to write
1166*5113495bSYour Name *
1167*5113495bSYour Name * Return: None.
1168*5113495bSYour Name */
hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,uint32_t offset,uint32_t value)1169*5113495bSYour Name static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,
1170*5113495bSYour Name uint32_t offset,
1171*5113495bSYour Name uint32_t value)
1172*5113495bSYour Name {
1173*5113495bSYour Name struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
1174*5113495bSYour Name
1175*5113495bSYour Name /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting
1176*5113495bSYour Name * that from offset.
1177*5113495bSYour Name */
1178*5113495bSYour Name offset = offset - CMEM_REG_BASE;
1179*5113495bSYour Name pld_reg_write(hal->qdf_dev->dev, offset, value,
1180*5113495bSYour Name hal->dev_base_addr_cmem);
1181*5113495bSYour Name }
1182*5113495bSYour Name
1183*5113495bSYour Name /**
1184*5113495bSYour Name * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target
1185*5113495bSYour Name *
1186*5113495bSYour Name * Return: number of bank
1187*5113495bSYour Name */
hal_tx_get_num_tcl_banks_5332(void)1188*5113495bSYour Name static uint8_t hal_tx_get_num_tcl_banks_5332(void)
1189*5113495bSYour Name {
1190*5113495bSYour Name return HAL_NUM_TCL_BANKS_5332;
1191*5113495bSYour Name }
1192*5113495bSYour Name
hal_reo_setup_5332(struct hal_soc * soc,void * reoparams,int qref_reset)1193*5113495bSYour Name static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams,
1194*5113495bSYour Name int qref_reset)
1195*5113495bSYour Name {
1196*5113495bSYour Name uint32_t reg_val;
1197*5113495bSYour Name struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
1198*5113495bSYour Name
1199*5113495bSYour Name reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
1200*5113495bSYour Name REO_REG_REG_BASE));
1201*5113495bSYour Name
1202*5113495bSYour Name hal_reo_config_5332(soc, reg_val, reo_params);
1203*5113495bSYour Name /* Other ring enable bits and REO_ENABLE will be set by FW */
1204*5113495bSYour Name
1205*5113495bSYour Name /* TODO: Setup destination ring mapping if enabled */
1206*5113495bSYour Name
1207*5113495bSYour Name /* TODO: Error destination ring setting is left to default.
1208*5113495bSYour Name * Default setting is to send all errors to release ring.
1209*5113495bSYour Name */
1210*5113495bSYour Name
1211*5113495bSYour Name /* Set the reo descriptor swap bits in case of BIG endian platform */
1212*5113495bSYour Name hal_setup_reo_swap(soc);
1213*5113495bSYour Name
1214*5113495bSYour Name HAL_REG_WRITE(soc,
1215*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
1216*5113495bSYour Name HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
1217*5113495bSYour Name
1218*5113495bSYour Name HAL_REG_WRITE(soc,
1219*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
1220*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1221*5113495bSYour Name
1222*5113495bSYour Name HAL_REG_WRITE(soc,
1223*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
1224*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1225*5113495bSYour Name
1226*5113495bSYour Name HAL_REG_WRITE(soc,
1227*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
1228*5113495bSYour Name (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
1229*5113495bSYour Name
1230*5113495bSYour Name /*
1231*5113495bSYour Name * When hash based routing is enabled, routing of the rx packet
1232*5113495bSYour Name * is done based on the following value: 1 _ _ _ _ The last 4
1233*5113495bSYour Name * bits are based on hash[3:0]. This means the possible values
1234*5113495bSYour Name * are 0x10 to 0x1f. This value is used to look-up the
1235*5113495bSYour Name * ring ID configured in Destination_Ring_Ctrl_IX_* register.
1236*5113495bSYour Name * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
1237*5113495bSYour Name * registers need to be configured to set-up the 16 entries to
1238*5113495bSYour Name * map the hash values to a ring number. There are 3 bits per
1239*5113495bSYour Name * hash entry – which are mapped as follows:
1240*5113495bSYour Name * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
1241*5113495bSYour Name * 7: NOT_USED.
1242*5113495bSYour Name */
1243*5113495bSYour Name if (reo_params->rx_hash_enabled) {
1244*5113495bSYour Name HAL_REG_WRITE(soc,
1245*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
1246*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap0);
1247*5113495bSYour Name
1248*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1249*5113495bSYour Name HAL_REG_READ(soc,
1250*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
1251*5113495bSYour Name REO_REG_REG_BASE)));
1252*5113495bSYour Name
1253*5113495bSYour Name HAL_REG_WRITE(soc,
1254*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
1255*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap1);
1256*5113495bSYour Name
1257*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1258*5113495bSYour Name HAL_REG_READ(soc,
1259*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
1260*5113495bSYour Name REO_REG_REG_BASE)));
1261*5113495bSYour Name
1262*5113495bSYour Name HAL_REG_WRITE(soc,
1263*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
1264*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap2);
1265*5113495bSYour Name
1266*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
1267*5113495bSYour Name HAL_REG_READ(soc,
1268*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
1269*5113495bSYour Name REO_REG_REG_BASE)));
1270*5113495bSYour Name }
1271*5113495bSYour Name
1272*5113495bSYour Name /* TODO: Check if the following registers shoould be setup by host:
1273*5113495bSYour Name * AGING_CONTROL
1274*5113495bSYour Name * HIGH_MEMORY_THRESHOLD
1275*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
1276*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_CTRL
1277*5113495bSYour Name */
1278*5113495bSYour Name
1279*5113495bSYour Name soc->reo_qref = *reo_params->reo_qref;
1280*5113495bSYour Name hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
1281*5113495bSYour Name }
1282*5113495bSYour Name
hal_get_rx_max_ba_window_qca5332(int tid)1283*5113495bSYour Name static uint16_t hal_get_rx_max_ba_window_qca5332(int tid)
1284*5113495bSYour Name {
1285*5113495bSYour Name return HAL_RX_BA_WINDOW_1024;
1286*5113495bSYour Name }
1287*5113495bSYour Name
1288*5113495bSYour Name /**
1289*5113495bSYour Name * hal_qca5332_get_reo_qdesc_size() - Get the reo queue descriptor size
1290*5113495bSYour Name * from the give Block-Ack window size
1291*5113495bSYour Name * @ba_window_size: Block-Ack window size
1292*5113495bSYour Name * @tid: TID
1293*5113495bSYour Name *
1294*5113495bSYour Name * Return: reo queue descriptor size
1295*5113495bSYour Name */
hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size,int tid)1296*5113495bSYour Name static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
1297*5113495bSYour Name {
1298*5113495bSYour Name /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
1299*5113495bSYour Name * NON_QOS_TID until HW issues are resolved.
1300*5113495bSYour Name */
1301*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
1302*5113495bSYour Name ba_window_size = hal_get_rx_max_ba_window_qca5332(tid);
1303*5113495bSYour Name
1304*5113495bSYour Name /* Return descriptor size corresponding to window size of 2 since
1305*5113495bSYour Name * we set ba_window_size to 2 while setting up REO descriptors as
1306*5113495bSYour Name * a WAR to get 2k jump exception aggregates are received without
1307*5113495bSYour Name * a BA session.
1308*5113495bSYour Name */
1309*5113495bSYour Name if (ba_window_size <= 1) {
1310*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
1311*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1312*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
1313*5113495bSYour Name else
1314*5113495bSYour Name return sizeof(struct rx_reo_queue);
1315*5113495bSYour Name }
1316*5113495bSYour Name
1317*5113495bSYour Name if (ba_window_size <= 105)
1318*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1319*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
1320*5113495bSYour Name
1321*5113495bSYour Name if (ba_window_size <= 210)
1322*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1323*5113495bSYour Name (2 * sizeof(struct rx_reo_queue_ext));
1324*5113495bSYour Name
1325*5113495bSYour Name if (ba_window_size <= 256)
1326*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1327*5113495bSYour Name (3 * sizeof(struct rx_reo_queue_ext));
1328*5113495bSYour Name
1329*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1330*5113495bSYour Name (10 * sizeof(struct rx_reo_queue_ext)) +
1331*5113495bSYour Name sizeof(struct rx_reo_queue_1k);
1332*5113495bSYour Name }
1333*5113495bSYour Name
1334*5113495bSYour Name /**
1335*5113495bSYour Name * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv
1336*5113495bSYour Name * @buf: pointer the tx_tlv
1337*5113495bSYour Name *
1338*5113495bSYour Name * Return: msdu done copy bit
1339*5113495bSYour Name */
hal_rx_tlv_msdu_done_copy_get_5332(uint8_t * buf)1340*5113495bSYour Name static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf)
1341*5113495bSYour Name {
1342*5113495bSYour Name return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
1343*5113495bSYour Name }
1344*5113495bSYour Name
hal_hw_txrx_ops_attach_qca5332(struct hal_soc * hal_soc)1345*5113495bSYour Name static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc)
1346*5113495bSYour Name {
1347*5113495bSYour Name /* init and setup */
1348*5113495bSYour Name hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1349*5113495bSYour Name hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1350*5113495bSYour Name hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic;
1351*5113495bSYour Name hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1352*5113495bSYour Name hal_soc->ops->hal_get_window_address = hal_get_window_address_5332;
1353*5113495bSYour Name hal_soc->ops->hal_cmem_write = hal_cmem_write_5332;
1354*5113495bSYour Name
1355*5113495bSYour Name /* tx */
1356*5113495bSYour Name hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332;
1357*5113495bSYour Name hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332;
1358*5113495bSYour Name hal_soc->ops->hal_tx_comp_get_status =
1359*5113495bSYour Name hal_tx_comp_get_status_generic_be;
1360*5113495bSYour Name hal_soc->ops->hal_tx_init_cmd_credit_ring =
1361*5113495bSYour Name hal_tx_init_cmd_credit_ring_5332;
1362*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL;
1363*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL;
1364*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL;
1365*5113495bSYour Name hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL;
1366*5113495bSYour Name hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL;
1367*5113495bSYour Name hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL;
1368*5113495bSYour Name hal_soc->ops->hal_tx_enable_pri2tid_map = NULL;
1369*5113495bSYour Name hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = NULL;
1370*5113495bSYour Name hal_soc->ops->hal_tx_config_rbm_mapping_be =
1371*5113495bSYour Name hal_tx_config_rbm_mapping_be_5332;
1372*5113495bSYour Name
1373*5113495bSYour Name /* rx */
1374*5113495bSYour Name hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
1375*5113495bSYour Name hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1376*5113495bSYour Name hal_rx_mon_hw_desc_get_mpdu_status_be;
1377*5113495bSYour Name hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332;
1378*5113495bSYour Name hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1379*5113495bSYour Name hal_rx_proc_phyrx_other_receive_info_tlv_5332;
1380*5113495bSYour Name
1381*5113495bSYour Name hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332;
1382*5113495bSYour Name hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1383*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_5332;
1384*5113495bSYour Name hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332;
1385*5113495bSYour Name
1386*5113495bSYour Name hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332;
1387*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
1388*5113495bSYour Name hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1389*5113495bSYour Name hal_rx_tlv_reception_type_get_be;
1390*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1391*5113495bSYour Name hal_rx_msdu_end_da_idx_get_be;
1392*5113495bSYour Name hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1393*5113495bSYour Name hal_rx_msdu_desc_info_get_ptr_5332;
1394*5113495bSYour Name hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1395*5113495bSYour Name hal_rx_link_desc_msdu0_ptr_5332;
1396*5113495bSYour Name hal_soc->ops->hal_reo_status_get_header =
1397*5113495bSYour Name hal_reo_status_get_header_5332;
1398*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
1399*5113495bSYour Name hal_soc->ops->hal_rx_status_get_tlv_info =
1400*5113495bSYour Name hal_rx_status_get_tlv_info_wrapper_be;
1401*5113495bSYour Name #endif
1402*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_info_get =
1403*5113495bSYour Name hal_rx_wbm_err_info_get_generic_be;
1404*5113495bSYour Name hal_soc->ops->hal_tx_set_pcp_tid_map =
1405*5113495bSYour Name hal_tx_set_pcp_tid_map_generic_be;
1406*5113495bSYour Name hal_soc->ops->hal_tx_update_pcp_tid_map =
1407*5113495bSYour Name hal_tx_update_pcp_tid_generic_be;
1408*5113495bSYour Name hal_soc->ops->hal_tx_set_tidmap_prty =
1409*5113495bSYour Name hal_tx_update_tidmap_prty_generic_be;
1410*5113495bSYour Name hal_soc->ops->hal_rx_get_rx_fragment_number =
1411*5113495bSYour Name hal_rx_get_rx_fragment_number_be,
1412*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1413*5113495bSYour Name hal_rx_tlv_da_is_mcbc_get_be;
1414*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
1415*5113495bSYour Name hal_rx_tlv_is_tkip_mic_err_get_be;
1416*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1417*5113495bSYour Name hal_rx_tlv_sa_is_valid_get_be;
1418*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
1419*5113495bSYour Name hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
1420*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1421*5113495bSYour Name hal_rx_tlv_l3_hdr_padding_get_be;
1422*5113495bSYour Name hal_soc->ops->hal_rx_encryption_info_valid =
1423*5113495bSYour Name hal_rx_encryption_info_valid_be;
1424*5113495bSYour Name hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
1425*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1426*5113495bSYour Name hal_rx_tlv_first_msdu_get_be;
1427*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1428*5113495bSYour Name hal_rx_tlv_da_is_valid_get_be;
1429*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1430*5113495bSYour Name hal_rx_tlv_last_msdu_get_be;
1431*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1432*5113495bSYour Name hal_rx_get_mpdu_mac_ad4_valid_be;
1433*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1434*5113495bSYour Name hal_rx_mpdu_start_sw_peer_id_get_be;
1435*5113495bSYour Name hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1436*5113495bSYour Name hal_rx_msdu_peer_meta_data_get_be;
1437*5113495bSYour Name #ifndef CONFIG_WORD_BASED_TLV
1438*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
1439*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1440*5113495bSYour Name hal_rx_mpdu_info_ampdu_flag_get_be;
1441*5113495bSYour Name hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1442*5113495bSYour Name hal_rx_hw_desc_get_ppduid_get_be;
1443*5113495bSYour Name hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
1444*5113495bSYour Name hal_rx_attn_phy_ppdu_id_get_be;
1445*5113495bSYour Name hal_soc->ops->hal_rx_get_filter_category =
1446*5113495bSYour Name hal_rx_get_filter_category_be;
1447*5113495bSYour Name #endif
1448*5113495bSYour Name hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
1449*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
1450*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
1451*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1452*5113495bSYour Name hal_rx_get_mpdu_frame_control_valid_be;
1453*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
1454*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
1455*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
1456*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1457*5113495bSYour Name hal_rx_get_mpdu_sequence_control_valid_be;
1458*5113495bSYour Name hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
1459*5113495bSYour Name hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
1460*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1461*5113495bSYour Name hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
1462*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1463*5113495bSYour Name hal_rx_msdu_end_sa_sw_peer_id_get_be;
1464*5113495bSYour Name hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1465*5113495bSYour Name hal_rx_msdu0_buffer_addr_lsb_5332;
1466*5113495bSYour Name hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1467*5113495bSYour Name hal_rx_msdu_desc_info_ptr_get_5332;
1468*5113495bSYour Name hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332;
1469*5113495bSYour Name hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332;
1470*5113495bSYour Name hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
1471*5113495bSYour Name hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
1472*5113495bSYour Name hal_soc->ops->hal_rx_get_mac_addr2_valid =
1473*5113495bSYour Name hal_rx_get_mac_addr2_valid_be;
1474*5113495bSYour Name hal_soc->ops->hal_reo_config = hal_reo_config_5332;
1475*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
1476*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1477*5113495bSYour Name hal_rx_msdu_flow_idx_invalid_be;
1478*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1479*5113495bSYour Name hal_rx_msdu_flow_idx_timeout_be;
1480*5113495bSYour Name hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1481*5113495bSYour Name hal_rx_msdu_fse_metadata_get_be;
1482*5113495bSYour Name hal_soc->ops->hal_rx_msdu_cce_match_get =
1483*5113495bSYour Name hal_rx_msdu_cce_match_get_be;
1484*5113495bSYour Name hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1485*5113495bSYour Name hal_rx_msdu_cce_metadata_get_be;
1486*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_flow_params =
1487*5113495bSYour Name hal_rx_msdu_get_flow_params_be;
1488*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
1489*5113495bSYour Name hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
1490*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1491*5113495bSYour Name hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332;
1492*5113495bSYour Name hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332;
1493*5113495bSYour Name #else
1494*5113495bSYour Name hal_soc->ops->hal_rx_get_bb_info = NULL;
1495*5113495bSYour Name hal_soc->ops->hal_rx_get_rtt_info = NULL;
1496*5113495bSYour Name #endif
1497*5113495bSYour Name /* rx - msdu fast path info fields */
1498*5113495bSYour Name hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1499*5113495bSYour Name hal_rx_msdu_packet_metadata_get_generic_be;
1500*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1501*5113495bSYour Name hal_rx_mpdu_start_tlv_tag_valid_be;
1502*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1503*5113495bSYour Name hal_rx_wbm_err_msdu_continuation_get_5332;
1504*5113495bSYour Name
1505*5113495bSYour Name /* rx - TLV struct offsets */
1506*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_offset_get =
1507*5113495bSYour Name hal_rx_msdu_end_offset_get_generic;
1508*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_offset_get =
1509*5113495bSYour Name hal_rx_mpdu_start_offset_get_generic;
1510*5113495bSYour Name #ifndef NO_RX_PKT_HDR_TLV
1511*5113495bSYour Name hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1512*5113495bSYour Name hal_rx_pkt_tlv_offset_get_generic;
1513*5113495bSYour Name #endif
1514*5113495bSYour Name hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332;
1515*5113495bSYour Name
1516*5113495bSYour Name hal_soc->ops->hal_rx_flow_get_tuple_info =
1517*5113495bSYour Name hal_rx_flow_get_tuple_info_be;
1518*5113495bSYour Name hal_soc->ops->hal_rx_flow_delete_entry =
1519*5113495bSYour Name hal_rx_flow_delete_entry_be;
1520*5113495bSYour Name hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
1521*5113495bSYour Name hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1522*5113495bSYour Name hal_compute_reo_remap_ix2_ix3_5332;
1523*5113495bSYour Name
1524*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
1525*5113495bSYour Name hal_rx_msdu_get_reo_destination_indication_be;
1526*5113495bSYour Name hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
1527*5113495bSYour Name hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
1528*5113495bSYour Name hal_rx_msdu_is_wlan_mcast_generic_be;
1529*5113495bSYour Name hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332;
1530*5113495bSYour Name hal_soc->ops->hal_rx_tlv_decap_format_get =
1531*5113495bSYour Name hal_rx_tlv_decap_format_get_be;
1532*5113495bSYour Name #ifdef RECEIVE_OFFLOAD
1533*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_offload_info =
1534*5113495bSYour Name hal_rx_tlv_get_offload_info_be;
1535*5113495bSYour Name hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
1536*5113495bSYour Name hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
1537*5113495bSYour Name #endif
1538*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_done_get =
1539*5113495bSYour Name hal_rx_tlv_msdu_done_copy_get_5332;
1540*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_len_get =
1541*5113495bSYour Name hal_rx_msdu_start_msdu_len_get_be;
1542*5113495bSYour Name hal_soc->ops->hal_rx_get_frame_ctrl_field =
1543*5113495bSYour Name hal_rx_get_frame_ctrl_field_be;
1544*5113495bSYour Name hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
1545*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_len_set =
1546*5113495bSYour Name hal_rx_msdu_start_msdu_len_set_be;
1547*5113495bSYour Name hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
1548*5113495bSYour Name hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
1549*5113495bSYour Name hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
1550*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
1551*5113495bSYour Name hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
1552*5113495bSYour Name hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1553*5113495bSYour Name hal_rx_tlv_decrypt_err_get_be;
1554*5113495bSYour Name hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
1555*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_is_decrypted =
1556*5113495bSYour Name hal_rx_tlv_get_is_decrypted_be;
1557*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
1558*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
1559*5113495bSYour Name hal_soc->ops->hal_rx_priv_info_set_in_tlv =
1560*5113495bSYour Name hal_rx_priv_info_set_in_tlv_be;
1561*5113495bSYour Name hal_soc->ops->hal_rx_priv_info_get_from_tlv =
1562*5113495bSYour Name hal_rx_priv_info_get_from_tlv_be;
1563*5113495bSYour Name hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
1564*5113495bSYour Name hal_soc->ops->hal_reo_setup = hal_reo_setup_5332;
1565*5113495bSYour Name #ifdef REO_SHARED_QREF_TABLE_EN
1566*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
1567*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
1568*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
1569*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
1570*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
1571*5113495bSYour Name #endif
1572*5113495bSYour Name /* Overwrite the default BE ops */
1573*5113495bSYour Name hal_soc->ops->hal_get_rx_max_ba_window =
1574*5113495bSYour Name hal_get_rx_max_ba_window_qca5332;
1575*5113495bSYour Name hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size;
1576*5113495bSYour Name /* TX MONITOR */
1577*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_TX_2_0
1578*5113495bSYour Name hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
1579*5113495bSYour Name hal_txmon_is_mon_buf_addr_tlv_generic_be;
1580*5113495bSYour Name hal_soc->ops->hal_txmon_populate_packet_info =
1581*5113495bSYour Name hal_txmon_populate_packet_info_generic_be;
1582*5113495bSYour Name hal_soc->ops->hal_txmon_status_parse_tlv =
1583*5113495bSYour Name hal_txmon_status_parse_tlv_generic_be;
1584*5113495bSYour Name hal_soc->ops->hal_txmon_status_get_num_users =
1585*5113495bSYour Name hal_txmon_status_get_num_users_generic_be;
1586*5113495bSYour Name #if defined(TX_MONITOR_WORD_MASK)
1587*5113495bSYour Name hal_soc->ops->hal_txmon_get_word_mask =
1588*5113495bSYour Name hal_txmon_get_word_mask_qca5332;
1589*5113495bSYour Name #else
1590*5113495bSYour Name hal_soc->ops->hal_txmon_get_word_mask =
1591*5113495bSYour Name hal_txmon_get_word_mask_generic_be;
1592*5113495bSYour Name #endif /* TX_MONITOR_WORD_MASK */
1593*5113495bSYour Name #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
1594*5113495bSYour Name hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1595*5113495bSYour Name hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
1596*5113495bSYour Name hal_tx_vdev_mismatch_routing_set_generic_be;
1597*5113495bSYour Name hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
1598*5113495bSYour Name hal_tx_mcast_mlo_reinject_routing_set_generic_be;
1599*5113495bSYour Name hal_soc->ops->hal_get_ba_aging_timeout =
1600*5113495bSYour Name hal_get_ba_aging_timeout_be_generic;
1601*5113495bSYour Name hal_soc->ops->hal_setup_link_idle_list =
1602*5113495bSYour Name hal_setup_link_idle_list_generic_be;
1603*5113495bSYour Name hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
1604*5113495bSYour Name hal_cookie_conversion_reg_cfg_generic_be;
1605*5113495bSYour Name hal_soc->ops->hal_set_ba_aging_timeout =
1606*5113495bSYour Name hal_set_ba_aging_timeout_be_generic;
1607*5113495bSYour Name hal_soc->ops->hal_tx_populate_bank_register =
1608*5113495bSYour Name hal_tx_populate_bank_register_be;
1609*5113495bSYour Name hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
1610*5113495bSYour Name hal_tx_vdev_mcast_ctrl_set_be;
1611*5113495bSYour Name hal_soc->ops->hal_get_tsf2_scratch_reg =
1612*5113495bSYour Name hal_get_tsf2_scratch_reg_qca5332;
1613*5113495bSYour Name hal_soc->ops->hal_get_tqm_scratch_reg =
1614*5113495bSYour Name hal_get_tqm_scratch_reg_qca5332;
1615*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
1616*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_wmask_get =
1617*5113495bSYour Name hal_rx_mpdu_start_wmask_get_be;
1618*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_wmask_get =
1619*5113495bSYour Name hal_rx_msdu_end_wmask_get_be;
1620*5113495bSYour Name #endif
1621*5113495bSYour Name };
1622*5113495bSYour Name
1623*5113495bSYour Name struct hal_hw_srng_config hw_srng_table_5332[] = {
1624*5113495bSYour Name /* TODO: max_rings can populated by querying HW capabilities */
1625*5113495bSYour Name { /* REO_DST */
1626*5113495bSYour Name .start_ring_id = HAL_SRNG_REO2SW1,
1627*5113495bSYour Name .max_rings = 8,
1628*5113495bSYour Name .entry_size = sizeof(struct reo_destination_ring) >> 2,
1629*5113495bSYour Name .lmac_ring = FALSE,
1630*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1631*5113495bSYour Name .reg_start = {
1632*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
1633*5113495bSYour Name REO_REG_REG_BASE),
1634*5113495bSYour Name HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
1635*5113495bSYour Name REO_REG_REG_BASE)
1636*5113495bSYour Name },
1637*5113495bSYour Name .reg_size = {
1638*5113495bSYour Name HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
1639*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
1640*5113495bSYour Name HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
1641*5113495bSYour Name HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
1642*5113495bSYour Name },
1643*5113495bSYour Name .max_size =
1644*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
1645*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
1646*5113495bSYour Name },
1647*5113495bSYour Name { /* REO_EXCEPTION */
1648*5113495bSYour Name /* Designating REO2SW0 ring as exception ring. This ring is
1649*5113495bSYour Name * similar to other REO2SW rings though it is named as REO2SW0.
1650*5113495bSYour Name * Any of theREO2SW rings can be used as exception ring.
1651*5113495bSYour Name */
1652*5113495bSYour Name .start_ring_id = HAL_SRNG_REO2SW0,
1653*5113495bSYour Name .max_rings = 1,
1654*5113495bSYour Name .entry_size = sizeof(struct reo_destination_ring) >> 2,
1655*5113495bSYour Name .lmac_ring = FALSE,
1656*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1657*5113495bSYour Name .reg_start = {
1658*5113495bSYour Name HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
1659*5113495bSYour Name REO_REG_REG_BASE),
1660*5113495bSYour Name HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
1661*5113495bSYour Name REO_REG_REG_BASE)
1662*5113495bSYour Name },
1663*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1664*5113495bSYour Name * type are supported
1665*5113495bSYour Name */
1666*5113495bSYour Name .reg_size = {},
1667*5113495bSYour Name .max_size =
1668*5113495bSYour Name HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
1669*5113495bSYour Name HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
1670*5113495bSYour Name },
1671*5113495bSYour Name { /* REO_REINJECT */
1672*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2REO,
1673*5113495bSYour Name .max_rings = 4,
1674*5113495bSYour Name .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1675*5113495bSYour Name .lmac_ring = FALSE,
1676*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1677*5113495bSYour Name .reg_start = {
1678*5113495bSYour Name HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
1679*5113495bSYour Name REO_REG_REG_BASE),
1680*5113495bSYour Name HWIO_REO_R2_SW2REO_RING_HP_ADDR(
1681*5113495bSYour Name REO_REG_REG_BASE)
1682*5113495bSYour Name },
1683*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1684*5113495bSYour Name * type are supported
1685*5113495bSYour Name */
1686*5113495bSYour Name .reg_size = {
1687*5113495bSYour Name HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
1688*5113495bSYour Name HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
1689*5113495bSYour Name HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
1690*5113495bSYour Name HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
1691*5113495bSYour Name },
1692*5113495bSYour Name .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
1693*5113495bSYour Name HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
1694*5113495bSYour Name },
1695*5113495bSYour Name { /* REO_CMD */
1696*5113495bSYour Name .start_ring_id = HAL_SRNG_REO_CMD,
1697*5113495bSYour Name .max_rings = 1,
1698*5113495bSYour Name .entry_size = (sizeof(struct tlv_32_hdr) +
1699*5113495bSYour Name sizeof(struct reo_get_queue_stats)) >> 2,
1700*5113495bSYour Name .lmac_ring = FALSE,
1701*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1702*5113495bSYour Name .reg_start = {
1703*5113495bSYour Name HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
1704*5113495bSYour Name REO_REG_REG_BASE),
1705*5113495bSYour Name HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
1706*5113495bSYour Name REO_REG_REG_BASE),
1707*5113495bSYour Name },
1708*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1709*5113495bSYour Name * type are supported
1710*5113495bSYour Name */
1711*5113495bSYour Name .reg_size = {},
1712*5113495bSYour Name .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1713*5113495bSYour Name HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1714*5113495bSYour Name },
1715*5113495bSYour Name { /* REO_STATUS */
1716*5113495bSYour Name .start_ring_id = HAL_SRNG_REO_STATUS,
1717*5113495bSYour Name .max_rings = 1,
1718*5113495bSYour Name .entry_size = (sizeof(struct tlv_32_hdr) +
1719*5113495bSYour Name sizeof(struct reo_get_queue_stats_status)) >> 2,
1720*5113495bSYour Name .lmac_ring = FALSE,
1721*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1722*5113495bSYour Name .reg_start = {
1723*5113495bSYour Name HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
1724*5113495bSYour Name REO_REG_REG_BASE),
1725*5113495bSYour Name HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
1726*5113495bSYour Name REO_REG_REG_BASE),
1727*5113495bSYour Name },
1728*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1729*5113495bSYour Name * type are supported
1730*5113495bSYour Name */
1731*5113495bSYour Name .reg_size = {},
1732*5113495bSYour Name .max_size =
1733*5113495bSYour Name HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1734*5113495bSYour Name HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1735*5113495bSYour Name },
1736*5113495bSYour Name { /* TCL_DATA */
1737*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2TCL1,
1738*5113495bSYour Name .max_rings = 6,
1739*5113495bSYour Name .entry_size = sizeof(struct tcl_data_cmd) >> 2,
1740*5113495bSYour Name .lmac_ring = FALSE,
1741*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1742*5113495bSYour Name .reg_start = {
1743*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
1744*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1745*5113495bSYour Name HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
1746*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1747*5113495bSYour Name },
1748*5113495bSYour Name .reg_size = {
1749*5113495bSYour Name HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
1750*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
1751*5113495bSYour Name HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
1752*5113495bSYour Name HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
1753*5113495bSYour Name },
1754*5113495bSYour Name .max_size =
1755*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
1756*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
1757*5113495bSYour Name },
1758*5113495bSYour Name { /* TCL_CMD/CREDIT */
1759*5113495bSYour Name /* qca8074v2 and qca5332 uses this ring for data commands */
1760*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2TCL_CMD,
1761*5113495bSYour Name .max_rings = 1,
1762*5113495bSYour Name .entry_size = sizeof(struct tcl_data_cmd) >> 2,
1763*5113495bSYour Name .lmac_ring = FALSE,
1764*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1765*5113495bSYour Name .reg_start = {
1766*5113495bSYour Name HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
1767*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1768*5113495bSYour Name HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
1769*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1770*5113495bSYour Name },
1771*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1772*5113495bSYour Name * type are supported
1773*5113495bSYour Name */
1774*5113495bSYour Name .reg_size = {},
1775*5113495bSYour Name .max_size =
1776*5113495bSYour Name HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
1777*5113495bSYour Name HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
1778*5113495bSYour Name },
1779*5113495bSYour Name { /* TCL_STATUS */
1780*5113495bSYour Name .start_ring_id = HAL_SRNG_TCL_STATUS,
1781*5113495bSYour Name .max_rings = 1,
1782*5113495bSYour Name .entry_size = (sizeof(struct tlv_32_hdr) +
1783*5113495bSYour Name sizeof(struct tcl_status_ring)) >> 2,
1784*5113495bSYour Name .lmac_ring = FALSE,
1785*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1786*5113495bSYour Name .reg_start = {
1787*5113495bSYour Name HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
1788*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1789*5113495bSYour Name HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
1790*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1791*5113495bSYour Name },
1792*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1793*5113495bSYour Name * type are supported
1794*5113495bSYour Name */
1795*5113495bSYour Name .reg_size = {},
1796*5113495bSYour Name .max_size =
1797*5113495bSYour Name HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
1798*5113495bSYour Name HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
1799*5113495bSYour Name },
1800*5113495bSYour Name { /* CE_SRC */
1801*5113495bSYour Name .start_ring_id = HAL_SRNG_CE_0_SRC,
1802*5113495bSYour Name .max_rings = 16,
1803*5113495bSYour Name .entry_size = sizeof(struct ce_src_desc) >> 2,
1804*5113495bSYour Name .lmac_ring = FALSE,
1805*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1806*5113495bSYour Name .reg_start = {
1807*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
1808*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
1809*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
1810*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
1811*5113495bSYour Name },
1812*5113495bSYour Name .reg_size = {
1813*5113495bSYour Name WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
1814*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
1815*5113495bSYour Name WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
1816*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
1817*5113495bSYour Name },
1818*5113495bSYour Name .max_size =
1819*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
1820*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
1821*5113495bSYour Name },
1822*5113495bSYour Name { /* CE_DST */
1823*5113495bSYour Name .start_ring_id = HAL_SRNG_CE_0_DST,
1824*5113495bSYour Name .max_rings = 16,
1825*5113495bSYour Name .entry_size = 8 >> 2,
1826*5113495bSYour Name /*TODO: entry_size above should actually be
1827*5113495bSYour Name * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
1828*5113495bSYour Name * of struct ce_dst_desc in HW header files
1829*5113495bSYour Name */
1830*5113495bSYour Name .lmac_ring = FALSE,
1831*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1832*5113495bSYour Name .reg_start = {
1833*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1834*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1835*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1836*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1837*5113495bSYour Name },
1838*5113495bSYour Name .reg_size = {
1839*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1840*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1841*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1842*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1843*5113495bSYour Name },
1844*5113495bSYour Name .max_size =
1845*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1846*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1847*5113495bSYour Name },
1848*5113495bSYour Name { /* CE_DST_STATUS */
1849*5113495bSYour Name .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
1850*5113495bSYour Name .max_rings = 16,
1851*5113495bSYour Name .entry_size = sizeof(struct ce_stat_desc) >> 2,
1852*5113495bSYour Name .lmac_ring = FALSE,
1853*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1854*5113495bSYour Name .reg_start = {
1855*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
1856*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1857*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
1858*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1859*5113495bSYour Name },
1860*5113495bSYour Name /* TODO: check destination status ring registers */
1861*5113495bSYour Name .reg_size = {
1862*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1863*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1864*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1865*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1866*5113495bSYour Name },
1867*5113495bSYour Name .max_size =
1868*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1869*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1870*5113495bSYour Name },
1871*5113495bSYour Name { /* WBM_IDLE_LINK */
1872*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
1873*5113495bSYour Name .max_rings = 1,
1874*5113495bSYour Name .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
1875*5113495bSYour Name .lmac_ring = FALSE,
1876*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1877*5113495bSYour Name .reg_start = {
1878*5113495bSYour Name HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
1879*5113495bSYour Name HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
1880*5113495bSYour Name },
1881*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1882*5113495bSYour Name * type are supported
1883*5113495bSYour Name */
1884*5113495bSYour Name .reg_size = {},
1885*5113495bSYour Name .max_size =
1886*5113495bSYour Name HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
1887*5113495bSYour Name HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
1888*5113495bSYour Name },
1889*5113495bSYour Name { /* SW2WBM_RELEASE */
1890*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
1891*5113495bSYour Name .max_rings = 1,
1892*5113495bSYour Name .entry_size = sizeof(struct wbm_release_ring) >> 2,
1893*5113495bSYour Name .lmac_ring = FALSE,
1894*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1895*5113495bSYour Name .reg_start = {
1896*5113495bSYour Name HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
1897*5113495bSYour Name HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
1898*5113495bSYour Name },
1899*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1900*5113495bSYour Name * type are supported
1901*5113495bSYour Name */
1902*5113495bSYour Name .reg_size = {},
1903*5113495bSYour Name .max_size =
1904*5113495bSYour Name HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1905*5113495bSYour Name HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1906*5113495bSYour Name },
1907*5113495bSYour Name { /* WBM2SW_RELEASE */
1908*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
1909*5113495bSYour Name .max_rings = 8,
1910*5113495bSYour Name .entry_size = sizeof(struct wbm_release_ring) >> 2,
1911*5113495bSYour Name .lmac_ring = FALSE,
1912*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1913*5113495bSYour Name .reg_start = {
1914*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
1915*5113495bSYour Name WBM_REG_REG_BASE),
1916*5113495bSYour Name HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
1917*5113495bSYour Name WBM_REG_REG_BASE),
1918*5113495bSYour Name },
1919*5113495bSYour Name .reg_size = {
1920*5113495bSYour Name HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
1921*5113495bSYour Name WBM_REG_REG_BASE) -
1922*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
1923*5113495bSYour Name WBM_REG_REG_BASE),
1924*5113495bSYour Name HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
1925*5113495bSYour Name WBM_REG_REG_BASE) -
1926*5113495bSYour Name HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
1927*5113495bSYour Name WBM_REG_REG_BASE),
1928*5113495bSYour Name },
1929*5113495bSYour Name .max_size =
1930*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1931*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1932*5113495bSYour Name },
1933*5113495bSYour Name { /* RXDMA_BUF */
1934*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
1935*5113495bSYour Name #ifdef IPA_OFFLOAD
1936*5113495bSYour Name .max_rings = 3,
1937*5113495bSYour Name #else
1938*5113495bSYour Name .max_rings = 3,
1939*5113495bSYour Name #endif
1940*5113495bSYour Name .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1941*5113495bSYour Name .lmac_ring = TRUE,
1942*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1943*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
1944*5113495bSYour Name * from host
1945*5113495bSYour Name */
1946*5113495bSYour Name .reg_start = {},
1947*5113495bSYour Name .reg_size = {},
1948*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
1949*5113495bSYour Name },
1950*5113495bSYour Name { /* RXDMA_DST */
1951*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
1952*5113495bSYour Name .max_rings = 0,
1953*5113495bSYour Name .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
1954*5113495bSYour Name .lmac_ring = TRUE,
1955*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1956*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
1957*5113495bSYour Name * from host
1958*5113495bSYour Name */
1959*5113495bSYour Name .reg_start = {},
1960*5113495bSYour Name .reg_size = {},
1961*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
1962*5113495bSYour Name },
1963*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
1964*5113495bSYour Name { /* RXDMA_MONITOR_BUF */
1965*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
1966*5113495bSYour Name .max_rings = 1,
1967*5113495bSYour Name .entry_size = sizeof(struct mon_ingress_ring) >> 2,
1968*5113495bSYour Name .lmac_ring = TRUE,
1969*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1970*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
1971*5113495bSYour Name * from host
1972*5113495bSYour Name */
1973*5113495bSYour Name .reg_start = {},
1974*5113495bSYour Name .reg_size = {},
1975*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
1976*5113495bSYour Name },
1977*5113495bSYour Name #else
1978*5113495bSYour Name {},
1979*5113495bSYour Name #endif
1980*5113495bSYour Name { /* RXDMA_MONITOR_STATUS */
1981*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
1982*5113495bSYour Name .max_rings = 0,
1983*5113495bSYour Name .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1984*5113495bSYour Name .lmac_ring = TRUE,
1985*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1986*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
1987*5113495bSYour Name * from host
1988*5113495bSYour Name */
1989*5113495bSYour Name .reg_start = {},
1990*5113495bSYour Name .reg_size = {},
1991*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
1992*5113495bSYour Name },
1993*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
1994*5113495bSYour Name { /* RXDMA_MONITOR_DST */
1995*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
1996*5113495bSYour Name .max_rings = 2,
1997*5113495bSYour Name .entry_size = sizeof(struct mon_destination_ring) >> 2,
1998*5113495bSYour Name .lmac_ring = TRUE,
1999*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2000*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2001*5113495bSYour Name * from host
2002*5113495bSYour Name */
2003*5113495bSYour Name .reg_start = {},
2004*5113495bSYour Name .reg_size = {},
2005*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2006*5113495bSYour Name },
2007*5113495bSYour Name #else
2008*5113495bSYour Name {},
2009*5113495bSYour Name #endif
2010*5113495bSYour Name { /* RXDMA_MONITOR_DESC */
2011*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2012*5113495bSYour Name .max_rings = 0,
2013*5113495bSYour Name .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
2014*5113495bSYour Name .lmac_ring = TRUE,
2015*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2016*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2017*5113495bSYour Name * from host
2018*5113495bSYour Name */
2019*5113495bSYour Name .reg_start = {},
2020*5113495bSYour Name .reg_size = {},
2021*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2022*5113495bSYour Name },
2023*5113495bSYour Name
2024*5113495bSYour Name { /* DIR_BUF_RX_DMA_SRC */
2025*5113495bSYour Name .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2026*5113495bSYour Name /* one ring for spectral, one ring for cfr and
2027*5113495bSYour Name * another one ring for txbf cv upload.
2028*5113495bSYour Name */
2029*5113495bSYour Name .max_rings = 3,
2030*5113495bSYour Name .entry_size = 2,
2031*5113495bSYour Name .lmac_ring = TRUE,
2032*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2033*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2034*5113495bSYour Name * from host
2035*5113495bSYour Name */
2036*5113495bSYour Name .reg_start = {},
2037*5113495bSYour Name .reg_size = {},
2038*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
2039*5113495bSYour Name },
2040*5113495bSYour Name #ifdef WLAN_FEATURE_CIF_CFR
2041*5113495bSYour Name { /* WIFI_POS_SRC */
2042*5113495bSYour Name .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2043*5113495bSYour Name .max_rings = 1,
2044*5113495bSYour Name .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2045*5113495bSYour Name .lmac_ring = TRUE,
2046*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2047*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2048*5113495bSYour Name * from host
2049*5113495bSYour Name */
2050*5113495bSYour Name .reg_start = {},
2051*5113495bSYour Name .reg_size = {},
2052*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2053*5113495bSYour Name },
2054*5113495bSYour Name #endif
2055*5113495bSYour Name /* PPE rings are not present in Miami. Added dummy entries to preserve
2056*5113495bSYour Name * Array Index
2057*5113495bSYour Name */
2058*5113495bSYour Name /* REO2PPE */
2059*5113495bSYour Name {},
2060*5113495bSYour Name /* PPE2TCL */
2061*5113495bSYour Name {},
2062*5113495bSYour Name /* PPE_RELEASE */
2063*5113495bSYour Name {},
2064*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_TX_2_0
2065*5113495bSYour Name { /* TX_MONITOR_BUF */
2066*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
2067*5113495bSYour Name .max_rings = 1,
2068*5113495bSYour Name .entry_size = sizeof(struct mon_ingress_ring) >> 2,
2069*5113495bSYour Name .lmac_ring = TRUE,
2070*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2071*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2072*5113495bSYour Name * from host
2073*5113495bSYour Name */
2074*5113495bSYour Name .reg_start = {},
2075*5113495bSYour Name .reg_size = {},
2076*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2077*5113495bSYour Name },
2078*5113495bSYour Name { /* TX_MONITOR_DST */
2079*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
2080*5113495bSYour Name .max_rings = 2,
2081*5113495bSYour Name .entry_size = sizeof(struct mon_destination_ring) >> 2,
2082*5113495bSYour Name .lmac_ring = TRUE,
2083*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2084*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2085*5113495bSYour Name * from host
2086*5113495bSYour Name */
2087*5113495bSYour Name .reg_start = {},
2088*5113495bSYour Name .reg_size = {},
2089*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2090*5113495bSYour Name },
2091*5113495bSYour Name #else
2092*5113495bSYour Name {},
2093*5113495bSYour Name {},
2094*5113495bSYour Name #endif
2095*5113495bSYour Name { /* SW2RXDMA */
2096*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
2097*5113495bSYour Name .max_rings = 3,
2098*5113495bSYour Name .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2099*5113495bSYour Name .lmac_ring = TRUE,
2100*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2101*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2102*5113495bSYour Name * from host
2103*5113495bSYour Name */
2104*5113495bSYour Name .reg_start = {},
2105*5113495bSYour Name .reg_size = {},
2106*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2107*5113495bSYour Name .dmac_cmn_ring = TRUE,
2108*5113495bSYour Name },
2109*5113495bSYour Name { /* SW2RXDMA_LINK_RELEASE */ 0},
2110*5113495bSYour Name };
2111*5113495bSYour Name
2112*5113495bSYour Name /**
2113*5113495bSYour Name * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset
2114*5113495bSYour Name * applicable only for qca5332
2115*5113495bSYour Name * @hal_soc: HAL Soc handle
2116*5113495bSYour Name *
2117*5113495bSYour Name * Return: None
2118*5113495bSYour Name */
hal_srng_hw_reg_offset_init_qca5332(struct hal_soc * hal_soc)2119*5113495bSYour Name static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc)
2120*5113495bSYour Name {
2121*5113495bSYour Name int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2122*5113495bSYour Name
2123*5113495bSYour Name hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
2124*5113495bSYour Name hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
2125*5113495bSYour Name hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
2126*5113495bSYour Name hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
2127*5113495bSYour Name REG_OFFSET(DST, PRODUCER_INT2_SETUP);
2128*5113495bSYour Name }
2129*5113495bSYour Name
2130*5113495bSYour Name /**
2131*5113495bSYour Name * hal_qca5332_attach() - Attach 5332 target specific hal_soc ops,
2132*5113495bSYour Name * offset and srng table
2133*5113495bSYour Name * @hal_soc: hal_soc handle
2134*5113495bSYour Name *
2135*5113495bSYour Name * Return: void
2136*5113495bSYour Name */
hal_qca5332_attach(struct hal_soc * hal_soc)2137*5113495bSYour Name void hal_qca5332_attach(struct hal_soc *hal_soc)
2138*5113495bSYour Name {
2139*5113495bSYour Name hal_soc->hw_srng_table = hw_srng_table_5332;
2140*5113495bSYour Name
2141*5113495bSYour Name hal_srng_hw_reg_offset_init_generic(hal_soc);
2142*5113495bSYour Name hal_srng_hw_reg_offset_init_qca5332(hal_soc);
2143*5113495bSYour Name
2144*5113495bSYour Name hal_hw_txrx_default_ops_attach_be(hal_soc);
2145*5113495bSYour Name hal_hw_txrx_ops_attach_qca5332(hal_soc);
2146*5113495bSYour Name hal_soc->dmac_cmn_src_rxbuf_ring = true;
2147*5113495bSYour Name }
2148