1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4*5113495bSYour Name * 5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 6*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 7*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16*5113495bSYour Name */ 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _HAL_5332_RX_H_ 19*5113495bSYour Name #define _HAL_5332_RX_H_ 20*5113495bSYour Name #include "qdf_util.h" 21*5113495bSYour Name #include "qdf_types.h" 22*5113495bSYour Name #include "qdf_lock.h" 23*5113495bSYour Name #include "qdf_mem.h" 24*5113495bSYour Name #include "qdf_nbuf.h" 25*5113495bSYour Name #include "tcl_data_cmd.h" 26*5113495bSYour Name #include "phyrx_rssi_legacy.h" 27*5113495bSYour Name #include "rx_msdu_start.h" 28*5113495bSYour Name #include "tlv_tag_def.h" 29*5113495bSYour Name #include "hal_hw_headers.h" 30*5113495bSYour Name #include "hal_internal.h" 31*5113495bSYour Name #include "cdp_txrx_mon_struct.h" 32*5113495bSYour Name #include "qdf_trace.h" 33*5113495bSYour Name #include "hal_rx.h" 34*5113495bSYour Name #include "hal_tx.h" 35*5113495bSYour Name #include "dp_types.h" 36*5113495bSYour Name #include "hal_api_mon.h" 37*5113495bSYour Name #include "phyrx_other_receive_info_ru_details.h" 38*5113495bSYour Name 39*5113495bSYour Name #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ 40*5113495bSYour Name (uint8_t *)(link_desc_va) + \ 41*5113495bSYour Name RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 42*5113495bSYour Name 43*5113495bSYour Name #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \ 44*5113495bSYour Name (uint8_t *)(msdu0) + \ 45*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 46*5113495bSYour Name 47*5113495bSYour Name #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \ 48*5113495bSYour Name (uint8_t *)(ent_ring_desc) + \ 49*5113495bSYour Name RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 50*5113495bSYour Name 51*5113495bSYour Name #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \ 52*5113495bSYour Name (uint8_t *)(dst_ring_desc) + \ 53*5113495bSYour Name REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 54*5113495bSYour Name 55*5113495bSYour Name #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ 56*5113495bSYour Name HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID) 57*5113495bSYour Name 58*5113495bSYour Name #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ 59*5113495bSYour Name HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID) 60*5113495bSYour Name 61*5113495bSYour Name /* 62*5113495bSYour Name * In Beryllium chipset msdu_start was removed and merged in msdu_end. 63*5113495bSYour Name * Due to this valid contents will be present only in last msdu. 64*5113495bSYour Name * After setting the 5th bit of spare control field, REO will copy the contents 65*5113495bSYour Name * from last buffer to all the other buffers of MSDU. 66*5113495bSYour Name */ 67*5113495bSYour Name #define HAL_REO_MSDU_END_COPY 0x20 68*5113495bSYour Name #define HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 69*5113495bSYour Name 70*5113495bSYour Name #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \ 71*5113495bSYour Name do { \ 72*5113495bSYour Name reg_val &= \ 73*5113495bSYour Name ~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\ 74*5113495bSYour Name HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \ 75*5113495bSYour Name reg_val |= \ 76*5113495bSYour Name HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 77*5113495bSYour Name AGING_LIST_ENABLE, 1) | \ 78*5113495bSYour Name HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \ 79*5113495bSYour Name AGING_FLUSH_ENABLE, 1); \ 80*5113495bSYour Name HAL_REG_WRITE(soc, \ 81*5113495bSYour Name HWIO_REO_R0_GENERAL_ENABLE_ADDR( \ 82*5113495bSYour Name REO_REG_REG_BASE), \ 83*5113495bSYour Name reg_val); \ 84*5113495bSYour Name reg_val = HAL_REG_READ(soc, \ 85*5113495bSYour Name HWIO_REO_R0_MISC_CTL_ADDR( \ 86*5113495bSYour Name REO_REG_REG_BASE)); \ 87*5113495bSYour Name reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \ 88*5113495bSYour Name reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \ 89*5113495bSYour Name FRAGMENT_DEST_RING, \ 90*5113495bSYour Name (reo_params)->frag_dst_ring); \ 91*5113495bSYour Name reg_val |= ((HAL_REO_MSDU_END_COPY) << \ 92*5113495bSYour Name HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT); \ 93*5113495bSYour Name HAL_REG_WRITE(soc, \ 94*5113495bSYour Name HWIO_REO_R0_MISC_CTL_ADDR(REO_REG_REG_BASE), \ 95*5113495bSYour Name reg_val); \ 96*5113495bSYour Name } while (0) 97*5113495bSYour Name 98*5113495bSYour Name #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ 99*5113495bSYour Name ((struct rx_msdu_desc_info *) \ 100*5113495bSYour Name _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ 101*5113495bSYour Name UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) 102*5113495bSYour Name 103*5113495bSYour Name #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \ 104*5113495bSYour Name HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy 105*5113495bSYour Name 106*5113495bSYour Name #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ 107*5113495bSYour Name ((struct rx_msdu_details *) \ 108*5113495bSYour Name _OFFSET_TO_BYTE_PTR((link_desc),\ 109*5113495bSYour Name RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) 110*5113495bSYour Name 111*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 112*5113495bSYour Name #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006 113*5113495bSYour Name #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1 114*5113495bSYour Name #define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2 115*5113495bSYour Name 116*5113495bSYour Name #define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \ 117*5113495bSYour Name ((HAL_RX_GET((rx_tlv), \ 118*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \ 119*5113495bSYour Name RTT_CFR_STATUS) & \ 120*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \ 121*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB) 122*5113495bSYour Name #endif 123*5113495bSYour Name #endif 124