xref: /wlan-driver/qca-wifi-host-cmn/hal/wifi3.0/qca8074v2/hal_8074v2_tx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for
6  * any purpose with or without fee is hereby granted, provided that the
7  * above copyright notice and this permission notice appear in all
8  * copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17  * PERFORMANCE OF THIS SOFTWARE.
18  */
19 #include "hal_hw_headers.h"
20 #include "hal_internal.h"
21 #include "cdp_txrx_mon_struct.h"
22 #include "qdf_trace.h"
23 #include "hal_rx.h"
24 #include "hal_tx.h"
25 #include "dp_types.h"
26 #include "hal_api_mon.h"
27 
28 /**
29  * hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion
30  *						table ID
31  * @desc: Handle to Tx Descriptor
32  * @id: DSCP to tid conversion table to be used for this frame
33  *
34  * Return: void
35  */
36 
hal_tx_desc_set_dscp_tid_table_id_8074v2(void * desc,uint8_t id)37 static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id)
38 {
39 	HAL_SET_FLD(desc, TCL_DATA_CMD_5,
40 			DSCP_TID_TABLE_NUM) |=
41 		HAL_TX_SM(TCL_DATA_CMD_5,
42 				DSCP_TID_TABLE_NUM, id);
43 }
44 
45 
46 #define DSCP_TID_TABLE_SIZE 24
47 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
48 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
49 /**
50  * hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table
51  * @soc: HAL SoC context
52  * @map: DSCP-TID mapping table
53  * @id: mapping table ID - 0,1
54  *
55  * DSCP are mapped to 8 TID values using TID values programmed
56  * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
57  * and DSCP_TID2_MAP_<0 to 6> (id = 1)
58  * Each mapping register has TID mapping for 10 DSCP values
59  *
60  * Return: none
61  */
hal_tx_set_dscp_tid_map_8074v2(struct hal_soc * soc,uint8_t * map,uint8_t id)62 static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc,
63 					   uint8_t *map,
64 					   uint8_t id)
65 {
66 	int i;
67 	uint32_t addr, cmn_reg_addr;
68 	uint32_t value = 0, regval;
69 	uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
70 
71 	if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS)
72 		return;
73 
74 	cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
75 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
76 
77 	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
78 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
79 				id * NUM_WORDS_PER_DSCP_TID_TABLE);
80 
81 	/* Enable read/write access */
82 	regval = HAL_REG_READ(soc, cmn_reg_addr);
83 	regval |=
84 	(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
85 
86 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
87 
88 	/* Write 8 (24 bits) DSCP-TID mappings in each iteration */
89 	for (i = 0; i < 64; i += 8) {
90 		value = (map[i] |
91 			(map[i + 1] << 0x3) |
92 			(map[i + 2] << 0x6) |
93 			(map[i + 3] << 0x9) |
94 			(map[i + 4] << 0xc) |
95 			(map[i + 5] << 0xf) |
96 			(map[i + 6] << 0x12) |
97 			(map[i + 7] << 0x15));
98 
99 		qdf_mem_copy(&val[cnt], &value, 3);
100 		cnt += 3;
101 	}
102 
103 	for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
104 		regval = *(uint32_t *)(val + i);
105 		HAL_REG_WRITE(soc, addr,
106 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
107 		addr += 4;
108 	}
109 
110 	/* Disable read/write access */
111 	regval = HAL_REG_READ(soc, cmn_reg_addr);
112 	regval &=
113 	~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
114 
115 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
116 }
117 
118 /**
119  * hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as
120  *                                   updated by user
121  * @soc: HAL SoC context
122  * @tid: TID
123  * @id : MAP ID
124  * @dscp: DSCP
125  *
126  * Return: void
127  */
hal_tx_update_dscp_tid_8074v2(struct hal_soc * soc,uint8_t tid,uint8_t id,uint8_t dscp)128 static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid,
129 					  uint8_t id, uint8_t dscp)
130 {
131 	uint32_t addr, addr1, cmn_reg_addr, regmask = 0xFFFFFFFF;
132 	uint32_t start_value = 0, end_value = 0;
133 	uint32_t regval;
134 	uint8_t end_bits = 0;
135 	uint8_t start_bits = 0;
136 	uint32_t start_index, end_index;
137 	cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
138 					SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
139 
140 	addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
141 				SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
142 				id * NUM_WORDS_PER_DSCP_TID_TABLE);
143 
144 	start_index = dscp * HAL_TX_BITS_PER_TID;
145 	end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
146 		    % HAL_TX_NUM_DSCP_REGISTER_SIZE;
147 	start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
148 	addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
149 			HAL_TX_NUM_DSCP_REGISTER_SIZE));
150 
151 	if (end_index < start_index) {
152 		end_bits = end_index + 1;
153 		start_bits = HAL_TX_BITS_PER_TID - end_bits;
154 		start_value = tid << start_index;
155 		end_value = tid >> start_bits;
156 		addr1 = addr + 4;
157 	} else {
158 		start_bits = HAL_TX_BITS_PER_TID - end_bits;
159 		start_value = tid << start_index;
160 		addr1 = 0;
161 	}
162 
163 	/* Enable read/write access */
164 	regval = HAL_REG_READ(soc, cmn_reg_addr);
165 	regval |=
166 	(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
167 
168 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
169 
170 	regval = HAL_REG_READ(soc, addr);
171 
172 	if (end_index < start_index)
173 		regval &= (regmask >> start_bits);
174 	else
175 		regval &= ~(7 << start_index);
176 
177 	regval |= start_value;
178 
179 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
180 
181 	if (addr1) {
182 		regval = HAL_REG_READ(soc, addr1);
183 		regval &= (~0) << end_bits;
184 		regval |= end_value;
185 
186 		HAL_REG_WRITE(soc, addr1, (regval &
187 			     HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
188 	}
189 
190 	/* Disable read/write access */
191 	regval = HAL_REG_READ(soc, cmn_reg_addr);
192 	regval &=
193 	~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
194 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);
195 }
196 
197 /**
198  * hal_tx_desc_set_lmac_id_8074v2() - Set the lmac_id value
199  * @desc: Handle to Tx Descriptor
200  * @lmac_id: mac Id to ast matching
201  *		     b00 – mac 0
202  *		     b01 – mac 1
203  *		     b10 – mac 2
204  *		     b11 – all macs (legacy HK way)
205  *
206  * Return: void
207  */
hal_tx_desc_set_lmac_id_8074v2(void * desc,uint8_t lmac_id)208 static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id)
209 {
210 	HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
211 		HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
212 }
213 
214 /**
215  * hal_tx_init_cmd_credit_ring_8074v2() - Initialize command/credit SRNG
216  * @hal_soc_hdl: Handle to HAL SoC structure
217  * @hal_ring_hdl: Handle to HAL SRNG structure
218  *
219  * Return: none
220  */
hal_tx_init_cmd_credit_ring_8074v2(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)221 static inline void hal_tx_init_cmd_credit_ring_8074v2(hal_soc_handle_t hal_soc_hdl,
222 						      hal_ring_handle_t hal_ring_hdl)
223 {
224 	uint8_t *desc_addr;
225 	struct hal_srng_params srng_params;
226 	uint32_t desc_size;
227 	uint32_t num_desc;
228 
229 	hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params);
230 
231 	desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
232 	desc_size = sizeof(struct tcl_data_cmd);
233 	num_desc = srng_params.num_entries;
234 
235 	while (num_desc) {
236 		/* using CMD/CREDIT Ring to send DATA CMD tag */
237 		HAL_TX_DESC_SET_TLV_HDR(desc_addr, WIFITCL_DATA_CMD_E,
238 					desc_size);
239 		desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
240 		num_desc--;
241 	}
242 }
243