1*5113495bSYour Name /*
2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4*5113495bSYour Name *
5*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any
6*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above
7*5113495bSYour Name * copyright notice and this permission notice appear in all copies.
8*5113495bSYour Name *
9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
16*5113495bSYour Name */
17*5113495bSYour Name #include "qdf_types.h"
18*5113495bSYour Name #include "qdf_util.h"
19*5113495bSYour Name #include "qdf_mem.h"
20*5113495bSYour Name #include "qdf_nbuf.h"
21*5113495bSYour Name #include "qdf_module.h"
22*5113495bSYour Name
23*5113495bSYour Name #include "target_type.h"
24*5113495bSYour Name #include "wcss_version.h"
25*5113495bSYour Name
26*5113495bSYour Name #include "hal_be_hw_headers.h"
27*5113495bSYour Name #include "hal_internal.h"
28*5113495bSYour Name #include "hal_api.h"
29*5113495bSYour Name #include "hal_flow.h"
30*5113495bSYour Name #include "rx_flow_search_entry.h"
31*5113495bSYour Name #include "hal_rx_flow_info.h"
32*5113495bSYour Name #include "hal_be_api.h"
33*5113495bSYour Name #include "tcl_entrance_from_ppe_ring.h"
34*5113495bSYour Name #include "sw_monitor_ring.h"
35*5113495bSYour Name #include "wcss_seq_hwioreg_umac.h"
36*5113495bSYour Name #include "wfss_ce_reg_seq_hwioreg.h"
37*5113495bSYour Name #include <uniform_reo_status_header.h>
38*5113495bSYour Name #include <wbm_release_ring_tx.h>
39*5113495bSYour Name #include <phyrx_location.h>
40*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \
41*5113495bSYour Name defined(WLAN_PKT_CAPTURE_RX_2_0)
42*5113495bSYour Name #include <mon_ingress_ring.h>
43*5113495bSYour Name #include <mon_destination_ring.h>
44*5113495bSYour Name #endif
45*5113495bSYour Name #include "rx_reo_queue_1k.h"
46*5113495bSYour Name
47*5113495bSYour Name #include <hal_be_rx.h>
48*5113495bSYour Name
49*5113495bSYour Name #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
50*5113495bSYour Name RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
51*5113495bSYour Name #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
52*5113495bSYour Name RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
53*5113495bSYour Name #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
54*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
55*5113495bSYour Name #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
56*5113495bSYour Name RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
57*5113495bSYour Name #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
58*5113495bSYour Name REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
59*5113495bSYour Name #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
60*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER
61*5113495bSYour Name #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
62*5113495bSYour Name STATUS_HEADER_TIMESTAMP
63*5113495bSYour Name #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
64*5113495bSYour Name RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
65*5113495bSYour Name #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
66*5113495bSYour Name RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
67*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
68*5113495bSYour Name TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
69*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
70*5113495bSYour Name TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
71*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
72*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
73*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
74*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
75*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
76*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
77*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
78*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
79*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
80*5113495bSYour Name BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
81*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
82*5113495bSYour Name BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
83*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
84*5113495bSYour Name BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
85*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
86*5113495bSYour Name BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
87*5113495bSYour Name #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
88*5113495bSYour Name BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
89*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
90*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
91*5113495bSYour Name #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
92*5113495bSYour Name TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
93*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
94*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
95*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
96*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
97*5113495bSYour Name #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
98*5113495bSYour Name WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
99*5113495bSYour Name
100*5113495bSYour Name #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0)
101*5113495bSYour Name #include "hal_be_api_mon.h"
102*5113495bSYour Name #endif
103*5113495bSYour Name
104*5113495bSYour Name #define CMEM_REG_BASE 0x00100000
105*5113495bSYour Name
106*5113495bSYour Name #define CE_WINDOW_ADDRESS_6432 \
107*5113495bSYour Name ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
108*5113495bSYour Name
109*5113495bSYour Name #define UMAC_WINDOW_ADDRESS_6432 \
110*5113495bSYour Name ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
111*5113495bSYour Name
112*5113495bSYour Name #define WINDOW_CONFIGURATION_VALUE_6432 \
113*5113495bSYour Name ((CE_WINDOW_ADDRESS_6432 << 6) |\
114*5113495bSYour Name (UMAC_WINDOW_ADDRESS_6432 << 12) | \
115*5113495bSYour Name WINDOW_ENABLE_BIT)
116*5113495bSYour Name
117*5113495bSYour Name /* For Berryllium sw2rxdma ring size increased to 20 bits */
118*5113495bSYour Name #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
119*5113495bSYour Name
120*5113495bSYour Name #include "hal_6432_rx.h"
121*5113495bSYour Name #include "hal_6432_tx.h"
122*5113495bSYour Name #include "hal_be_rx_tlv.h"
123*5113495bSYour Name #include <hal_be_generic_api.h>
124*5113495bSYour Name
125*5113495bSYour Name #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
126*5113495bSYour Name #define PMM_REG_BASE_QCN6432 0xB500FC
127*5113495bSYour Name
128*5113495bSYour Name /**
129*5113495bSYour Name * hal_get_link_desc_size_6432(): API to get the link desc size
130*5113495bSYour Name *
131*5113495bSYour Name * Return: uint32_t
132*5113495bSYour Name */
hal_get_link_desc_size_6432(void)133*5113495bSYour Name static uint32_t hal_get_link_desc_size_6432(void)
134*5113495bSYour Name {
135*5113495bSYour Name return LINK_DESC_SIZE;
136*5113495bSYour Name }
137*5113495bSYour Name
138*5113495bSYour Name /**
139*5113495bSYour Name * hal_rx_get_tlv_6432(): API to get the tlv
140*5113495bSYour Name *
141*5113495bSYour Name * @rx_tlv: TLV data extracted from the rx packet
142*5113495bSYour Name * Return: uint8_t
143*5113495bSYour Name */
hal_rx_get_tlv_6432(void * rx_tlv)144*5113495bSYour Name static uint8_t hal_rx_get_tlv_6432(void *rx_tlv)
145*5113495bSYour Name {
146*5113495bSYour Name return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
147*5113495bSYour Name }
148*5113495bSYour Name
149*5113495bSYour Name /**
150*5113495bSYour Name * hal_rx_wbm_err_msdu_continuation_get_6432 () - API to check if WBM
151*5113495bSYour Name * msdu continuation bit is set
152*5113495bSYour Name *
153*5113495bSYour Name *@wbm_desc: wbm release ring descriptor
154*5113495bSYour Name *
155*5113495bSYour Name * Return: true if msdu continuation bit is set.
156*5113495bSYour Name */
hal_rx_wbm_err_msdu_continuation_get_6432(void * wbm_desc)157*5113495bSYour Name uint8_t hal_rx_wbm_err_msdu_continuation_get_6432(void *wbm_desc)
158*5113495bSYour Name {
159*5113495bSYour Name uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
160*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
161*5113495bSYour Name
162*5113495bSYour Name return (comp_desc &
163*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
164*5113495bSYour Name WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
165*5113495bSYour Name }
166*5113495bSYour Name
167*5113495bSYour Name #if 0 // check this registration for MLO
168*5113495bSYour Name /**
169*5113495bSYour Name * hal_read_pmm_scratch_reg_5332(): API to read PMM Scratch register
170*5113495bSYour Name *
171*5113495bSYour Name * @soc: HAL soc
172*5113495bSYour Name * @reg_enum: Enum of the scratch register
173*5113495bSYour Name *
174*5113495bSYour Name * Return: uint32_t
175*5113495bSYour Name */
176*5113495bSYour Name static inline
177*5113495bSYour Name uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc,
178*5113495bSYour Name enum hal_scratch_reg_enum reg_enum)
179*5113495bSYour Name {
180*5113495bSYour Name uint32_t val = 0;
181*5113495bSYour Name void __iomem *bar;
182*5113495bSYour Name
183*5113495bSYour Name bar = ioremap_nocache(PMM_SCRATCH_BASE_QCA5332, PMM_SCRATCH_SIZE);
184*5113495bSYour Name pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val, bar);
185*5113495bSYour Name iounmap(bar);
186*5113495bSYour Name return val;
187*5113495bSYour Name }
188*5113495bSYour Name
189*5113495bSYour Name /**
190*5113495bSYour Name * hal_get_tsf2_scratch_reg_qca5332(): API to read tsf2 scratch register
191*5113495bSYour Name *
192*5113495bSYour Name * @hal_soc_hdl: HAL soc context
193*5113495bSYour Name * @mac_id: mac id
194*5113495bSYour Name * @value: Pointer to update tsf2 value
195*5113495bSYour Name *
196*5113495bSYour Name * Return: void
197*5113495bSYour Name */
198*5113495bSYour Name static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
199*5113495bSYour Name uint8_t mac_id, uint64_t *value)
200*5113495bSYour Name {
201*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
202*5113495bSYour Name uint32_t offset_lo, offset_hi;
203*5113495bSYour Name enum hal_scratch_reg_enum enum_lo, enum_hi;
204*5113495bSYour Name
205*5113495bSYour Name hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
206*5113495bSYour Name
207*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg_5332(soc, enum_lo);
208*5113495bSYour Name
209*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg_5332(soc, enum_hi);
210*5113495bSYour Name
211*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
212*5113495bSYour Name }
213*5113495bSYour Name
214*5113495bSYour Name /**
215*5113495bSYour Name * hal_get_tqm_scratch_reg_qca5332(): API to read tqm scratch register
216*5113495bSYour Name *
217*5113495bSYour Name * @hal_soc_hdl: HAL soc context
218*5113495bSYour Name * @value: Pointer to update tqm value
219*5113495bSYour Name *
220*5113495bSYour Name * Return: void
221*5113495bSYour Name */
222*5113495bSYour Name static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
223*5113495bSYour Name uint64_t *value)
224*5113495bSYour Name {
225*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
226*5113495bSYour Name uint32_t offset_lo, offset_hi;
227*5113495bSYour Name
228*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg_5332(soc,
229*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_LO_US);
230*5113495bSYour Name
231*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg_5332(soc,
232*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_HI_US);
233*5113495bSYour Name
234*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
235*5113495bSYour Name }
236*5113495bSYour Name #endif
237*5113495bSYour Name /**
238*5113495bSYour Name * hal_rx_proc_phyrx_other_receive_info_tlv_6432(): API to get tlv info
239*5113495bSYour Name *
240*5113495bSYour Name * @rx_tlv_hdr: start address of rx_pkt_tlvs
241*5113495bSYour Name * @ppdu_info_hdl: PPDU info handle to fill
242*5113495bSYour Name *
243*5113495bSYour Name * Return: uint32_t
244*5113495bSYour Name */
245*5113495bSYour Name static inline
hal_rx_proc_phyrx_other_receive_info_tlv_6432(void * rx_tlv_hdr,void * ppdu_info_hdl)246*5113495bSYour Name void hal_rx_proc_phyrx_other_receive_info_tlv_6432(void *rx_tlv_hdr,
247*5113495bSYour Name void *ppdu_info_hdl)
248*5113495bSYour Name {
249*5113495bSYour Name uint32_t tlv_tag, tlv_len;
250*5113495bSYour Name uint32_t temp_len, other_tlv_len, other_tlv_tag;
251*5113495bSYour Name void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
252*5113495bSYour Name void *other_tlv_hdr = NULL;
253*5113495bSYour Name void *other_tlv = NULL;
254*5113495bSYour Name
255*5113495bSYour Name tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
256*5113495bSYour Name tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
257*5113495bSYour Name temp_len = 0;
258*5113495bSYour Name
259*5113495bSYour Name other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
260*5113495bSYour Name other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
261*5113495bSYour Name other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
262*5113495bSYour Name
263*5113495bSYour Name temp_len += other_tlv_len;
264*5113495bSYour Name other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
265*5113495bSYour Name
266*5113495bSYour Name switch (other_tlv_tag) {
267*5113495bSYour Name default:
268*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
269*5113495bSYour Name "%s unhandled TLV type: %d, TLV len:%d",
270*5113495bSYour Name __func__, other_tlv_tag, other_tlv_len);
271*5113495bSYour Name break;
272*5113495bSYour Name }
273*5113495bSYour Name }
274*5113495bSYour Name
275*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
276*5113495bSYour Name static inline
hal_rx_get_bb_info_6432(void * rx_tlv,void * ppdu_info_hdl)277*5113495bSYour Name void hal_rx_get_bb_info_6432(void *rx_tlv, void *ppdu_info_hdl)
278*5113495bSYour Name {
279*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
280*5113495bSYour Name
281*5113495bSYour Name ppdu_info->cfr_info.bb_captured_channel =
282*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
283*5113495bSYour Name
284*5113495bSYour Name ppdu_info->cfr_info.bb_captured_timeout =
285*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
286*5113495bSYour Name
287*5113495bSYour Name ppdu_info->cfr_info.bb_captured_reason =
288*5113495bSYour Name HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
289*5113495bSYour Name }
290*5113495bSYour Name
291*5113495bSYour Name static inline
hal_rx_get_rtt_info_6432(void * rx_tlv,void * ppdu_info_hdl)292*5113495bSYour Name void hal_rx_get_rtt_info_6432(void *rx_tlv, void *ppdu_info_hdl)
293*5113495bSYour Name {
294*5113495bSYour Name struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
295*5113495bSYour Name
296*5113495bSYour Name ppdu_info->cfr_info.rx_location_info_valid =
297*5113495bSYour Name HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
298*5113495bSYour Name RX_LOCATION_INFO_VALID);
299*5113495bSYour Name
300*5113495bSYour Name ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
301*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
302*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
303*5113495bSYour Name RTT_CHE_BUFFER_POINTER_LOW32);
304*5113495bSYour Name
305*5113495bSYour Name ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
306*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
307*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
308*5113495bSYour Name RTT_CHE_BUFFER_POINTER_HIGH8);
309*5113495bSYour Name
310*5113495bSYour Name ppdu_info->cfr_info.chan_capture_status =
311*5113495bSYour Name HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
312*5113495bSYour Name
313*5113495bSYour Name ppdu_info->cfr_info.rx_start_ts =
314*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
315*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
316*5113495bSYour Name RX_START_TS);
317*5113495bSYour Name
318*5113495bSYour Name ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
319*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
320*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
321*5113495bSYour Name RTT_CFO_MEASUREMENT);
322*5113495bSYour Name
323*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info0 =
324*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
325*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
326*5113495bSYour Name GAIN_CHAIN0);
327*5113495bSYour Name
328*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info0 |=
329*5113495bSYour Name (((uint32_t)HAL_RX_GET_64(rx_tlv,
330*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
331*5113495bSYour Name GAIN_CHAIN1)) << 16);
332*5113495bSYour Name
333*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info1 =
334*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
335*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
336*5113495bSYour Name GAIN_CHAIN2);
337*5113495bSYour Name
338*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info1 |=
339*5113495bSYour Name (((uint32_t)HAL_RX_GET_64(rx_tlv,
340*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
341*5113495bSYour Name GAIN_CHAIN3)) << 16);
342*5113495bSYour Name
343*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info2 = 0;
344*5113495bSYour Name
345*5113495bSYour Name ppdu_info->cfr_info.agc_gain_info3 = 0;
346*5113495bSYour Name
347*5113495bSYour Name ppdu_info->cfr_info.mcs_rate =
348*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
349*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
350*5113495bSYour Name RTT_MCS_RATE);
351*5113495bSYour Name
352*5113495bSYour Name ppdu_info->cfr_info.gi_type =
353*5113495bSYour Name HAL_RX_GET_64(rx_tlv,
354*5113495bSYour Name PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
355*5113495bSYour Name RTT_GI_TYPE);
356*5113495bSYour Name }
357*5113495bSYour Name #endif
358*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
359*5113495bSYour Name /**
360*5113495bSYour Name * hal_rx_dump_mpdu_start_tlv_6432() - dump RX mpdu_start TLV in structured
361*5113495bSYour Name * human readable format.
362*5113495bSYour Name * @mpdustart: pointer the rx_attention TLV in pkt.
363*5113495bSYour Name * @dbg_level: log level.
364*5113495bSYour Name *
365*5113495bSYour Name * Return: void
366*5113495bSYour Name */
hal_rx_dump_mpdu_start_tlv_6432(void * mpdustart,uint8_t dbg_level)367*5113495bSYour Name static inline void hal_rx_dump_mpdu_start_tlv_6432(void *mpdustart,
368*5113495bSYour Name uint8_t dbg_level)
369*5113495bSYour Name {
370*5113495bSYour Name struct rx_mpdu_start_compact *mpdu_info =
371*5113495bSYour Name (struct rx_mpdu_start_compact *)mpdustart;
372*5113495bSYour Name
373*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
374*5113495bSYour Name "rx_mpdu_start tlv (1/5) - "
375*5113495bSYour Name "rx_reo_queue_desc_addr_39_32 :%x"
376*5113495bSYour Name "receive_queue_number:%x "
377*5113495bSYour Name "pre_delim_err_warning:%x "
378*5113495bSYour Name "first_delim_err:%x "
379*5113495bSYour Name "pn_31_0:%x "
380*5113495bSYour Name "pn_63_32:%x "
381*5113495bSYour Name "pn_95_64:%x ",
382*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_39_32,
383*5113495bSYour Name mpdu_info->receive_queue_number,
384*5113495bSYour Name mpdu_info->pre_delim_err_warning,
385*5113495bSYour Name mpdu_info->first_delim_err,
386*5113495bSYour Name mpdu_info->pn_31_0,
387*5113495bSYour Name mpdu_info->pn_63_32,
388*5113495bSYour Name mpdu_info->pn_95_64);
389*5113495bSYour Name
390*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
391*5113495bSYour Name "rx_mpdu_start tlv (2/5) - "
392*5113495bSYour Name "ast_index:%x "
393*5113495bSYour Name "sw_peer_id:%x "
394*5113495bSYour Name "mpdu_frame_control_valid:%x "
395*5113495bSYour Name "mpdu_duration_valid:%x "
396*5113495bSYour Name "mac_addr_ad1_valid:%x "
397*5113495bSYour Name "mac_addr_ad2_valid:%x "
398*5113495bSYour Name "mac_addr_ad3_valid:%x "
399*5113495bSYour Name "mac_addr_ad4_valid:%x "
400*5113495bSYour Name "mpdu_sequence_control_valid :%x"
401*5113495bSYour Name "mpdu_qos_control_valid:%x "
402*5113495bSYour Name "mpdu_ht_control_valid:%x "
403*5113495bSYour Name "frame_encryption_info_valid :%x",
404*5113495bSYour Name mpdu_info->ast_index,
405*5113495bSYour Name mpdu_info->sw_peer_id,
406*5113495bSYour Name mpdu_info->mpdu_frame_control_valid,
407*5113495bSYour Name mpdu_info->mpdu_duration_valid,
408*5113495bSYour Name mpdu_info->mac_addr_ad1_valid,
409*5113495bSYour Name mpdu_info->mac_addr_ad2_valid,
410*5113495bSYour Name mpdu_info->mac_addr_ad3_valid,
411*5113495bSYour Name mpdu_info->mac_addr_ad4_valid,
412*5113495bSYour Name mpdu_info->mpdu_sequence_control_valid,
413*5113495bSYour Name mpdu_info->mpdu_qos_control_valid,
414*5113495bSYour Name mpdu_info->mpdu_ht_control_valid,
415*5113495bSYour Name mpdu_info->frame_encryption_info_valid);
416*5113495bSYour Name
417*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
418*5113495bSYour Name "rx_mpdu_start tlv (3/5) - "
419*5113495bSYour Name "mpdu_fragment_number:%x "
420*5113495bSYour Name "more_fragment_flag:%x "
421*5113495bSYour Name "fr_ds:%x "
422*5113495bSYour Name "to_ds:%x "
423*5113495bSYour Name "encrypted:%x "
424*5113495bSYour Name "mpdu_retry:%x "
425*5113495bSYour Name "mpdu_sequence_number:%x ",
426*5113495bSYour Name mpdu_info->mpdu_fragment_number,
427*5113495bSYour Name mpdu_info->more_fragment_flag,
428*5113495bSYour Name mpdu_info->fr_ds,
429*5113495bSYour Name mpdu_info->to_ds,
430*5113495bSYour Name mpdu_info->encrypted,
431*5113495bSYour Name mpdu_info->mpdu_retry,
432*5113495bSYour Name mpdu_info->mpdu_sequence_number);
433*5113495bSYour Name
434*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
435*5113495bSYour Name "rx_mpdu_start tlv (4/5) - "
436*5113495bSYour Name "mpdu_frame_control_field:%x "
437*5113495bSYour Name "mpdu_duration_field:%x ",
438*5113495bSYour Name mpdu_info->mpdu_frame_control_field,
439*5113495bSYour Name mpdu_info->mpdu_duration_field);
440*5113495bSYour Name
441*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
442*5113495bSYour Name "rx_mpdu_start tlv (5/5) - "
443*5113495bSYour Name "mac_addr_ad1_31_0:%x "
444*5113495bSYour Name "mac_addr_ad1_47_32:%x "
445*5113495bSYour Name "mac_addr_ad2_15_0:%x "
446*5113495bSYour Name "mac_addr_ad2_47_16:%x "
447*5113495bSYour Name "mac_addr_ad3_31_0:%x "
448*5113495bSYour Name "mac_addr_ad3_47_32:%x "
449*5113495bSYour Name "mpdu_sequence_control_field :%x",
450*5113495bSYour Name mpdu_info->mac_addr_ad1_31_0,
451*5113495bSYour Name mpdu_info->mac_addr_ad1_47_32,
452*5113495bSYour Name mpdu_info->mac_addr_ad2_15_0,
453*5113495bSYour Name mpdu_info->mac_addr_ad2_47_16,
454*5113495bSYour Name mpdu_info->mac_addr_ad3_31_0,
455*5113495bSYour Name mpdu_info->mac_addr_ad3_47_32,
456*5113495bSYour Name mpdu_info->mpdu_sequence_control_field);
457*5113495bSYour Name }
458*5113495bSYour Name
459*5113495bSYour Name /**
460*5113495bSYour Name * hal_rx_dump_msdu_end_tlv_6432() - dump RX msdu_end TLV in structured
461*5113495bSYour Name * human readable format.
462*5113495bSYour Name * @msduend: pointer the msdu_end TLV in pkt.
463*5113495bSYour Name * @dbg_level: log level.
464*5113495bSYour Name *
465*5113495bSYour Name * Return: void
466*5113495bSYour Name */
hal_rx_dump_msdu_end_tlv_6432(void * msduend,uint8_t dbg_level)467*5113495bSYour Name static void hal_rx_dump_msdu_end_tlv_6432(void *msduend,
468*5113495bSYour Name uint8_t dbg_level)
469*5113495bSYour Name {
470*5113495bSYour Name struct rx_msdu_end_compact *msdu_end =
471*5113495bSYour Name (struct rx_msdu_end_compact *)msduend;
472*5113495bSYour Name
473*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
474*5113495bSYour Name "rx_msdu_end tlv - "
475*5113495bSYour Name "key_id_octet: %d "
476*5113495bSYour Name "tcp_udp_chksum: %d "
477*5113495bSYour Name "sa_idx_timeout: %d "
478*5113495bSYour Name "da_idx_timeout: %d "
479*5113495bSYour Name "msdu_limit_error: %d "
480*5113495bSYour Name "flow_idx_timeout: %d "
481*5113495bSYour Name "flow_idx_invalid: %d "
482*5113495bSYour Name "wifi_parser_error: %d "
483*5113495bSYour Name "sa_is_valid: %d "
484*5113495bSYour Name "da_is_valid: %d "
485*5113495bSYour Name "da_is_mcbc: %d "
486*5113495bSYour Name "tkip_mic_err: %d "
487*5113495bSYour Name "l3_header_padding: %d "
488*5113495bSYour Name "first_msdu: %d "
489*5113495bSYour Name "last_msdu: %d "
490*5113495bSYour Name "sa_idx: %d "
491*5113495bSYour Name "msdu_drop: %d "
492*5113495bSYour Name "reo_destination_indication: %d "
493*5113495bSYour Name "flow_idx: %d "
494*5113495bSYour Name "fse_metadata: %d "
495*5113495bSYour Name "cce_metadata: %d "
496*5113495bSYour Name "sa_sw_peer_id: %d ",
497*5113495bSYour Name msdu_end->key_id_octet,
498*5113495bSYour Name msdu_end->tcp_udp_chksum,
499*5113495bSYour Name msdu_end->sa_idx_timeout,
500*5113495bSYour Name msdu_end->da_idx_timeout,
501*5113495bSYour Name msdu_end->msdu_limit_error,
502*5113495bSYour Name msdu_end->flow_idx_timeout,
503*5113495bSYour Name msdu_end->flow_idx_invalid,
504*5113495bSYour Name msdu_end->wifi_parser_error,
505*5113495bSYour Name msdu_end->sa_is_valid,
506*5113495bSYour Name msdu_end->da_is_valid,
507*5113495bSYour Name msdu_end->da_is_mcbc,
508*5113495bSYour Name msdu_end->tkip_mic_err,
509*5113495bSYour Name msdu_end->l3_header_padding,
510*5113495bSYour Name msdu_end->first_msdu,
511*5113495bSYour Name msdu_end->last_msdu,
512*5113495bSYour Name msdu_end->sa_idx,
513*5113495bSYour Name msdu_end->msdu_drop,
514*5113495bSYour Name msdu_end->reo_destination_indication,
515*5113495bSYour Name msdu_end->flow_idx,
516*5113495bSYour Name msdu_end->fse_metadata,
517*5113495bSYour Name msdu_end->cce_metadata,
518*5113495bSYour Name msdu_end->sa_sw_peer_id);
519*5113495bSYour Name }
520*5113495bSYour Name #else
hal_rx_dump_mpdu_start_tlv_6432(void * mpdustart,uint8_t dbg_level)521*5113495bSYour Name static inline void hal_rx_dump_mpdu_start_tlv_6432(void *mpdustart,
522*5113495bSYour Name uint8_t dbg_level)
523*5113495bSYour Name {
524*5113495bSYour Name struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
525*5113495bSYour Name struct rx_mpdu_info *mpdu_info =
526*5113495bSYour Name (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
527*5113495bSYour Name
528*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
529*5113495bSYour Name "rx_mpdu_start tlv (1/5) - "
530*5113495bSYour Name "rx_reo_queue_desc_addr_31_0 :%x"
531*5113495bSYour Name "rx_reo_queue_desc_addr_39_32 :%x"
532*5113495bSYour Name "receive_queue_number:%x "
533*5113495bSYour Name "pre_delim_err_warning:%x "
534*5113495bSYour Name "first_delim_err:%x "
535*5113495bSYour Name "reserved_2a:%x "
536*5113495bSYour Name "pn_31_0:%x "
537*5113495bSYour Name "pn_63_32:%x "
538*5113495bSYour Name "pn_95_64:%x "
539*5113495bSYour Name "pn_127_96:%x "
540*5113495bSYour Name "epd_en:%x "
541*5113495bSYour Name "all_frames_shall_be_encrypted :%x"
542*5113495bSYour Name "encrypt_type:%x "
543*5113495bSYour Name "wep_key_width_for_variable_key :%x"
544*5113495bSYour Name "mesh_sta:%x "
545*5113495bSYour Name "bssid_hit:%x "
546*5113495bSYour Name "bssid_number:%x "
547*5113495bSYour Name "tid:%x "
548*5113495bSYour Name "reserved_7a:%x ",
549*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_31_0,
550*5113495bSYour Name mpdu_info->rx_reo_queue_desc_addr_39_32,
551*5113495bSYour Name mpdu_info->receive_queue_number,
552*5113495bSYour Name mpdu_info->pre_delim_err_warning,
553*5113495bSYour Name mpdu_info->first_delim_err,
554*5113495bSYour Name mpdu_info->reserved_2a,
555*5113495bSYour Name mpdu_info->pn_31_0,
556*5113495bSYour Name mpdu_info->pn_63_32,
557*5113495bSYour Name mpdu_info->pn_95_64,
558*5113495bSYour Name mpdu_info->pn_127_96,
559*5113495bSYour Name mpdu_info->epd_en,
560*5113495bSYour Name mpdu_info->all_frames_shall_be_encrypted,
561*5113495bSYour Name mpdu_info->encrypt_type,
562*5113495bSYour Name mpdu_info->wep_key_width_for_variable_key,
563*5113495bSYour Name mpdu_info->mesh_sta,
564*5113495bSYour Name mpdu_info->bssid_hit,
565*5113495bSYour Name mpdu_info->bssid_number,
566*5113495bSYour Name mpdu_info->tid,
567*5113495bSYour Name mpdu_info->reserved_7a);
568*5113495bSYour Name
569*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
570*5113495bSYour Name "rx_mpdu_start tlv (2/5) - "
571*5113495bSYour Name "ast_index:%x "
572*5113495bSYour Name "sw_peer_id:%x "
573*5113495bSYour Name "mpdu_frame_control_valid:%x "
574*5113495bSYour Name "mpdu_duration_valid:%x "
575*5113495bSYour Name "mac_addr_ad1_valid:%x "
576*5113495bSYour Name "mac_addr_ad2_valid:%x "
577*5113495bSYour Name "mac_addr_ad3_valid:%x "
578*5113495bSYour Name "mac_addr_ad4_valid:%x "
579*5113495bSYour Name "mpdu_sequence_control_valid :%x"
580*5113495bSYour Name "mpdu_qos_control_valid:%x "
581*5113495bSYour Name "mpdu_ht_control_valid:%x "
582*5113495bSYour Name "frame_encryption_info_valid :%x",
583*5113495bSYour Name mpdu_info->ast_index,
584*5113495bSYour Name mpdu_info->sw_peer_id,
585*5113495bSYour Name mpdu_info->mpdu_frame_control_valid,
586*5113495bSYour Name mpdu_info->mpdu_duration_valid,
587*5113495bSYour Name mpdu_info->mac_addr_ad1_valid,
588*5113495bSYour Name mpdu_info->mac_addr_ad2_valid,
589*5113495bSYour Name mpdu_info->mac_addr_ad3_valid,
590*5113495bSYour Name mpdu_info->mac_addr_ad4_valid,
591*5113495bSYour Name mpdu_info->mpdu_sequence_control_valid,
592*5113495bSYour Name mpdu_info->mpdu_qos_control_valid,
593*5113495bSYour Name mpdu_info->mpdu_ht_control_valid,
594*5113495bSYour Name mpdu_info->frame_encryption_info_valid);
595*5113495bSYour Name
596*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
597*5113495bSYour Name "rx_mpdu_start tlv (3/5) - "
598*5113495bSYour Name "mpdu_fragment_number:%x "
599*5113495bSYour Name "more_fragment_flag:%x "
600*5113495bSYour Name "reserved_11a:%x "
601*5113495bSYour Name "fr_ds:%x "
602*5113495bSYour Name "to_ds:%x "
603*5113495bSYour Name "encrypted:%x "
604*5113495bSYour Name "mpdu_retry:%x "
605*5113495bSYour Name "mpdu_sequence_number:%x ",
606*5113495bSYour Name mpdu_info->mpdu_fragment_number,
607*5113495bSYour Name mpdu_info->more_fragment_flag,
608*5113495bSYour Name mpdu_info->reserved_11a,
609*5113495bSYour Name mpdu_info->fr_ds,
610*5113495bSYour Name mpdu_info->to_ds,
611*5113495bSYour Name mpdu_info->encrypted,
612*5113495bSYour Name mpdu_info->mpdu_retry,
613*5113495bSYour Name mpdu_info->mpdu_sequence_number);
614*5113495bSYour Name
615*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
616*5113495bSYour Name "rx_mpdu_start tlv (4/5) - "
617*5113495bSYour Name "mpdu_frame_control_field:%x "
618*5113495bSYour Name "mpdu_duration_field:%x ",
619*5113495bSYour Name mpdu_info->mpdu_frame_control_field,
620*5113495bSYour Name mpdu_info->mpdu_duration_field);
621*5113495bSYour Name
622*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
623*5113495bSYour Name "rx_mpdu_start tlv (5/5) - "
624*5113495bSYour Name "mac_addr_ad1_31_0:%x "
625*5113495bSYour Name "mac_addr_ad1_47_32:%x "
626*5113495bSYour Name "mac_addr_ad2_15_0:%x "
627*5113495bSYour Name "mac_addr_ad2_47_16:%x "
628*5113495bSYour Name "mac_addr_ad3_31_0:%x "
629*5113495bSYour Name "mac_addr_ad3_47_32:%x "
630*5113495bSYour Name "mpdu_sequence_control_field :%x"
631*5113495bSYour Name "mac_addr_ad4_31_0:%x "
632*5113495bSYour Name "mac_addr_ad4_47_32:%x "
633*5113495bSYour Name "mpdu_qos_control_field:%x ",
634*5113495bSYour Name mpdu_info->mac_addr_ad1_31_0,
635*5113495bSYour Name mpdu_info->mac_addr_ad1_47_32,
636*5113495bSYour Name mpdu_info->mac_addr_ad2_15_0,
637*5113495bSYour Name mpdu_info->mac_addr_ad2_47_16,
638*5113495bSYour Name mpdu_info->mac_addr_ad3_31_0,
639*5113495bSYour Name mpdu_info->mac_addr_ad3_47_32,
640*5113495bSYour Name mpdu_info->mpdu_sequence_control_field,
641*5113495bSYour Name mpdu_info->mac_addr_ad4_31_0,
642*5113495bSYour Name mpdu_info->mac_addr_ad4_47_32,
643*5113495bSYour Name mpdu_info->mpdu_qos_control_field);
644*5113495bSYour Name }
645*5113495bSYour Name
hal_rx_dump_msdu_end_tlv_6432(void * msduend,uint8_t dbg_level)646*5113495bSYour Name static void hal_rx_dump_msdu_end_tlv_6432(void *msduend,
647*5113495bSYour Name uint8_t dbg_level)
648*5113495bSYour Name {
649*5113495bSYour Name struct rx_msdu_end *msdu_end =
650*5113495bSYour Name (struct rx_msdu_end *)msduend;
651*5113495bSYour Name
652*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
653*5113495bSYour Name "rx_msdu_end tlv - "
654*5113495bSYour Name "key_id_octet: %d "
655*5113495bSYour Name "cce_super_rule: %d "
656*5113495bSYour Name "cce_classify_not_done_truncat: %d "
657*5113495bSYour Name "cce_classify_not_done_cce_dis: %d "
658*5113495bSYour Name "rule_indication_31_0: %d "
659*5113495bSYour Name "tcp_udp_chksum: %d "
660*5113495bSYour Name "sa_idx_timeout: %d "
661*5113495bSYour Name "da_idx_timeout: %d "
662*5113495bSYour Name "msdu_limit_error: %d "
663*5113495bSYour Name "flow_idx_timeout: %d "
664*5113495bSYour Name "flow_idx_invalid: %d "
665*5113495bSYour Name "wifi_parser_error: %d "
666*5113495bSYour Name "sa_is_valid: %d "
667*5113495bSYour Name "da_is_valid: %d "
668*5113495bSYour Name "da_is_mcbc: %d "
669*5113495bSYour Name "tkip_mic_err: %d "
670*5113495bSYour Name "l3_header_padding: %d "
671*5113495bSYour Name "first_msdu: %d "
672*5113495bSYour Name "last_msdu: %d "
673*5113495bSYour Name "sa_idx: %d "
674*5113495bSYour Name "msdu_drop: %d "
675*5113495bSYour Name "reo_destination_indication: %d "
676*5113495bSYour Name "flow_idx: %d "
677*5113495bSYour Name "fse_metadata: %d "
678*5113495bSYour Name "cce_metadata: %d "
679*5113495bSYour Name "sa_sw_peer_id: %d ",
680*5113495bSYour Name msdu_end->key_id_octet,
681*5113495bSYour Name msdu_end->cce_super_rule,
682*5113495bSYour Name msdu_end->cce_classify_not_done_truncate,
683*5113495bSYour Name msdu_end->cce_classify_not_done_cce_dis,
684*5113495bSYour Name msdu_end->rule_indication_31_0,
685*5113495bSYour Name msdu_end->tcp_udp_chksum,
686*5113495bSYour Name msdu_end->sa_idx_timeout,
687*5113495bSYour Name msdu_end->da_idx_timeout,
688*5113495bSYour Name msdu_end->msdu_limit_error,
689*5113495bSYour Name msdu_end->flow_idx_timeout,
690*5113495bSYour Name msdu_end->flow_idx_invalid,
691*5113495bSYour Name msdu_end->wifi_parser_error,
692*5113495bSYour Name msdu_end->sa_is_valid,
693*5113495bSYour Name msdu_end->da_is_valid,
694*5113495bSYour Name msdu_end->da_is_mcbc,
695*5113495bSYour Name msdu_end->tkip_mic_err,
696*5113495bSYour Name msdu_end->l3_header_padding,
697*5113495bSYour Name msdu_end->first_msdu,
698*5113495bSYour Name msdu_end->last_msdu,
699*5113495bSYour Name msdu_end->sa_idx,
700*5113495bSYour Name msdu_end->msdu_drop,
701*5113495bSYour Name msdu_end->reo_destination_indication,
702*5113495bSYour Name msdu_end->flow_idx,
703*5113495bSYour Name msdu_end->fse_metadata,
704*5113495bSYour Name msdu_end->cce_metadata,
705*5113495bSYour Name msdu_end->sa_sw_peer_id);
706*5113495bSYour Name }
707*5113495bSYour Name #endif
708*5113495bSYour Name
709*5113495bSYour Name /**
710*5113495bSYour Name * hal_reo_status_get_header_6432() - Process reo desc info
711*5113495bSYour Name *
712*5113495bSYour Name * @ring_desc: Pointer to reo descriptor
713*5113495bSYour Name * @b: tlv type info
714*5113495bSYour Name * @h1: Pointer to hal_reo_status_header where info to be stored
715*5113495bSYour Name *
716*5113495bSYour Name * Return: none.
717*5113495bSYour Name *
718*5113495bSYour Name */
hal_reo_status_get_header_6432(hal_ring_desc_t ring_desc,int b,void * h1)719*5113495bSYour Name static void hal_reo_status_get_header_6432(hal_ring_desc_t ring_desc,
720*5113495bSYour Name int b, void *h1)
721*5113495bSYour Name {
722*5113495bSYour Name uint64_t *d = (uint64_t *)ring_desc;
723*5113495bSYour Name uint64_t val1 = 0;
724*5113495bSYour Name struct hal_reo_status_header *h =
725*5113495bSYour Name (struct hal_reo_status_header *)h1;
726*5113495bSYour Name
727*5113495bSYour Name /* Offsets of descriptor fields defined in HW headers start
728*5113495bSYour Name * from the field after TLV header
729*5113495bSYour Name */
730*5113495bSYour Name d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
731*5113495bSYour Name
732*5113495bSYour Name switch (b) {
733*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
734*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
735*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
736*5113495bSYour Name break;
737*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
738*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
739*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
740*5113495bSYour Name break;
741*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
742*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
743*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
744*5113495bSYour Name break;
745*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
746*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
747*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
748*5113495bSYour Name break;
749*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
750*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
751*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
752*5113495bSYour Name break;
753*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
754*5113495bSYour Name val1 =
755*5113495bSYour Name d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
756*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
757*5113495bSYour Name break;
758*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
759*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
760*5113495bSYour Name STATUS_HEADER_REO_STATUS_NUMBER)];
761*5113495bSYour Name break;
762*5113495bSYour Name default:
763*5113495bSYour Name qdf_nofl_err("ERROR: Unknown tlv\n");
764*5113495bSYour Name break;
765*5113495bSYour Name }
766*5113495bSYour Name h->cmd_num =
767*5113495bSYour Name HAL_GET_FIELD(
768*5113495bSYour Name UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
769*5113495bSYour Name val1);
770*5113495bSYour Name h->exec_time =
771*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
772*5113495bSYour Name CMD_EXECUTION_TIME, val1);
773*5113495bSYour Name h->status =
774*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
775*5113495bSYour Name REO_CMD_EXECUTION_STATUS, val1);
776*5113495bSYour Name switch (b) {
777*5113495bSYour Name case HAL_REO_QUEUE_STATS_STATUS_TLV:
778*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
779*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
780*5113495bSYour Name break;
781*5113495bSYour Name case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
782*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
783*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
784*5113495bSYour Name break;
785*5113495bSYour Name case HAL_REO_FLUSH_CACHE_STATUS_TLV:
786*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
787*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
788*5113495bSYour Name break;
789*5113495bSYour Name case HAL_REO_UNBLK_CACHE_STATUS_TLV:
790*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
791*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
792*5113495bSYour Name break;
793*5113495bSYour Name case HAL_REO_TIMOUT_LIST_STATUS_TLV:
794*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
795*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
796*5113495bSYour Name break;
797*5113495bSYour Name case HAL_REO_DESC_THRES_STATUS_TLV:
798*5113495bSYour Name val1 =
799*5113495bSYour Name d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
800*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
801*5113495bSYour Name break;
802*5113495bSYour Name case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
803*5113495bSYour Name val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
804*5113495bSYour Name STATUS_HEADER_TIMESTAMP)];
805*5113495bSYour Name break;
806*5113495bSYour Name default:
807*5113495bSYour Name qdf_nofl_err("ERROR: Unknown tlv\n");
808*5113495bSYour Name break;
809*5113495bSYour Name }
810*5113495bSYour Name h->tstamp =
811*5113495bSYour Name HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
812*5113495bSYour Name }
813*5113495bSYour Name
814*5113495bSYour Name static
hal_rx_msdu0_buffer_addr_lsb_6432(void * link_desc_va)815*5113495bSYour Name void *hal_rx_msdu0_buffer_addr_lsb_6432(void *link_desc_va)
816*5113495bSYour Name {
817*5113495bSYour Name return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
818*5113495bSYour Name }
819*5113495bSYour Name
820*5113495bSYour Name static
hal_rx_msdu_desc_info_ptr_get_6432(void * msdu0)821*5113495bSYour Name void *hal_rx_msdu_desc_info_ptr_get_6432(void *msdu0)
822*5113495bSYour Name {
823*5113495bSYour Name return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
824*5113495bSYour Name }
825*5113495bSYour Name
826*5113495bSYour Name static
hal_ent_mpdu_desc_info_6432(void * ent_ring_desc)827*5113495bSYour Name void *hal_ent_mpdu_desc_info_6432(void *ent_ring_desc)
828*5113495bSYour Name {
829*5113495bSYour Name return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
830*5113495bSYour Name }
831*5113495bSYour Name
832*5113495bSYour Name static
hal_dst_mpdu_desc_info_6432(void * dst_ring_desc)833*5113495bSYour Name void *hal_dst_mpdu_desc_info_6432(void *dst_ring_desc)
834*5113495bSYour Name {
835*5113495bSYour Name return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
836*5113495bSYour Name }
837*5113495bSYour Name
838*5113495bSYour Name /**
839*5113495bSYour Name * hal_reo_config_6432(): Set reo config parameters
840*5113495bSYour Name * @soc: hal soc handle
841*5113495bSYour Name * @reg_val: value to be set
842*5113495bSYour Name * @reo_params: reo parameters
843*5113495bSYour Name *
844*5113495bSYour Name * Return: void
845*5113495bSYour Name */
846*5113495bSYour Name static void
hal_reo_config_6432(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)847*5113495bSYour Name hal_reo_config_6432(struct hal_soc *soc,
848*5113495bSYour Name uint32_t reg_val,
849*5113495bSYour Name struct hal_reo_params *reo_params)
850*5113495bSYour Name {
851*5113495bSYour Name HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
852*5113495bSYour Name }
853*5113495bSYour Name
854*5113495bSYour Name /**
855*5113495bSYour Name * hal_rx_msdu_desc_info_get_ptr_6432() - Get msdu desc info ptr
856*5113495bSYour Name * @msdu_details_ptr: Pointer to msdu_details_ptr
857*5113495bSYour Name *
858*5113495bSYour Name * Return: Pointer to rx_msdu_desc_info structure.
859*5113495bSYour Name *
860*5113495bSYour Name */
hal_rx_msdu_desc_info_get_ptr_6432(void * msdu_details_ptr)861*5113495bSYour Name static void *hal_rx_msdu_desc_info_get_ptr_6432(void *msdu_details_ptr)
862*5113495bSYour Name {
863*5113495bSYour Name return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
864*5113495bSYour Name }
865*5113495bSYour Name
866*5113495bSYour Name /**
867*5113495bSYour Name * hal_rx_link_desc_msdu0_ptr_6432 - Get pointer to rx_msdu details
868*5113495bSYour Name * @link_desc: Pointer to link desc
869*5113495bSYour Name *
870*5113495bSYour Name * Return: Pointer to rx_msdu_details structure
871*5113495bSYour Name *
872*5113495bSYour Name */
hal_rx_link_desc_msdu0_ptr_6432(void * link_desc)873*5113495bSYour Name static void *hal_rx_link_desc_msdu0_ptr_6432(void *link_desc)
874*5113495bSYour Name {
875*5113495bSYour Name return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
876*5113495bSYour Name }
877*5113495bSYour Name
878*5113495bSYour Name /**
879*5113495bSYour Name * hal_get_window_address_6432(): Function to get hp/tp address
880*5113495bSYour Name * @hal_soc: Pointer to hal_soc
881*5113495bSYour Name * @addr: address offset of register
882*5113495bSYour Name *
883*5113495bSYour Name * Return: modified address offset of register
884*5113495bSYour Name */
885*5113495bSYour Name
hal_get_window_address_6432(struct hal_soc * hal_soc,qdf_iomem_t addr)886*5113495bSYour Name static inline qdf_iomem_t hal_get_window_address_6432(struct hal_soc *hal_soc,
887*5113495bSYour Name qdf_iomem_t addr)
888*5113495bSYour Name {
889*5113495bSYour Name uint32_t offset = addr - hal_soc->dev_base_addr;
890*5113495bSYour Name qdf_iomem_t new_offset;
891*5113495bSYour Name
892*5113495bSYour Name /*
893*5113495bSYour Name * If offset lies within DP register range, use 3rd window to write
894*5113495bSYour Name * into DP region.
895*5113495bSYour Name */
896*5113495bSYour Name if ((offset ^ UMAC_BASE) < WINDOW_RANGE_MASK) {
897*5113495bSYour Name new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) +
898*5113495bSYour Name (offset & WINDOW_RANGE_MASK));
899*5113495bSYour Name /*
900*5113495bSYour Name * If offset lies within CE register range, use 2nd window to write
901*5113495bSYour Name * into CE region.
902*5113495bSYour Name */
903*5113495bSYour Name } else if ((offset ^ SOC_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) {
904*5113495bSYour Name new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) +
905*5113495bSYour Name (offset & WINDOW_RANGE_MASK));
906*5113495bSYour Name } else {
907*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
908*5113495bSYour Name "%s: ERROR: Accessing Wrong register\n", __func__);
909*5113495bSYour Name qdf_assert_always(0);
910*5113495bSYour Name return 0;
911*5113495bSYour Name }
912*5113495bSYour Name return new_offset;
913*5113495bSYour Name }
914*5113495bSYour Name
hal_write_window_register(struct hal_soc * hal_soc)915*5113495bSYour Name static inline void hal_write_window_register(struct hal_soc *hal_soc)
916*5113495bSYour Name {
917*5113495bSYour Name /* Write value into window configuration register */
918*5113495bSYour Name qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
919*5113495bSYour Name WINDOW_CONFIGURATION_VALUE_6432);
920*5113495bSYour Name }
921*5113495bSYour Name
922*5113495bSYour Name static
hal_compute_reo_remap_ix2_ix3_6432(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)923*5113495bSYour Name void hal_compute_reo_remap_ix2_ix3_6432(uint32_t *ring, uint32_t num_rings,
924*5113495bSYour Name uint32_t *remap1, uint32_t *remap2)
925*5113495bSYour Name {
926*5113495bSYour Name switch (num_rings) {
927*5113495bSYour Name case 1:
928*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
929*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 17) |
930*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 18) |
931*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 19) |
932*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
933*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 21) |
934*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 22) |
935*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 23);
936*5113495bSYour Name
937*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
938*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
939*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 26) |
940*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 27) |
941*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
942*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 29) |
943*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 30) |
944*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 31);
945*5113495bSYour Name break;
946*5113495bSYour Name case 2:
947*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
948*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 17) |
949*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 18) |
950*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 19) |
951*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
952*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 21) |
953*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 22) |
954*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 23);
955*5113495bSYour Name
956*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
957*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
958*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 26) |
959*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 27) |
960*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
961*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 29) |
962*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 30) |
963*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 31);
964*5113495bSYour Name break;
965*5113495bSYour Name case 3:
966*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
967*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 17) |
968*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 18) |
969*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 19) |
970*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 20) |
971*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 21) |
972*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 22) |
973*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 23);
974*5113495bSYour Name
975*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
976*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 25) |
977*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 26) |
978*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 27) |
979*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
980*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 29) |
981*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 30) |
982*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 31);
983*5113495bSYour Name break;
984*5113495bSYour Name case 4:
985*5113495bSYour Name *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
986*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 17) |
987*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 18) |
988*5113495bSYour Name HAL_REO_REMAP_IX2(ring[3], 19) |
989*5113495bSYour Name HAL_REO_REMAP_IX2(ring[0], 20) |
990*5113495bSYour Name HAL_REO_REMAP_IX2(ring[1], 21) |
991*5113495bSYour Name HAL_REO_REMAP_IX2(ring[2], 22) |
992*5113495bSYour Name HAL_REO_REMAP_IX2(ring[3], 23);
993*5113495bSYour Name
994*5113495bSYour Name *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
995*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 25) |
996*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 26) |
997*5113495bSYour Name HAL_REO_REMAP_IX3(ring[3], 27) |
998*5113495bSYour Name HAL_REO_REMAP_IX3(ring[0], 28) |
999*5113495bSYour Name HAL_REO_REMAP_IX3(ring[1], 29) |
1000*5113495bSYour Name HAL_REO_REMAP_IX3(ring[2], 30) |
1001*5113495bSYour Name HAL_REO_REMAP_IX3(ring[3], 31);
1002*5113495bSYour Name break;
1003*5113495bSYour Name }
1004*5113495bSYour Name }
1005*5113495bSYour Name
1006*5113495bSYour Name /**
1007*5113495bSYour Name * hal_rx_flow_setup_fse_6432() - Setup a flow search entry in HW FST
1008*5113495bSYour Name * @rx_fst: Pointer to the Rx Flow Search Table
1009*5113495bSYour Name * @table_offset: offset into the table where the flow is to be setup
1010*5113495bSYour Name * @rx_flow: Flow Parameters
1011*5113495bSYour Name *
1012*5113495bSYour Name * Return: Success/Failure
1013*5113495bSYour Name */
1014*5113495bSYour Name static void *
hal_rx_flow_setup_fse_6432(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1015*5113495bSYour Name hal_rx_flow_setup_fse_6432(uint8_t *rx_fst, uint32_t table_offset,
1016*5113495bSYour Name uint8_t *rx_flow)
1017*5113495bSYour Name {
1018*5113495bSYour Name struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1019*5113495bSYour Name struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1020*5113495bSYour Name uint8_t *fse;
1021*5113495bSYour Name bool fse_valid;
1022*5113495bSYour Name
1023*5113495bSYour Name if (table_offset >= fst->max_entries) {
1024*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1025*5113495bSYour Name "HAL FSE table offset %u exceeds max entries %u",
1026*5113495bSYour Name table_offset, fst->max_entries);
1027*5113495bSYour Name return NULL;
1028*5113495bSYour Name }
1029*5113495bSYour Name
1030*5113495bSYour Name fse = (uint8_t *)fst->base_vaddr +
1031*5113495bSYour Name (table_offset * HAL_RX_FST_ENTRY_SIZE);
1032*5113495bSYour Name
1033*5113495bSYour Name fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1034*5113495bSYour Name
1035*5113495bSYour Name if (fse_valid) {
1036*5113495bSYour Name QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1037*5113495bSYour Name "HAL FSE %pK already valid", fse);
1038*5113495bSYour Name return NULL;
1039*5113495bSYour Name }
1040*5113495bSYour Name
1041*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
1042*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1043*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_127_96));
1044*5113495bSYour Name
1045*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
1046*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1047*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_95_64));
1048*5113495bSYour Name
1049*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
1050*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1051*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_63_32));
1052*5113495bSYour Name
1053*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
1054*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1055*5113495bSYour Name qdf_htonl(flow->tuple_info.src_ip_31_0));
1056*5113495bSYour Name
1057*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
1058*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1059*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_127_96));
1060*5113495bSYour Name
1061*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
1062*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1063*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_95_64));
1064*5113495bSYour Name
1065*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
1066*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1067*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_63_32));
1068*5113495bSYour Name
1069*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
1070*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1071*5113495bSYour Name qdf_htonl(flow->tuple_info.dest_ip_31_0));
1072*5113495bSYour Name
1073*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
1074*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
1075*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1076*5113495bSYour Name (flow->tuple_info.dest_port));
1077*5113495bSYour Name
1078*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
1079*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
1080*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1081*5113495bSYour Name (flow->tuple_info.src_port));
1082*5113495bSYour Name
1083*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
1084*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
1085*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1086*5113495bSYour Name flow->tuple_info.l4_protocol);
1087*5113495bSYour Name
1088*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE);
1089*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, USE_PPE) |=
1090*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, USE_PPE, flow->use_ppe_ds);
1091*5113495bSYour Name
1092*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID);
1093*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID) |=
1094*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, PRIORITY_VALID,
1095*5113495bSYour Name flow->priority_vld);
1096*5113495bSYour Name
1097*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE);
1098*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SERVICE_CODE) |=
1099*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SERVICE_CODE,
1100*5113495bSYour Name flow->service_code);
1101*5113495bSYour Name
1102*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
1103*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
1104*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1105*5113495bSYour Name flow->reo_destination_handler);
1106*5113495bSYour Name
1107*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1108*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
1109*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1110*5113495bSYour Name
1111*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
1112*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
1113*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1114*5113495bSYour Name flow->fse_metadata);
1115*5113495bSYour Name
1116*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
1117*5113495bSYour Name HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
1118*5113495bSYour Name HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1119*5113495bSYour Name REO_DESTINATION_INDICATION,
1120*5113495bSYour Name flow->reo_destination_indication);
1121*5113495bSYour Name
1122*5113495bSYour Name /* Reset all the other fields in FSE */
1123*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
1124*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
1125*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
1126*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
1127*5113495bSYour Name HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
1128*5113495bSYour Name
1129*5113495bSYour Name return fse;
1130*5113495bSYour Name }
1131*5113495bSYour Name
1132*5113495bSYour Name #ifndef NO_RX_PKT_HDR_TLV
1133*5113495bSYour Name /**
1134*5113495bSYour Name * hal_rx_dump_pkt_hdr_tlv_6432(): dump RX pkt header TLV in hex format
1135*5113495bSYour Name * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
1136*5113495bSYour Name * @dbg_level: log level.
1137*5113495bSYour Name *
1138*5113495bSYour Name * Return: void
1139*5113495bSYour Name */
hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1140*5113495bSYour Name static inline void hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs *pkt_tlvs,
1141*5113495bSYour Name uint8_t dbg_level)
1142*5113495bSYour Name {
1143*5113495bSYour Name struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
1144*5113495bSYour Name
1145*5113495bSYour Name hal_verbose_debug("\n---------------\n"
1146*5113495bSYour Name "rx_pkt_hdr_tlv\n"
1147*5113495bSYour Name "---------------\n"
1148*5113495bSYour Name "phy_ppdu_id 0x%x ",
1149*5113495bSYour Name pkt_hdr_tlv->phy_ppdu_id);
1150*5113495bSYour Name
1151*5113495bSYour Name hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
1152*5113495bSYour Name sizeof(pkt_hdr_tlv->rx_pkt_hdr));
1153*5113495bSYour Name }
1154*5113495bSYour Name #else
1155*5113495bSYour Name /**
1156*5113495bSYour Name * hal_rx_dump_pkt_hdr_tlv_6432(): dump RX pkt header TLV in hex format
1157*5113495bSYour Name * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
1158*5113495bSYour Name * @dbg_level: log level.
1159*5113495bSYour Name *
1160*5113495bSYour Name * Return: void
1161*5113495bSYour Name */
hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1162*5113495bSYour Name static inline void hal_rx_dump_pkt_hdr_tlv_6432(struct rx_pkt_tlvs *pkt_tlvs,
1163*5113495bSYour Name uint8_t dbg_level)
1164*5113495bSYour Name {
1165*5113495bSYour Name }
1166*5113495bSYour Name #endif
1167*5113495bSYour Name
1168*5113495bSYour Name /**
1169*5113495bSYour Name * hal_rx_dump_pkt_tlvs_6432(): API to print RX Pkt TLVS qcn6432
1170*5113495bSYour Name * @hal_soc_hdl: hal_soc handle
1171*5113495bSYour Name * @buf: pointer the pkt buffer
1172*5113495bSYour Name * @dbg_level: log level
1173*5113495bSYour Name *
1174*5113495bSYour Name * Return: void
1175*5113495bSYour Name */
1176*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1177*5113495bSYour Name static void hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl,
1178*5113495bSYour Name uint8_t *buf, uint8_t dbg_level)
1179*5113495bSYour Name {
1180*5113495bSYour Name struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1181*5113495bSYour Name struct rx_msdu_end_compact *msdu_end =
1182*5113495bSYour Name &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1183*5113495bSYour Name struct rx_mpdu_start_compact *mpdu_start =
1184*5113495bSYour Name &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1185*5113495bSYour Name
1186*5113495bSYour Name hal_rx_dump_msdu_end_tlv_6432(msdu_end, dbg_level);
1187*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_6432(mpdu_start, dbg_level);
1188*5113495bSYour Name hal_rx_dump_pkt_hdr_tlv_6432(pkt_tlvs, dbg_level);
1189*5113495bSYour Name }
1190*5113495bSYour Name #else
hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1191*5113495bSYour Name static void hal_rx_dump_pkt_tlvs_6432(hal_soc_handle_t hal_soc_hdl,
1192*5113495bSYour Name uint8_t *buf, uint8_t dbg_level)
1193*5113495bSYour Name {
1194*5113495bSYour Name struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1195*5113495bSYour Name struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1196*5113495bSYour Name struct rx_mpdu_start *mpdu_start =
1197*5113495bSYour Name &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1198*5113495bSYour Name
1199*5113495bSYour Name hal_rx_dump_msdu_end_tlv_6432(msdu_end, dbg_level);
1200*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_6432(mpdu_start, dbg_level);
1201*5113495bSYour Name hal_rx_dump_pkt_hdr_tlv_6432(pkt_tlvs, dbg_level);
1202*5113495bSYour Name }
1203*5113495bSYour Name #endif
1204*5113495bSYour Name
1205*5113495bSYour Name #define HAL_NUM_TCL_BANKS_6432 24
1206*5113495bSYour Name
1207*5113495bSYour Name /**
1208*5113495bSYour Name * hal_cmem_write_6432() - function for CMEM buffer writing
1209*5113495bSYour Name * @hal_soc_hdl: HAL SOC handle
1210*5113495bSYour Name * @offset: CMEM address
1211*5113495bSYour Name * @value: value to write
1212*5113495bSYour Name *
1213*5113495bSYour Name * Return: None.
1214*5113495bSYour Name */
hal_cmem_write_6432(hal_soc_handle_t hal_soc_hdl,uint32_t offset,uint32_t value)1215*5113495bSYour Name static void hal_cmem_write_6432(hal_soc_handle_t hal_soc_hdl,
1216*5113495bSYour Name uint32_t offset,
1217*5113495bSYour Name uint32_t value)
1218*5113495bSYour Name {
1219*5113495bSYour Name struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
1220*5113495bSYour Name
1221*5113495bSYour Name pld_reg_write(hal->qdf_dev->dev, offset, value,
1222*5113495bSYour Name hal->dev_base_addr_cmem);
1223*5113495bSYour Name }
1224*5113495bSYour Name
1225*5113495bSYour Name /**
1226*5113495bSYour Name * hal_tx_get_num_tcl_banks_6432() - Get number of banks in target
1227*5113495bSYour Name *
1228*5113495bSYour Name * Returns: number of bank
1229*5113495bSYour Name */
hal_tx_get_num_tcl_banks_6432(void)1230*5113495bSYour Name static uint8_t hal_tx_get_num_tcl_banks_6432(void)
1231*5113495bSYour Name {
1232*5113495bSYour Name return HAL_NUM_TCL_BANKS_6432;
1233*5113495bSYour Name }
1234*5113495bSYour Name
1235*5113495bSYour Name static
hal_compute_reo_remap_ix0_6432(struct hal_soc * soc)1236*5113495bSYour Name void hal_compute_reo_remap_ix0_6432(struct hal_soc *soc)
1237*5113495bSYour Name {
1238*5113495bSYour Name uint32_t remap0;
1239*5113495bSYour Name
1240*5113495bSYour Name remap0 = HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1241*5113495bSYour Name (REO_REG_REG_BASE));
1242*5113495bSYour Name
1243*5113495bSYour Name remap0 &= ~(HAL_REO_REMAP_IX0(0xF, 6));
1244*5113495bSYour Name remap0 |= HAL_REO_REMAP_IX0(REO2PPE_DST_RING, 6);
1245*5113495bSYour Name
1246*5113495bSYour Name HAL_REG_WRITE(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1247*5113495bSYour Name (REO_REG_REG_BASE), remap0);
1248*5113495bSYour Name
1249*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x",
1250*5113495bSYour Name HAL_REG_READ(soc, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR
1251*5113495bSYour Name (REO_REG_REG_BASE)));
1252*5113495bSYour Name }
1253*5113495bSYour Name
hal_reo_setup_6432(struct hal_soc * soc,void * reoparams,int qref_reset)1254*5113495bSYour Name static void hal_reo_setup_6432(struct hal_soc *soc, void *reoparams,
1255*5113495bSYour Name int qref_reset)
1256*5113495bSYour Name {
1257*5113495bSYour Name uint32_t reg_val;
1258*5113495bSYour Name struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
1259*5113495bSYour Name
1260*5113495bSYour Name reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
1261*5113495bSYour Name REO_REG_REG_BASE));
1262*5113495bSYour Name
1263*5113495bSYour Name hal_reo_config_6432(soc, reg_val, reo_params);
1264*5113495bSYour Name /* Other ring enable bits and REO_ENABLE will be set by FW */
1265*5113495bSYour Name
1266*5113495bSYour Name /* TODO: Setup destination ring mapping if enabled */
1267*5113495bSYour Name
1268*5113495bSYour Name /* TODO: Error destination ring setting is left to default.
1269*5113495bSYour Name * Default setting is to send all errors to release ring.
1270*5113495bSYour Name */
1271*5113495bSYour Name
1272*5113495bSYour Name /* Set the reo descriptor swap bits in case of BIG endian platform */
1273*5113495bSYour Name hal_setup_reo_swap(soc);
1274*5113495bSYour Name
1275*5113495bSYour Name HAL_REG_WRITE(soc,
1276*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
1277*5113495bSYour Name HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
1278*5113495bSYour Name
1279*5113495bSYour Name HAL_REG_WRITE(soc,
1280*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
1281*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1282*5113495bSYour Name
1283*5113495bSYour Name HAL_REG_WRITE(soc,
1284*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
1285*5113495bSYour Name (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1286*5113495bSYour Name
1287*5113495bSYour Name HAL_REG_WRITE(soc,
1288*5113495bSYour Name HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
1289*5113495bSYour Name (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
1290*5113495bSYour Name
1291*5113495bSYour Name /*
1292*5113495bSYour Name * When hash based routing is enabled, routing of the rx packet
1293*5113495bSYour Name * is done based on the following value: 1 _ _ _ _ The last 4
1294*5113495bSYour Name * bits are based on hash[3:0]. This means the possible values
1295*5113495bSYour Name * are 0x10 to 0x1f. This value is used to look-up the
1296*5113495bSYour Name * ring ID configured in Destination_Ring_Ctrl_IX_* register.
1297*5113495bSYour Name * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
1298*5113495bSYour Name * registers need to be configured to set-up the 16 entries to
1299*5113495bSYour Name * map the hash values to a ring number. There are 3 bits per
1300*5113495bSYour Name * hash entry – which are mapped as follows:
1301*5113495bSYour Name * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
1302*5113495bSYour Name * 7: NOT_USED.
1303*5113495bSYour Name */
1304*5113495bSYour Name if (reo_params->rx_hash_enabled) {
1305*5113495bSYour Name hal_compute_reo_remap_ix0_6432(soc);
1306*5113495bSYour Name HAL_REG_WRITE(soc,
1307*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
1308*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap0);
1309*5113495bSYour Name
1310*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1311*5113495bSYour Name HAL_REG_READ(soc,
1312*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
1313*5113495bSYour Name REO_REG_REG_BASE)));
1314*5113495bSYour Name
1315*5113495bSYour Name HAL_REG_WRITE(soc,
1316*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
1317*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap1);
1318*5113495bSYour Name
1319*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1320*5113495bSYour Name HAL_REG_READ(soc,
1321*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
1322*5113495bSYour Name REO_REG_REG_BASE)));
1323*5113495bSYour Name
1324*5113495bSYour Name HAL_REG_WRITE(soc,
1325*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
1326*5113495bSYour Name (REO_REG_REG_BASE), reo_params->remap2);
1327*5113495bSYour Name
1328*5113495bSYour Name hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
1329*5113495bSYour Name HAL_REG_READ(soc,
1330*5113495bSYour Name HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
1331*5113495bSYour Name REO_REG_REG_BASE)));
1332*5113495bSYour Name }
1333*5113495bSYour Name
1334*5113495bSYour Name /* TODO: Check if the following registers shoould be setup by host:
1335*5113495bSYour Name * AGING_CONTROL
1336*5113495bSYour Name * HIGH_MEMORY_THRESHOLD
1337*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
1338*5113495bSYour Name * GLOBAL_LINK_DESC_COUNT_CTRL
1339*5113495bSYour Name */
1340*5113495bSYour Name
1341*5113495bSYour Name soc->reo_qref = *reo_params->reo_qref;
1342*5113495bSYour Name hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
1343*5113495bSYour Name }
1344*5113495bSYour Name
hal_get_rx_max_ba_window_qcn6432(int tid)1345*5113495bSYour Name static uint16_t hal_get_rx_max_ba_window_qcn6432(int tid)
1346*5113495bSYour Name {
1347*5113495bSYour Name return HAL_RX_BA_WINDOW_1024;
1348*5113495bSYour Name }
1349*5113495bSYour Name
1350*5113495bSYour Name /**
1351*5113495bSYour Name * hal_qcn6432_get_reo_qdesc_size()- Get the reo queue descriptor size
1352*5113495bSYour Name * from the give Block-Ack window size
1353*5113495bSYour Name * @ba_window_size: Block-Ack window size
1354*5113495bSYour Name * @tid: TID
1355*5113495bSYour Name *
1356*5113495bSYour Name * Return: reo queue descriptor size
1357*5113495bSYour Name */
hal_qcn6432_get_reo_qdesc_size(uint32_t ba_window_size,int tid)1358*5113495bSYour Name static uint32_t hal_qcn6432_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
1359*5113495bSYour Name {
1360*5113495bSYour Name /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
1361*5113495bSYour Name * NON_QOS_TID until HW issues are resolved.
1362*5113495bSYour Name */
1363*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
1364*5113495bSYour Name ba_window_size = hal_get_rx_max_ba_window_qcn6432(tid);
1365*5113495bSYour Name
1366*5113495bSYour Name /* Return descriptor size corresponding to window size of 2 since
1367*5113495bSYour Name * we set ba_window_size to 2 while setting up REO descriptors as
1368*5113495bSYour Name * a WAR to get 2k jump exception aggregates are received without
1369*5113495bSYour Name * a BA session.
1370*5113495bSYour Name */
1371*5113495bSYour Name if (ba_window_size <= 1) {
1372*5113495bSYour Name if (tid != HAL_NON_QOS_TID)
1373*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1374*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
1375*5113495bSYour Name else
1376*5113495bSYour Name return sizeof(struct rx_reo_queue);
1377*5113495bSYour Name }
1378*5113495bSYour Name
1379*5113495bSYour Name if (ba_window_size <= 105)
1380*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1381*5113495bSYour Name sizeof(struct rx_reo_queue_ext);
1382*5113495bSYour Name
1383*5113495bSYour Name if (ba_window_size <= 210)
1384*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1385*5113495bSYour Name (2 * sizeof(struct rx_reo_queue_ext));
1386*5113495bSYour Name
1387*5113495bSYour Name if (ba_window_size <= 256)
1388*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1389*5113495bSYour Name (3 * sizeof(struct rx_reo_queue_ext));
1390*5113495bSYour Name
1391*5113495bSYour Name return sizeof(struct rx_reo_queue) +
1392*5113495bSYour Name (10 * sizeof(struct rx_reo_queue_ext)) +
1393*5113495bSYour Name sizeof(struct rx_reo_queue_1k);
1394*5113495bSYour Name }
1395*5113495bSYour Name /**
1396*5113495bSYour Name * hal_rx_tlv_msdu_done_copy_get_6432() - Get msdu done copy bit from rx_tlv
1397*5113495bSYour Name *
1398*5113495bSYour Name * @buf: pointer the tx_tlv
1399*5113495bSYour Name *
1400*5113495bSYour Name * Returns: msdu done copy bit
1401*5113495bSYour Name */
hal_rx_tlv_msdu_done_copy_get_6432(uint8_t * buf)1402*5113495bSYour Name static inline uint32_t hal_rx_tlv_msdu_done_copy_get_6432(uint8_t *buf)
1403*5113495bSYour Name {
1404*5113495bSYour Name return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
1405*5113495bSYour Name }
1406*5113495bSYour Name
1407*5113495bSYour Name /**
1408*5113495bSYour Name * hal_read_pmm_scratch_reg_6432(): API to read PMM Scratch register
1409*5113495bSYour Name *
1410*5113495bSYour Name * @soc: HAL soc
1411*5113495bSYour Name * @base_addr: BAR address
1412*5113495bSYour Name * @reg_enum: Enum of the scratch register
1413*5113495bSYour Name *
1414*5113495bSYour Name * Return: uint32_t
1415*5113495bSYour Name */
1416*5113495bSYour Name static inline
hal_read_pmm_scratch_reg_6432(struct hal_soc * soc,uint32_t base_addr,enum hal_scratch_reg_enum reg_enum)1417*5113495bSYour Name uint32_t hal_read_pmm_scratch_reg_6432(struct hal_soc *soc,
1418*5113495bSYour Name uint32_t base_addr,
1419*5113495bSYour Name enum hal_scratch_reg_enum reg_enum)
1420*5113495bSYour Name {
1421*5113495bSYour Name uint32_t val = 0;
1422*5113495bSYour Name
1423*5113495bSYour Name pld_reg_read(soc->qdf_dev->dev, base_addr + (reg_enum * 4), &val, NULL);
1424*5113495bSYour Name return val;
1425*5113495bSYour Name }
1426*5113495bSYour Name
1427*5113495bSYour Name /**
1428*5113495bSYour Name * hal_get_tsf2_scratch_reg_qcn6432(): API to read tsf2 scratch register
1429*5113495bSYour Name *
1430*5113495bSYour Name * @hal_soc_hdl: HAL soc context
1431*5113495bSYour Name * @mac_id: mac id
1432*5113495bSYour Name * @value: Pointer to update tsf2 value
1433*5113495bSYour Name *
1434*5113495bSYour Name * Return: void
1435*5113495bSYour Name */
hal_get_tsf2_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl,uint8_t mac_id,uint64_t * value)1436*5113495bSYour Name static void hal_get_tsf2_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl,
1437*5113495bSYour Name uint8_t mac_id, uint64_t *value)
1438*5113495bSYour Name {
1439*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
1440*5113495bSYour Name uint32_t offset_lo, offset_hi;
1441*5113495bSYour Name enum hal_scratch_reg_enum enum_lo, enum_hi;
1442*5113495bSYour Name
1443*5113495bSYour Name hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
1444*5113495bSYour Name
1445*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg_6432(soc,
1446*5113495bSYour Name PMM_REG_BASE_QCN6432,
1447*5113495bSYour Name enum_lo);
1448*5113495bSYour Name
1449*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg_6432(soc,
1450*5113495bSYour Name PMM_REG_BASE_QCN6432,
1451*5113495bSYour Name enum_hi);
1452*5113495bSYour Name
1453*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
1454*5113495bSYour Name }
1455*5113495bSYour Name
1456*5113495bSYour Name /**
1457*5113495bSYour Name * hal_get_tqm_scratch_reg_qcn6432(): API to read tqm scratch register
1458*5113495bSYour Name *
1459*5113495bSYour Name * @hal_soc_hdl: HAL soc context
1460*5113495bSYour Name * @value: Pointer to update tqm value
1461*5113495bSYour Name *
1462*5113495bSYour Name * Return: void
1463*5113495bSYour Name */
1464*5113495bSYour Name
hal_get_tqm_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl,uint64_t * value)1465*5113495bSYour Name static void hal_get_tqm_scratch_reg_qcn6432(hal_soc_handle_t hal_soc_hdl,
1466*5113495bSYour Name uint64_t *value)
1467*5113495bSYour Name {
1468*5113495bSYour Name struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
1469*5113495bSYour Name uint32_t offset_lo, offset_hi;
1470*5113495bSYour Name
1471*5113495bSYour Name offset_lo = hal_read_pmm_scratch_reg_6432(soc,
1472*5113495bSYour Name PMM_REG_BASE_QCN6432,
1473*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_LO_US);
1474*5113495bSYour Name
1475*5113495bSYour Name offset_hi = hal_read_pmm_scratch_reg_6432(soc,
1476*5113495bSYour Name PMM_REG_BASE_QCN6432,
1477*5113495bSYour Name PMM_TQM_CLOCK_OFFSET_HI_US);
1478*5113495bSYour Name
1479*5113495bSYour Name *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
1480*5113495bSYour Name }
1481*5113495bSYour Name
hal_hw_txrx_ops_attach_qcn6432(struct hal_soc * hal_soc)1482*5113495bSYour Name static void hal_hw_txrx_ops_attach_qcn6432(struct hal_soc *hal_soc)
1483*5113495bSYour Name {
1484*5113495bSYour Name /* init and setup */
1485*5113495bSYour Name hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1486*5113495bSYour Name hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1487*5113495bSYour Name hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic;
1488*5113495bSYour Name hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1489*5113495bSYour Name hal_soc->ops->hal_get_window_address = hal_get_window_address_6432;
1490*5113495bSYour Name hal_soc->ops->hal_cmem_write = hal_cmem_write_6432;
1491*5113495bSYour Name
1492*5113495bSYour Name /* tx */
1493*5113495bSYour Name hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6432;
1494*5113495bSYour Name hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6432;
1495*5113495bSYour Name hal_soc->ops->hal_tx_comp_get_status =
1496*5113495bSYour Name hal_tx_comp_get_status_generic_be;
1497*5113495bSYour Name hal_soc->ops->hal_tx_init_cmd_credit_ring =
1498*5113495bSYour Name hal_tx_init_cmd_credit_ring_6432;
1499*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_cmn_cfg = hal_tx_set_ppe_cmn_config_6432;
1500*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_vp_entry = hal_tx_set_ppe_vp_entry_6432;
1501*5113495bSYour Name hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg =
1502*5113495bSYour Name hal_ppeds_cfg_ast_override_map_reg_6432;
1503*5113495bSYour Name hal_soc->ops->hal_tx_set_ppe_pri2tid = hal_tx_set_ppe_pri2tid_map_6432;
1504*5113495bSYour Name hal_soc->ops->hal_tx_update_ppe_pri2tid =
1505*5113495bSYour Name hal_tx_update_ppe_pri2tid_6432;
1506*5113495bSYour Name hal_soc->ops->hal_tx_dump_ppe_vp_entry = hal_tx_dump_ppe_vp_entry_6432;
1507*5113495bSYour Name hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries =
1508*5113495bSYour Name hal_tx_get_num_ppe_vp_tbl_entries_6432;
1509*5113495bSYour Name hal_soc->ops->hal_tx_enable_pri2tid_map =
1510*5113495bSYour Name hal_tx_enable_pri2tid_map_6432;
1511*5113495bSYour Name hal_soc->ops->hal_tx_config_rbm_mapping_be =
1512*5113495bSYour Name hal_tx_config_rbm_mapping_be_6432;
1513*5113495bSYour Name
1514*5113495bSYour Name /* rx */
1515*5113495bSYour Name hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
1516*5113495bSYour Name hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1517*5113495bSYour Name hal_rx_mon_hw_desc_get_mpdu_status_be;
1518*5113495bSYour Name hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6432;
1519*5113495bSYour Name hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1520*5113495bSYour Name hal_rx_proc_phyrx_other_receive_info_tlv_6432;
1521*5113495bSYour Name
1522*5113495bSYour Name hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6432;
1523*5113495bSYour Name hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1524*5113495bSYour Name hal_rx_dump_mpdu_start_tlv_6432;
1525*5113495bSYour Name hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_6432;
1526*5113495bSYour Name
1527*5113495bSYour Name hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6432;
1528*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
1529*5113495bSYour Name hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1530*5113495bSYour Name hal_rx_tlv_reception_type_get_be;
1531*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1532*5113495bSYour Name hal_rx_msdu_end_da_idx_get_be;
1533*5113495bSYour Name hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1534*5113495bSYour Name hal_rx_msdu_desc_info_get_ptr_6432;
1535*5113495bSYour Name hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1536*5113495bSYour Name hal_rx_link_desc_msdu0_ptr_6432;
1537*5113495bSYour Name hal_soc->ops->hal_reo_status_get_header =
1538*5113495bSYour Name hal_reo_status_get_header_6432;
1539*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
1540*5113495bSYour Name hal_soc->ops->hal_rx_status_get_tlv_info =
1541*5113495bSYour Name hal_rx_status_get_tlv_info_wrapper_be;
1542*5113495bSYour Name #endif
1543*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_info_get =
1544*5113495bSYour Name hal_rx_wbm_err_info_get_generic_be;
1545*5113495bSYour Name hal_soc->ops->hal_tx_set_pcp_tid_map =
1546*5113495bSYour Name hal_tx_set_pcp_tid_map_generic_be;
1547*5113495bSYour Name hal_soc->ops->hal_tx_update_pcp_tid_map =
1548*5113495bSYour Name hal_tx_update_pcp_tid_generic_be;
1549*5113495bSYour Name hal_soc->ops->hal_tx_set_tidmap_prty =
1550*5113495bSYour Name hal_tx_update_tidmap_prty_generic_be;
1551*5113495bSYour Name hal_soc->ops->hal_rx_get_rx_fragment_number =
1552*5113495bSYour Name hal_rx_get_rx_fragment_number_be,
1553*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1554*5113495bSYour Name hal_rx_tlv_da_is_mcbc_get_be;
1555*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
1556*5113495bSYour Name hal_rx_tlv_is_tkip_mic_err_get_be;
1557*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1558*5113495bSYour Name hal_rx_tlv_sa_is_valid_get_be;
1559*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
1560*5113495bSYour Name hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
1561*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1562*5113495bSYour Name hal_rx_tlv_l3_hdr_padding_get_be;
1563*5113495bSYour Name hal_soc->ops->hal_rx_encryption_info_valid =
1564*5113495bSYour Name hal_rx_encryption_info_valid_be;
1565*5113495bSYour Name hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
1566*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1567*5113495bSYour Name hal_rx_tlv_first_msdu_get_be;
1568*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1569*5113495bSYour Name hal_rx_tlv_da_is_valid_get_be;
1570*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1571*5113495bSYour Name hal_rx_tlv_last_msdu_get_be;
1572*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1573*5113495bSYour Name hal_rx_get_mpdu_mac_ad4_valid_be;
1574*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1575*5113495bSYour Name hal_rx_mpdu_start_sw_peer_id_get_be;
1576*5113495bSYour Name hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1577*5113495bSYour Name hal_rx_msdu_peer_meta_data_get_be;
1578*5113495bSYour Name #ifndef CONFIG_WORD_BASED_TLV
1579*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
1580*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1581*5113495bSYour Name hal_rx_mpdu_info_ampdu_flag_get_be;
1582*5113495bSYour Name hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1583*5113495bSYour Name hal_rx_hw_desc_get_ppduid_get_be;
1584*5113495bSYour Name hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
1585*5113495bSYour Name hal_rx_attn_phy_ppdu_id_get_be;
1586*5113495bSYour Name hal_soc->ops->hal_rx_get_filter_category =
1587*5113495bSYour Name hal_rx_get_filter_category_be;
1588*5113495bSYour Name #endif
1589*5113495bSYour Name hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
1590*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
1591*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
1592*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1593*5113495bSYour Name hal_rx_get_mpdu_frame_control_valid_be;
1594*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
1595*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
1596*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
1597*5113495bSYour Name hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1598*5113495bSYour Name hal_rx_get_mpdu_sequence_control_valid_be;
1599*5113495bSYour Name hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
1600*5113495bSYour Name hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
1601*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1602*5113495bSYour Name hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
1603*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1604*5113495bSYour Name hal_rx_msdu_end_sa_sw_peer_id_get_be;
1605*5113495bSYour Name hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1606*5113495bSYour Name hal_rx_msdu0_buffer_addr_lsb_6432;
1607*5113495bSYour Name hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1608*5113495bSYour Name hal_rx_msdu_desc_info_ptr_get_6432;
1609*5113495bSYour Name hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6432;
1610*5113495bSYour Name hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6432;
1611*5113495bSYour Name hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
1612*5113495bSYour Name hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
1613*5113495bSYour Name hal_soc->ops->hal_rx_get_mac_addr2_valid =
1614*5113495bSYour Name hal_rx_get_mac_addr2_valid_be;
1615*5113495bSYour Name hal_soc->ops->hal_reo_config = hal_reo_config_6432;
1616*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
1617*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1618*5113495bSYour Name hal_rx_msdu_flow_idx_invalid_be;
1619*5113495bSYour Name hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1620*5113495bSYour Name hal_rx_msdu_flow_idx_timeout_be;
1621*5113495bSYour Name hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1622*5113495bSYour Name hal_rx_msdu_fse_metadata_get_be;
1623*5113495bSYour Name hal_soc->ops->hal_rx_msdu_cce_match_get =
1624*5113495bSYour Name hal_rx_msdu_cce_match_get_be;
1625*5113495bSYour Name hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1626*5113495bSYour Name hal_rx_msdu_cce_metadata_get_be;
1627*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_flow_params =
1628*5113495bSYour Name hal_rx_msdu_get_flow_params_be;
1629*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
1630*5113495bSYour Name hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
1631*5113495bSYour Name #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1632*5113495bSYour Name hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6432;
1633*5113495bSYour Name hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6432;
1634*5113495bSYour Name #else
1635*5113495bSYour Name hal_soc->ops->hal_rx_get_bb_info = NULL;
1636*5113495bSYour Name hal_soc->ops->hal_rx_get_rtt_info = NULL;
1637*5113495bSYour Name #endif
1638*5113495bSYour Name /* rx - msdu fast path info fields */
1639*5113495bSYour Name hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1640*5113495bSYour Name hal_rx_msdu_packet_metadata_get_generic_be;
1641*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1642*5113495bSYour Name hal_rx_mpdu_start_tlv_tag_valid_be;
1643*5113495bSYour Name hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1644*5113495bSYour Name hal_rx_wbm_err_msdu_continuation_get_6432;
1645*5113495bSYour Name
1646*5113495bSYour Name /* rx - TLV struct offsets */
1647*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_offset_get =
1648*5113495bSYour Name hal_rx_msdu_end_offset_get_generic;
1649*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_offset_get =
1650*5113495bSYour Name hal_rx_mpdu_start_offset_get_generic;
1651*5113495bSYour Name #ifndef NO_RX_PKT_HDR_TLV
1652*5113495bSYour Name hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1653*5113495bSYour Name hal_rx_pkt_tlv_offset_get_generic;
1654*5113495bSYour Name #endif
1655*5113495bSYour Name hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6432;
1656*5113495bSYour Name
1657*5113495bSYour Name hal_soc->ops->hal_rx_flow_get_tuple_info =
1658*5113495bSYour Name hal_rx_flow_get_tuple_info_be;
1659*5113495bSYour Name hal_soc->ops->hal_rx_flow_delete_entry =
1660*5113495bSYour Name hal_rx_flow_delete_entry_be;
1661*5113495bSYour Name hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
1662*5113495bSYour Name hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1663*5113495bSYour Name hal_compute_reo_remap_ix2_ix3_6432;
1664*5113495bSYour Name
1665*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
1666*5113495bSYour Name hal_rx_msdu_get_reo_destination_indication_be;
1667*5113495bSYour Name hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
1668*5113495bSYour Name hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
1669*5113495bSYour Name hal_rx_msdu_is_wlan_mcast_generic_be;
1670*5113495bSYour Name hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_6432;
1671*5113495bSYour Name hal_soc->ops->hal_rx_tlv_decap_format_get =
1672*5113495bSYour Name hal_rx_tlv_decap_format_get_be;
1673*5113495bSYour Name #ifdef RECEIVE_OFFLOAD
1674*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_offload_info =
1675*5113495bSYour Name hal_rx_tlv_get_offload_info_be;
1676*5113495bSYour Name hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
1677*5113495bSYour Name hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
1678*5113495bSYour Name #endif
1679*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_done_get =
1680*5113495bSYour Name hal_rx_tlv_msdu_done_copy_get_6432;
1681*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_len_get =
1682*5113495bSYour Name hal_rx_msdu_start_msdu_len_get_be;
1683*5113495bSYour Name hal_soc->ops->hal_rx_get_frame_ctrl_field =
1684*5113495bSYour Name hal_rx_get_frame_ctrl_field_be;
1685*5113495bSYour Name hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
1686*5113495bSYour Name hal_soc->ops->hal_rx_tlv_msdu_len_set =
1687*5113495bSYour Name hal_rx_msdu_start_msdu_len_set_be;
1688*5113495bSYour Name hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
1689*5113495bSYour Name hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
1690*5113495bSYour Name hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
1691*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
1692*5113495bSYour Name hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
1693*5113495bSYour Name hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1694*5113495bSYour Name hal_rx_tlv_decrypt_err_get_be;
1695*5113495bSYour Name hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
1696*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_is_decrypted =
1697*5113495bSYour Name hal_rx_tlv_get_is_decrypted_be;
1698*5113495bSYour Name hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
1699*5113495bSYour Name hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
1700*5113495bSYour Name hal_soc->ops->hal_rx_priv_info_set_in_tlv =
1701*5113495bSYour Name hal_rx_priv_info_set_in_tlv_be;
1702*5113495bSYour Name hal_soc->ops->hal_rx_priv_info_get_from_tlv =
1703*5113495bSYour Name hal_rx_priv_info_get_from_tlv_be;
1704*5113495bSYour Name hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
1705*5113495bSYour Name hal_soc->ops->hal_reo_setup = hal_reo_setup_6432;
1706*5113495bSYour Name hal_soc->ops->hal_reo_config_reo2ppe_dest_info = NULL;
1707*5113495bSYour Name #ifdef REO_SHARED_QREF_TABLE_EN
1708*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
1709*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
1710*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
1711*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
1712*5113495bSYour Name hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
1713*5113495bSYour Name #endif
1714*5113495bSYour Name /* Overwrite the default BE ops */
1715*5113495bSYour Name hal_soc->ops->hal_get_rx_max_ba_window =
1716*5113495bSYour Name hal_get_rx_max_ba_window_qcn6432;
1717*5113495bSYour Name hal_soc->ops->hal_get_reo_qdesc_size = hal_qcn6432_get_reo_qdesc_size;
1718*5113495bSYour Name /* TX MONITOR */
1719*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_TX_2_0
1720*5113495bSYour Name hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
1721*5113495bSYour Name hal_txmon_is_mon_buf_addr_tlv_generic_be;
1722*5113495bSYour Name hal_soc->ops->hal_txmon_populate_packet_info =
1723*5113495bSYour Name hal_txmon_populate_packet_info_generic_be;
1724*5113495bSYour Name hal_soc->ops->hal_txmon_status_parse_tlv =
1725*5113495bSYour Name hal_txmon_status_parse_tlv_generic_be;
1726*5113495bSYour Name hal_soc->ops->hal_txmon_status_get_num_users =
1727*5113495bSYour Name hal_txmon_status_get_num_users_generic_be;
1728*5113495bSYour Name #if defined(TX_MONITOR_WORD_MASK)
1729*5113495bSYour Name hal_soc->ops->hal_txmon_get_word_mask =
1730*5113495bSYour Name hal_txmon_get_word_mask_qcn6432;
1731*5113495bSYour Name #else
1732*5113495bSYour Name hal_soc->ops->hal_txmon_get_word_mask =
1733*5113495bSYour Name hal_txmon_get_word_mask_generic_be;
1734*5113495bSYour Name #endif /* TX_MONITOR_WORD_MASK */
1735*5113495bSYour Name #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
1736*5113495bSYour Name hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1737*5113495bSYour Name hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
1738*5113495bSYour Name hal_tx_vdev_mismatch_routing_set_generic_be;
1739*5113495bSYour Name hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
1740*5113495bSYour Name hal_tx_mcast_mlo_reinject_routing_set_generic_be;
1741*5113495bSYour Name hal_soc->ops->hal_get_ba_aging_timeout =
1742*5113495bSYour Name hal_get_ba_aging_timeout_be_generic;
1743*5113495bSYour Name hal_soc->ops->hal_setup_link_idle_list =
1744*5113495bSYour Name hal_setup_link_idle_list_generic_be;
1745*5113495bSYour Name hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
1746*5113495bSYour Name hal_cookie_conversion_reg_cfg_generic_be;
1747*5113495bSYour Name hal_soc->ops->hal_set_ba_aging_timeout =
1748*5113495bSYour Name hal_set_ba_aging_timeout_be_generic;
1749*5113495bSYour Name hal_soc->ops->hal_tx_populate_bank_register =
1750*5113495bSYour Name hal_tx_populate_bank_register_be;
1751*5113495bSYour Name hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
1752*5113495bSYour Name hal_tx_vdev_mcast_ctrl_set_be;
1753*5113495bSYour Name #ifdef CONFIG_WORD_BASED_TLV
1754*5113495bSYour Name hal_soc->ops->hal_rx_mpdu_start_wmask_get =
1755*5113495bSYour Name hal_rx_mpdu_start_wmask_get_be;
1756*5113495bSYour Name hal_soc->ops->hal_rx_msdu_end_wmask_get =
1757*5113495bSYour Name hal_rx_msdu_end_wmask_get_be;
1758*5113495bSYour Name #endif
1759*5113495bSYour Name hal_soc->ops->hal_get_tsf2_scratch_reg =
1760*5113495bSYour Name hal_get_tsf2_scratch_reg_qcn6432;
1761*5113495bSYour Name hal_soc->ops->hal_get_tqm_scratch_reg =
1762*5113495bSYour Name hal_get_tqm_scratch_reg_qcn6432;
1763*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_set = hal_tx_ppe2tcl_ring_halt_set_6432;
1764*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_reset =
1765*5113495bSYour Name hal_tx_ppe2tcl_ring_halt_reset_6432;
1766*5113495bSYour Name hal_soc->ops->hal_tx_ring_halt_poll =
1767*5113495bSYour Name hal_tx_ppe2tcl_ring_halt_done_6432;
1768*5113495bSYour Name hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries =
1769*5113495bSYour Name hal_tx_get_num_ppe_vp_search_idx_reg_entries_6432;
1770*5113495bSYour Name };
1771*5113495bSYour Name
1772*5113495bSYour Name struct hal_hw_srng_config hw_srng_table_6432[] = {
1773*5113495bSYour Name /* TODO: max_rings can populated by querying HW capabilities */
1774*5113495bSYour Name { /* REO_DST */
1775*5113495bSYour Name .start_ring_id = HAL_SRNG_REO2SW1,
1776*5113495bSYour Name .max_rings = 8,
1777*5113495bSYour Name .entry_size = sizeof(struct reo_destination_ring) >> 2,
1778*5113495bSYour Name .lmac_ring = FALSE,
1779*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1780*5113495bSYour Name .reg_start = {
1781*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
1782*5113495bSYour Name REO_REG_REG_BASE),
1783*5113495bSYour Name HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
1784*5113495bSYour Name REO_REG_REG_BASE)
1785*5113495bSYour Name },
1786*5113495bSYour Name .reg_size = {
1787*5113495bSYour Name HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
1788*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
1789*5113495bSYour Name HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
1790*5113495bSYour Name HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
1791*5113495bSYour Name },
1792*5113495bSYour Name .max_size =
1793*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
1794*5113495bSYour Name HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
1795*5113495bSYour Name },
1796*5113495bSYour Name { /* REO_EXCEPTION */
1797*5113495bSYour Name /* Designating REO2SW0 ring as exception ring. This ring is
1798*5113495bSYour Name * similar to other REO2SW rings though it is named as REO2SW0.
1799*5113495bSYour Name * Any of theREO2SW rings can be used as exception ring.
1800*5113495bSYour Name */
1801*5113495bSYour Name .start_ring_id = HAL_SRNG_REO2SW0,
1802*5113495bSYour Name .max_rings = 1,
1803*5113495bSYour Name .entry_size = sizeof(struct reo_destination_ring) >> 2,
1804*5113495bSYour Name .lmac_ring = FALSE,
1805*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1806*5113495bSYour Name .reg_start = {
1807*5113495bSYour Name HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
1808*5113495bSYour Name REO_REG_REG_BASE),
1809*5113495bSYour Name HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
1810*5113495bSYour Name REO_REG_REG_BASE)
1811*5113495bSYour Name },
1812*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1813*5113495bSYour Name * type are supported
1814*5113495bSYour Name */
1815*5113495bSYour Name .reg_size = {},
1816*5113495bSYour Name .max_size =
1817*5113495bSYour Name HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
1818*5113495bSYour Name HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
1819*5113495bSYour Name },
1820*5113495bSYour Name { /* REO_REINJECT */
1821*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2REO,
1822*5113495bSYour Name .max_rings = 4,
1823*5113495bSYour Name .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1824*5113495bSYour Name .lmac_ring = FALSE,
1825*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1826*5113495bSYour Name .reg_start = {
1827*5113495bSYour Name HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
1828*5113495bSYour Name REO_REG_REG_BASE),
1829*5113495bSYour Name HWIO_REO_R2_SW2REO_RING_HP_ADDR(
1830*5113495bSYour Name REO_REG_REG_BASE)
1831*5113495bSYour Name },
1832*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1833*5113495bSYour Name * type are supported
1834*5113495bSYour Name */
1835*5113495bSYour Name .reg_size = {
1836*5113495bSYour Name HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
1837*5113495bSYour Name HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
1838*5113495bSYour Name HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
1839*5113495bSYour Name HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
1840*5113495bSYour Name },
1841*5113495bSYour Name .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
1842*5113495bSYour Name HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
1843*5113495bSYour Name },
1844*5113495bSYour Name { /* REO_CMD */
1845*5113495bSYour Name .start_ring_id = HAL_SRNG_REO_CMD,
1846*5113495bSYour Name .max_rings = 1,
1847*5113495bSYour Name .entry_size = (sizeof(struct tlv_32_hdr) +
1848*5113495bSYour Name sizeof(struct reo_get_queue_stats)) >> 2,
1849*5113495bSYour Name .lmac_ring = FALSE,
1850*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1851*5113495bSYour Name .reg_start = {
1852*5113495bSYour Name HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
1853*5113495bSYour Name REO_REG_REG_BASE),
1854*5113495bSYour Name HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
1855*5113495bSYour Name REO_REG_REG_BASE),
1856*5113495bSYour Name },
1857*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1858*5113495bSYour Name * type are supported
1859*5113495bSYour Name */
1860*5113495bSYour Name .reg_size = {},
1861*5113495bSYour Name .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1862*5113495bSYour Name HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1863*5113495bSYour Name },
1864*5113495bSYour Name { /* REO_STATUS */
1865*5113495bSYour Name .start_ring_id = HAL_SRNG_REO_STATUS,
1866*5113495bSYour Name .max_rings = 1,
1867*5113495bSYour Name .entry_size = (sizeof(struct tlv_32_hdr) +
1868*5113495bSYour Name sizeof(struct reo_get_queue_stats_status)) >> 2,
1869*5113495bSYour Name .lmac_ring = FALSE,
1870*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1871*5113495bSYour Name .reg_start = {
1872*5113495bSYour Name HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
1873*5113495bSYour Name REO_REG_REG_BASE),
1874*5113495bSYour Name HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
1875*5113495bSYour Name REO_REG_REG_BASE),
1876*5113495bSYour Name },
1877*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1878*5113495bSYour Name * type are supported
1879*5113495bSYour Name */
1880*5113495bSYour Name .reg_size = {},
1881*5113495bSYour Name .max_size =
1882*5113495bSYour Name HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1883*5113495bSYour Name HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1884*5113495bSYour Name },
1885*5113495bSYour Name { /* TCL_DATA */
1886*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2TCL1,
1887*5113495bSYour Name .max_rings = 6,
1888*5113495bSYour Name .entry_size = sizeof(struct tcl_data_cmd) >> 2,
1889*5113495bSYour Name .lmac_ring = FALSE,
1890*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1891*5113495bSYour Name .reg_start = {
1892*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
1893*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1894*5113495bSYour Name HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
1895*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1896*5113495bSYour Name },
1897*5113495bSYour Name .reg_size = {
1898*5113495bSYour Name HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
1899*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
1900*5113495bSYour Name HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
1901*5113495bSYour Name HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
1902*5113495bSYour Name },
1903*5113495bSYour Name .max_size =
1904*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
1905*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
1906*5113495bSYour Name },
1907*5113495bSYour Name { /* TCL_CMD/CREDIT */
1908*5113495bSYour Name /* qca8074v2 and qcn6432 uses this ring for data commands */
1909*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2TCL_CMD,
1910*5113495bSYour Name .max_rings = 1,
1911*5113495bSYour Name .entry_size = sizeof(struct tcl_data_cmd) >> 2,
1912*5113495bSYour Name .lmac_ring = FALSE,
1913*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1914*5113495bSYour Name .reg_start = {
1915*5113495bSYour Name HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
1916*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1917*5113495bSYour Name HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
1918*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1919*5113495bSYour Name },
1920*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1921*5113495bSYour Name * type are supported
1922*5113495bSYour Name */
1923*5113495bSYour Name .reg_size = {},
1924*5113495bSYour Name .max_size =
1925*5113495bSYour Name HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
1926*5113495bSYour Name HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
1927*5113495bSYour Name },
1928*5113495bSYour Name { /* TCL_STATUS */
1929*5113495bSYour Name .start_ring_id = HAL_SRNG_TCL_STATUS,
1930*5113495bSYour Name .max_rings = 1,
1931*5113495bSYour Name .entry_size = (sizeof(struct tlv_32_hdr) +
1932*5113495bSYour Name sizeof(struct tcl_status_ring)) >> 2,
1933*5113495bSYour Name .lmac_ring = FALSE,
1934*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
1935*5113495bSYour Name .reg_start = {
1936*5113495bSYour Name HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
1937*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1938*5113495bSYour Name HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
1939*5113495bSYour Name MAC_TCL_REG_REG_BASE),
1940*5113495bSYour Name },
1941*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
1942*5113495bSYour Name * type are supported
1943*5113495bSYour Name */
1944*5113495bSYour Name .reg_size = {},
1945*5113495bSYour Name .max_size =
1946*5113495bSYour Name HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
1947*5113495bSYour Name HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
1948*5113495bSYour Name },
1949*5113495bSYour Name { /* CE_SRC */
1950*5113495bSYour Name .start_ring_id = HAL_SRNG_CE_0_SRC,
1951*5113495bSYour Name .max_rings = 16,
1952*5113495bSYour Name .entry_size = sizeof(struct ce_src_desc) >> 2,
1953*5113495bSYour Name .lmac_ring = FALSE,
1954*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1955*5113495bSYour Name .reg_start = {
1956*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
1957*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
1958*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
1959*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
1960*5113495bSYour Name },
1961*5113495bSYour Name .reg_size = {
1962*5113495bSYour Name WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
1963*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
1964*5113495bSYour Name WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
1965*5113495bSYour Name WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
1966*5113495bSYour Name },
1967*5113495bSYour Name .max_size =
1968*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
1969*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
1970*5113495bSYour Name },
1971*5113495bSYour Name { /* CE_DST */
1972*5113495bSYour Name .start_ring_id = HAL_SRNG_CE_0_DST,
1973*5113495bSYour Name .max_rings = 16,
1974*5113495bSYour Name .entry_size = 8 >> 2,
1975*5113495bSYour Name /*TODO: entry_size above should actually be
1976*5113495bSYour Name * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
1977*5113495bSYour Name * of struct ce_dst_desc in HW header files
1978*5113495bSYour Name */
1979*5113495bSYour Name .lmac_ring = FALSE,
1980*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
1981*5113495bSYour Name .reg_start = {
1982*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1983*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1984*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1985*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1986*5113495bSYour Name },
1987*5113495bSYour Name .reg_size = {
1988*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1989*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1990*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1991*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1992*5113495bSYour Name },
1993*5113495bSYour Name .max_size =
1994*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1995*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1996*5113495bSYour Name },
1997*5113495bSYour Name { /* CE_DST_STATUS */
1998*5113495bSYour Name .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
1999*5113495bSYour Name .max_rings = 16,
2000*5113495bSYour Name .entry_size = sizeof(struct ce_stat_desc) >> 2,
2001*5113495bSYour Name .lmac_ring = FALSE,
2002*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2003*5113495bSYour Name .reg_start = {
2004*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
2005*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
2006*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
2007*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
2008*5113495bSYour Name },
2009*5113495bSYour Name /* TODO: check destination status ring registers */
2010*5113495bSYour Name .reg_size = {
2011*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
2012*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
2013*5113495bSYour Name WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
2014*5113495bSYour Name WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
2015*5113495bSYour Name },
2016*5113495bSYour Name .max_size =
2017*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2018*5113495bSYour Name HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2019*5113495bSYour Name },
2020*5113495bSYour Name { /* WBM_IDLE_LINK */
2021*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
2022*5113495bSYour Name .max_rings = 1,
2023*5113495bSYour Name .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
2024*5113495bSYour Name .lmac_ring = FALSE,
2025*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2026*5113495bSYour Name .reg_start = {
2027*5113495bSYour Name HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
2028*5113495bSYour Name HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
2029*5113495bSYour Name },
2030*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
2031*5113495bSYour Name * type are supported
2032*5113495bSYour Name */
2033*5113495bSYour Name .reg_size = {},
2034*5113495bSYour Name .max_size =
2035*5113495bSYour Name HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
2036*5113495bSYour Name HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
2037*5113495bSYour Name },
2038*5113495bSYour Name { /* SW2WBM_RELEASE */
2039*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
2040*5113495bSYour Name .max_rings = 1,
2041*5113495bSYour Name .entry_size = sizeof(struct wbm_release_ring) >> 2,
2042*5113495bSYour Name .lmac_ring = FALSE,
2043*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2044*5113495bSYour Name .reg_start = {
2045*5113495bSYour Name HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
2046*5113495bSYour Name HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
2047*5113495bSYour Name },
2048*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
2049*5113495bSYour Name * type are supported
2050*5113495bSYour Name */
2051*5113495bSYour Name .reg_size = {},
2052*5113495bSYour Name .max_size =
2053*5113495bSYour Name HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2054*5113495bSYour Name HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2055*5113495bSYour Name },
2056*5113495bSYour Name { /* WBM2SW_RELEASE */
2057*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
2058*5113495bSYour Name .max_rings = 8,
2059*5113495bSYour Name .entry_size = sizeof(struct wbm_release_ring) >> 2,
2060*5113495bSYour Name .lmac_ring = FALSE,
2061*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2062*5113495bSYour Name .reg_start = {
2063*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
2064*5113495bSYour Name WBM_REG_REG_BASE),
2065*5113495bSYour Name HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
2066*5113495bSYour Name WBM_REG_REG_BASE),
2067*5113495bSYour Name },
2068*5113495bSYour Name .reg_size = {
2069*5113495bSYour Name HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
2070*5113495bSYour Name WBM_REG_REG_BASE) -
2071*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
2072*5113495bSYour Name WBM_REG_REG_BASE),
2073*5113495bSYour Name HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
2074*5113495bSYour Name WBM_REG_REG_BASE) -
2075*5113495bSYour Name HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
2076*5113495bSYour Name WBM_REG_REG_BASE),
2077*5113495bSYour Name },
2078*5113495bSYour Name .max_size =
2079*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2080*5113495bSYour Name HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2081*5113495bSYour Name },
2082*5113495bSYour Name { /* RXDMA_BUF */
2083*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
2084*5113495bSYour Name #ifdef IPA_OFFLOAD
2085*5113495bSYour Name .max_rings = 3,
2086*5113495bSYour Name #else
2087*5113495bSYour Name .max_rings = 3,
2088*5113495bSYour Name #endif
2089*5113495bSYour Name .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2090*5113495bSYour Name .lmac_ring = TRUE,
2091*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2092*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2093*5113495bSYour Name * from host
2094*5113495bSYour Name */
2095*5113495bSYour Name .reg_start = {},
2096*5113495bSYour Name .reg_size = {},
2097*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
2098*5113495bSYour Name },
2099*5113495bSYour Name { /* RXDMA_DST */
2100*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
2101*5113495bSYour Name .max_rings = 0,
2102*5113495bSYour Name .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
2103*5113495bSYour Name .lmac_ring = TRUE,
2104*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2105*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2106*5113495bSYour Name * from host
2107*5113495bSYour Name */
2108*5113495bSYour Name .reg_start = {},
2109*5113495bSYour Name .reg_size = {},
2110*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
2111*5113495bSYour Name },
2112*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
2113*5113495bSYour Name { /* RXDMA_MONITOR_BUF */
2114*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
2115*5113495bSYour Name .max_rings = 1,
2116*5113495bSYour Name .entry_size = sizeof(struct mon_ingress_ring) >> 2,
2117*5113495bSYour Name .lmac_ring = TRUE,
2118*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2119*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2120*5113495bSYour Name * from host
2121*5113495bSYour Name */
2122*5113495bSYour Name .reg_start = {},
2123*5113495bSYour Name .reg_size = {},
2124*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2125*5113495bSYour Name },
2126*5113495bSYour Name #else
2127*5113495bSYour Name {},
2128*5113495bSYour Name #endif
2129*5113495bSYour Name { /* RXDMA_MONITOR_STATUS */
2130*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
2131*5113495bSYour Name .max_rings = 0,
2132*5113495bSYour Name .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2133*5113495bSYour Name .lmac_ring = TRUE,
2134*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2135*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2136*5113495bSYour Name * from host
2137*5113495bSYour Name */
2138*5113495bSYour Name .reg_start = {},
2139*5113495bSYour Name .reg_size = {},
2140*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
2141*5113495bSYour Name },
2142*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_RX_2_0
2143*5113495bSYour Name { /* RXDMA_MONITOR_DST */
2144*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
2145*5113495bSYour Name .max_rings = 2,
2146*5113495bSYour Name .entry_size = sizeof(struct mon_destination_ring) >> 2,
2147*5113495bSYour Name .lmac_ring = TRUE,
2148*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2149*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2150*5113495bSYour Name * from host
2151*5113495bSYour Name */
2152*5113495bSYour Name .reg_start = {},
2153*5113495bSYour Name .reg_size = {},
2154*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2155*5113495bSYour Name },
2156*5113495bSYour Name #else
2157*5113495bSYour Name {},
2158*5113495bSYour Name #endif
2159*5113495bSYour Name { /* RXDMA_MONITOR_DESC */
2160*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2161*5113495bSYour Name .max_rings = 0,
2162*5113495bSYour Name .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
2163*5113495bSYour Name .lmac_ring = TRUE,
2164*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2165*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2166*5113495bSYour Name * from host
2167*5113495bSYour Name */
2168*5113495bSYour Name .reg_start = {},
2169*5113495bSYour Name .reg_size = {},
2170*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2171*5113495bSYour Name },
2172*5113495bSYour Name
2173*5113495bSYour Name { /* DIR_BUF_RX_DMA_SRC */
2174*5113495bSYour Name .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2175*5113495bSYour Name /* one ring for spectral and one ring for cfr */
2176*5113495bSYour Name .max_rings = 2,
2177*5113495bSYour Name .entry_size = 2,
2178*5113495bSYour Name .lmac_ring = TRUE,
2179*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2180*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2181*5113495bSYour Name * from host
2182*5113495bSYour Name */
2183*5113495bSYour Name .reg_start = {},
2184*5113495bSYour Name .reg_size = {},
2185*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE,
2186*5113495bSYour Name },
2187*5113495bSYour Name #ifdef WLAN_FEATURE_CIF_CFR
2188*5113495bSYour Name { /* WIFI_POS_SRC */
2189*5113495bSYour Name .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2190*5113495bSYour Name .max_rings = 1,
2191*5113495bSYour Name .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2192*5113495bSYour Name .lmac_ring = TRUE,
2193*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2194*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2195*5113495bSYour Name * from host
2196*5113495bSYour Name */
2197*5113495bSYour Name .reg_start = {},
2198*5113495bSYour Name .reg_size = {},
2199*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2200*5113495bSYour Name },
2201*5113495bSYour Name #endif
2202*5113495bSYour Name { /* REO2PPE */
2203*5113495bSYour Name .start_ring_id = HAL_SRNG_REO2PPE,
2204*5113495bSYour Name .max_rings = 1,
2205*5113495bSYour Name .entry_size = sizeof(struct reo_destination_ring) >> 2,
2206*5113495bSYour Name .lmac_ring = FALSE,
2207*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2208*5113495bSYour Name .reg_start = {
2209*5113495bSYour Name HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(
2210*5113495bSYour Name REO_REG_REG_BASE),
2211*5113495bSYour Name HWIO_REO_R2_REO2PPE_RING_HP_ADDR(
2212*5113495bSYour Name REO_REG_REG_BASE),
2213*5113495bSYour Name },
2214*5113495bSYour Name /* Single ring - provide ring size if multiple rings of this
2215*5113495bSYour Name * type are supported
2216*5113495bSYour Name */
2217*5113495bSYour Name .reg_size = {},
2218*5113495bSYour Name .max_size =
2219*5113495bSYour Name HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >>
2220*5113495bSYour Name HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT,
2221*5113495bSYour Name },
2222*5113495bSYour Name { /* PPE2TCL */
2223*5113495bSYour Name .start_ring_id = HAL_SRNG_PPE2TCL1,
2224*5113495bSYour Name .max_rings = 1,
2225*5113495bSYour Name .entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2,
2226*5113495bSYour Name .lmac_ring = FALSE,
2227*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2228*5113495bSYour Name .reg_start = {
2229*5113495bSYour Name HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(
2230*5113495bSYour Name MAC_TCL_REG_REG_BASE),
2231*5113495bSYour Name HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(
2232*5113495bSYour Name MAC_TCL_REG_REG_BASE),
2233*5113495bSYour Name },
2234*5113495bSYour Name .reg_size = {},
2235*5113495bSYour Name .max_size =
2236*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
2237*5113495bSYour Name HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
2238*5113495bSYour Name },
2239*5113495bSYour Name { /* PPE_RELEASE */
2240*5113495bSYour Name .start_ring_id = HAL_SRNG_WBM_PPE_RELEASE,
2241*5113495bSYour Name .max_rings = 1,
2242*5113495bSYour Name .entry_size = sizeof(struct wbm_release_ring) >> 2,
2243*5113495bSYour Name .lmac_ring = FALSE,
2244*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2245*5113495bSYour Name },
2246*5113495bSYour Name #ifdef WLAN_PKT_CAPTURE_TX_2_0
2247*5113495bSYour Name { /* TX_MONITOR_BUF */
2248*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
2249*5113495bSYour Name .max_rings = 1,
2250*5113495bSYour Name .entry_size = sizeof(struct mon_ingress_ring) >> 2,
2251*5113495bSYour Name .lmac_ring = TRUE,
2252*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2253*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2254*5113495bSYour Name * from host
2255*5113495bSYour Name */
2256*5113495bSYour Name .reg_start = {},
2257*5113495bSYour Name .reg_size = {},
2258*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2259*5113495bSYour Name },
2260*5113495bSYour Name { /* TX_MONITOR_DST */
2261*5113495bSYour Name .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
2262*5113495bSYour Name .max_rings = 2,
2263*5113495bSYour Name .entry_size = sizeof(struct mon_destination_ring) >> 2,
2264*5113495bSYour Name .lmac_ring = TRUE,
2265*5113495bSYour Name .ring_dir = HAL_SRNG_DST_RING,
2266*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2267*5113495bSYour Name * from host
2268*5113495bSYour Name */
2269*5113495bSYour Name .reg_start = {},
2270*5113495bSYour Name .reg_size = {},
2271*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2272*5113495bSYour Name },
2273*5113495bSYour Name #else
2274*5113495bSYour Name {},
2275*5113495bSYour Name {},
2276*5113495bSYour Name #endif
2277*5113495bSYour Name { /* SW2RXDMA */
2278*5113495bSYour Name .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
2279*5113495bSYour Name .max_rings = 3,
2280*5113495bSYour Name .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2281*5113495bSYour Name .lmac_ring = TRUE,
2282*5113495bSYour Name .ring_dir = HAL_SRNG_SRC_RING,
2283*5113495bSYour Name /* reg_start is not set because LMAC rings are not accessed
2284*5113495bSYour Name * from host
2285*5113495bSYour Name */
2286*5113495bSYour Name .reg_start = {},
2287*5113495bSYour Name .reg_size = {},
2288*5113495bSYour Name .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2289*5113495bSYour Name .dmac_cmn_ring = TRUE,
2290*5113495bSYour Name },
2291*5113495bSYour Name { /* SW2RXDMA_LINK_RELEASE */ 0},
2292*5113495bSYour Name };
2293*5113495bSYour Name
2294*5113495bSYour Name /**
2295*5113495bSYour Name * hal_srng_hw_reg_offset_init_qcn6432() - Initialize the HW srng reg offset
2296*5113495bSYour Name * applicable only for qcn6432
2297*5113495bSYour Name * @hal_soc: HAL Soc handle
2298*5113495bSYour Name *
2299*5113495bSYour Name * Return: None
2300*5113495bSYour Name */
hal_srng_hw_reg_offset_init_qcn6432(struct hal_soc * hal_soc)2301*5113495bSYour Name static inline void hal_srng_hw_reg_offset_init_qcn6432(struct hal_soc *hal_soc)
2302*5113495bSYour Name {
2303*5113495bSYour Name int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2304*5113495bSYour Name
2305*5113495bSYour Name hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
2306*5113495bSYour Name hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
2307*5113495bSYour Name hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
2308*5113495bSYour Name hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
2309*5113495bSYour Name REG_OFFSET(DST, PRODUCER_INT2_SETUP);
2310*5113495bSYour Name }
2311*5113495bSYour Name
2312*5113495bSYour Name /*
2313*5113495bSYour Name * hal_reo_config_reo2ppe_dest_info_6432() - Configure reo2ppe dest info
2314*5113495bSYour Name * @hal_soc_hdl: HAL SoC Context
2315*5113495bSYour Name *
2316*5113495bSYour Name * Return: None.
2317*5113495bSYour Name */
2318*5113495bSYour Name static inline
hal_reo_config_reo2ppe_dest_info_6432(hal_soc_handle_t hal_soc_hdl)2319*5113495bSYour Name void hal_reo_config_reo2ppe_dest_info_6432(hal_soc_handle_t hal_soc_hdl)
2320*5113495bSYour Name {
2321*5113495bSYour Name HAL_REG_WRITE((struct hal_soc *)hal_soc_hdl,
2322*5113495bSYour Name HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(REO_REG_REG_BASE),
2323*5113495bSYour Name REO2PPE_RULE_FAIL_FB);
2324*5113495bSYour Name }
2325*5113495bSYour Name
hal_hw_txrx_ops_override_qcn6432(struct hal_soc * hal_soc)2326*5113495bSYour Name static void hal_hw_txrx_ops_override_qcn6432(struct hal_soc *hal_soc)
2327*5113495bSYour Name {
2328*5113495bSYour Name hal_soc->ops->hal_reo_config_reo2ppe_dest_info =
2329*5113495bSYour Name hal_reo_config_reo2ppe_dest_info_6432;
2330*5113495bSYour Name
2331*5113495bSYour Name hal_soc->ops->hal_get_tsf2_scratch_reg =
2332*5113495bSYour Name hal_get_tsf2_scratch_reg_qcn6432;
2333*5113495bSYour Name hal_soc->ops->hal_get_tqm_scratch_reg =
2334*5113495bSYour Name hal_get_tqm_scratch_reg_qcn6432;
2335*5113495bSYour Name }
2336*5113495bSYour Name
2337*5113495bSYour Name /**
2338*5113495bSYour Name * hal_qcn6432_attach()- Attach 6432 target specific hal_soc ops,
2339*5113495bSYour Name * offset and srng table
2340*5113495bSYour Name * @hal_soc: hal_soc handle
2341*5113495bSYour Name *
2342*5113495bSYour Name * Return: void
2343*5113495bSYour Name */
hal_qcn6432_attach(struct hal_soc * hal_soc)2344*5113495bSYour Name void hal_qcn6432_attach(struct hal_soc *hal_soc)
2345*5113495bSYour Name {
2346*5113495bSYour Name hal_soc->hw_srng_table = hw_srng_table_6432;
2347*5113495bSYour Name
2348*5113495bSYour Name hal_srng_hw_reg_offset_init_generic(hal_soc);
2349*5113495bSYour Name hal_srng_hw_reg_offset_init_qcn6432(hal_soc);
2350*5113495bSYour Name
2351*5113495bSYour Name hal_hw_txrx_default_ops_attach_be(hal_soc);
2352*5113495bSYour Name hal_hw_txrx_ops_attach_qcn6432(hal_soc);
2353*5113495bSYour Name hal_soc->dmac_cmn_src_rxbuf_ring = true;
2354*5113495bSYour Name if (hal_soc->static_window_map)
2355*5113495bSYour Name hal_write_window_register(hal_soc);
2356*5113495bSYour Name hal_hw_txrx_ops_override_qcn6432(hal_soc);
2357*5113495bSYour Name }
2358